JPH0683020B2 - Digital filter reset device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset device for a digital filter used in a digital circuit.

Prior Art FIG. 5 shows the configuration of a conventional digital filter. Fifth
In the figure, 51 is an n-stage delay element, 52 is a reset terminal for resetting the delay element 51, 53 is an adder, A is an input signal from the outside, B is an output signal to the outside, and D is an output of the delay element 51. A signal, e is a reset signal.

This circuit adds the external input signal A and the output signal D of the delay element 51 by the adder 53, and is a digital filter having a comb-shaped transfer characteristic. In the conventional technology, as a means for resetting this filter, the delay element 51 has a reset terminal.
A method has been used in which the delay element 51 is provided with 52 and the reset signal e is input to reset all stages of the delay element 51 to reset the filter.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the configuration described above, the n-stage delay element 51 needs to include the reset terminal 52. However, the delay element including the reset terminal does not include the reset element 52. When the circuit scale is larger than that of a delay element that is not provided and therefore the number of stages n of the delay elements is large or when a circuit configuration for processing multiple bits in parallel is used, the delay elements occupy most of the circuit scale. The use of the delay element having the reset terminal has a drawback that the circuit scale becomes considerably large.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems, and to provide a reset device of a digital filter that can perform reset even if a delay element that does not have a reset terminal is used.

Means for Solving the Problems To achieve this object, the present invention comprises at least n stages of delay elements and an output control terminal for controlling whether the input is output as it is or the output is reset regardless of the input. Switch circuit, an adder for adding the output of the switch circuit and an external input signal, a counter for counting n stages, and a reset circuit for receiving the output of the counter and outputting a reset signal to the switch circuit It is configured with and.

Operation According to the present invention, when all the delay elements in the n stages are reset by the above configuration, the cleared signal is output to the adder until the signal is output after n clocks. Therefore, the delay element is not reset, a switch circuit is provided between the adder and the delay element, and the output of the delay element is allowed to pass as it is in normal operation, and the output of the delay element is blocked during the n clock period when the reset signal is input. By outputting the cleared signal, the same signal as when the delay element is reset can be output to the adder. The present invention utilizes this principle to reset a comb digital filter using a delay element having no reset terminal.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, 11 is an n-stage delay element that delays the external input signal A, 12 is a switch circuit that inputs the output of the delay element 11 and switches the output by the input of the output control terminal 13, and 13 is a switch circuit 12. An output control terminal, 14 is an adder for adding the external input signal A and the output D of the switch circuit 12, 15 is a counter for counting a time equal to the delay time of the delay element 11, 16 is an input for the output of the counter 15, and a switch The reset circuit outputs a reset signal to the output control terminal 13 of the circuit 12.

The operation will be described below with reference to FIG.

In FIG. 1, the switch circuit 12 is an n-stage delay element in normal operation.
The output signal C from 11 is passed as it is, and the switch circuit
Twelve output signals D are input to the adder 14.

When the reset signal e is input to the counter 15, the counter 15
Starts counting n stages and outputs a counter output signal f to the reset circuit 16. When the counting of the nth stage is completed, the counter 15 finishes its operation and stops, and finishes outputting the counter output signal f.

The reset circuit 16 outputs the reset signal g to the output control terminal 13 that clears the output signal D of the switch circuit 12 while the counter output signal f is being input.

While the reset signal g is input to the output control terminal 13, the switch circuit 12 does not pass the output signal C of the delay element 11, and the cleared signal is the output signal D of the switch circuit 12.
Output as. Therefore, the output signal D of the switch circuit 12 at this time is equal to the delay element output signal D when the delay element 51 shown in FIG. 5 is reset, and the reset is completed.

FIG. 2 shows an example of the counter 15. This is the configuration when n = 4. OR gate when reset signal e becomes "1"
The output of 24 becomes "1" and this is input to the half adder 22, and the counting starts. When both outputs of the D flip-flop 21 become "1", the output of the NAND gate 23 becomes "0", and if the reset signal e has already returned to "0", the output of the OR gate 24 becomes "0". Next stops counting. In this circuit, the output of the OR gate 24 becomes "1" only when the counting operation is being performed, so that this is used as the counter output signal f.

FIG. 3 shows an example of the reset circuit 16. In order to clear the output signal D of the switch circuit 12, a negative logic reset signal g must be input to the output control terminal 13,
The counter output signal f is inverted by the NOT gate 31, and the output is used as the reset signal g.

FIG. 4 shows an example of the switch circuit 12. When the reset signal g is "1", the delay element output signal C is output as it is, and when the reset signal g becomes "0", the output is always "0", and the AND gate 41 is used. ing.

EFFECTS OF THE INVENTION The present invention makes it possible to reset a comb-shaped digital filter configured by using a delay element having no reset terminal by using a counter, a reset circuit and a switch circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a reset device for a comb-shaped digital filter according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a counter shown in FIG. 1, and FIG. 3 is a reset circuit shown in FIG. FIG. 4 is a circuit diagram of the switch circuit shown in FIG. 1, and FIG. 5 is a block diagram of a conventional example. 11 …… n-stage delay element, 12 …… switch circuit, 13 …… output control terminal, 14 …… adder, 15 …… counter, 16 …… reset circuit, 21 …… D-type flip-flop, 22 …… half Adder, 23 …… NAND gate, 24 …… OR gate, 31 …… NOT gate, 41 …… AND gate.

Claims (1)

[Claims] 1. An n-stage delay element for delaying at least an external input signal, and an output of the n-stage delay element as inputs, and outputs the input as it is according to an input signal to an output control terminal, or inputs the same. A switch circuit for controlling whether to reset the output regardless of the above, an adder for adding the external input signal and the output of the switch circuit, and a counter for counting a time equal to the delay time of the n-stage delay element. A reset circuit for receiving the output of the counter and outputting a reset signal to the output control terminal of the switch circuit.