JPH0683039B2 - comparator - Google Patents

Description

The present invention relates to a comparator used in an A / D converter or the like, and more particularly to a comparator that determines whether or not the potential difference between two input signals exceeds a certain value. .

[Conventional technology]

Conventionally, when quantizing the potential difference between two inputs with an A / D converter, as shown in FIG. 2, the potential difference between the two inputs is converted into a voltage with respect to the ground potential and input to a conventional comparator to be connected to the ground potential. The method used was to compare with a reference potential given to the. In FIG. 2, 21 to 24 are resistors, 25 is an operational amplifier, 26 is a conventional comparator, 27 is a reference voltage source, and 2 is a reference voltage source.
Reference numerals 8 and 29 are input terminals. The resistors 21 to 24 and the operational amplifier 25 form a differential amplifier and convert the potential difference between the input terminals 28 and 29 into a voltage between the point P and the ground potential. The comparator 26 compares this with the voltage of the reference voltage source 27 to quantize the input potential difference.

[Problems to be solved by the invention]

The above-described conventional quantizer has drawbacks such as a large scale, limited accuracy in the conversion circuit, and a finite input impedance (a drive source is restricted).

An object of the present invention is to provide a comparator that solves the above problems.

[Means for solving problems]

The present invention is a four MOS transistor having a load circuit including a current mirror circuit composed of two MOS transistors, the sources of which are connected to a common current source. The drains of first and second MOS transistors are the current mirror. 3rd and 4th MO connected to the primary side of the load circuit by the circuit
The drain of the S transistor is connected to the secondary side of the load circuit formed by the current mirror circuit, and the reference voltage source connected to the gate of the second MOS transistor and the reference voltage source connected to the gate of the third MOS transistor are connected. The comparator is characterized in that it outputs a comparison result of an input signal connected to the gate of the first MOS transistor and an input signal connected to the gate of the MOS transistor by using two reference values.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. In the figure, 1 to 4 are n-type MOS transistors, 5 and 6 are p-type MOS transistors 7 forming a current mirror circuit which is a load circuit, a constant current source, 8 and 9 are reference voltage sources, and 10 and 11 are input terminals. , 12
Is an output terminal.

The present invention uses four MOs whose sources are connected to a common constant current source 7.
Of the S transistors 1 to 4, two MOS transistors 1,
2 drain to MOS transistor 5 and the other two
The drains of the MOS transistors 3 and 4 are connected to the MOS transistor 6.

In the embodiment, the potentials of the input terminals 10 and 11 are respectively V ₁ and
The voltages of V ₂ and the reference voltage sources 8 and 9 are Vr1 and Vr2, respectively. MO
When S transistor 1-4 of the same characteristics, MOS transistor 6 is V1 + Vr1> V2 + Vr2 in resistance _{region, V 1 + Vr 1 <V} 2 + Vr 2
It becomes the interruption area. That is, since the drain current of the MOS transistor is determined by the gate-source voltage, the sources of the MOS transistors 1 to 4 have the same potential, so that the drain current is determined only by the gate potential of each. Therefore, the current flowing through the primary side of the load circuit by the current mirror circuit (sum of drain currents of the MOS transistors 1 and 2) is i5 and the current flowing through the secondary side of the load circuit by the current mirror circuit (of the MOS transistors 3 and 4). If the sum of drain currents) is i6, then if V1 + Vr1> V2 + Vr2, then i5> i6 and V1 + Vr1 <V2
If + Vr2, then i5 <i6. As a result, the current mirror circuit
Since MOS transistor 6 can be in the saturation region (which is synonymous with the active region in the bipolar transistor) only under the condition of i5 = i6, if V1 + Vr1> V2 + Vr2, the MOS transistor 6 is in the resistance (linear) region (same as the saturation region in the bipolar transistor). ), And if V1 + Vr1 <V2 + Vr2, the MOS transistor 6 shifts to the cutoff region. Therefore, the present circuit can quantize by comparing the potential difference (V ₁ −V ₂ ) between the input terminals 10 and 11 with the threshold value (Vr ₁ −Vr ₂ ). At this time, since the input terminals 10 and 11 are connected only to the gate of the MOS transistor, almost no power is taken from the driving source.

〔The invention's effect〕

As described above, according to the present invention, there is an effect that the potential difference between two points can be detected by a simple circuit without taking electric power from the driving source and compared with an arbitrary reference voltage to be quantized.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a configuration example of a quantizer using a conventional comparator. 1,2,3,4 …… n type MOS transistor 5,6 …… p type MOS transistor 7 …… constant current source, 8,9 …… reference voltage source 10,11 …… input terminal, 12 …… output terminal

Claims (1)

[Claims] 1. A load circuit comprising a current mirror circuit composed of two MOS transistors, the four MOS transistors having sources connected to a common current source, wherein drains of first and second MOS transistors are connected to the current source. Connected to the primary side of the load circuit by the mirror circuit, and connecting the drains of the third and fourth MOS transistors to the secondary side of the load circuit by the current mirror circuit,
A first reference voltage source connected to the gate of the second MOS transistor and a second reference voltage source connected to the gate of the third MOS transistor are used to connect the first reference voltage source to the gate of the first MOS transistor. A comparator which outputs a comparison result between an input signal and a second input signal connected to the gate of the fourth MOS transistor.