JPH0683052B2 - 3-state circuit - Google Patents

Description

The present invention relates to a three-state circuit using complementary MOS transistors (hereinafter referred to as CMOS transistors).

[Conventional technology]

FIGS. 3 and 4 show the circuit configuration of a conventional 3-state circuit.

The DATA signal is connected to the gate of the 2-input NAND circuit, and the output of the 2-input NAND circuit is the same as the gate of the P-type MOS transistor of the output CMOS inversion circuit (hereinafter referred to as the output inverter), and the output of the 2-input NOR circuit is N-type MOS of output inverter
It is connected to the gate of the transistor.

The other gate of the 2-input NAND circuit has an output enable signal (hereinafter referred to as OE signal) connected to the gate of the 2-input NAND circuit as an output control signal, and the gate of the 2-input NOR circuit has The inverted signal ▲ ▼ is connected.

[Problems to be solved by the invention]

Conventionally, a 3-state circuit has an output inverter and its P-type
2 inputs N for MOS transistor gate control
As gate control of ANDN type MOS transistor,
You are using a 2-input NOR. In other words, if the IC has a 3-state terminal, then 10 MOS transistor elements must be used. Every year, LSIs such as CPUs are being highly integrated, and the number of terminals is increasing and the number of 3-state terminals is also increasing, so the effect on the chip size cannot be ignored. In particular, the output transistor has a large load and thus has a large channel width.
The channel width of the input NAND and the input 2 NOR must be increased inevitably, and the area occupied by the chip becomes larger than other internal circuits, and there are many 3-state terminals.
IC is a disadvantage.

In addition, since the number of I / O terminals in the gate array has increased recently and the area occupied by the 3-State circuit has increased, many functions must be provided with the number of elements set in one chip. It is a disadvantage.

An object of the present invention is to provide a three-state circuit in which the occupied area is reduced by reducing the number of MOS transistor elements.

[Means for solving problems]

According to the present invention, a 2-input NAND N-type MO that is a gate control circuit of a P-type MOS transistor of an output inverter.
Remove one S transistor (MOS transistor for DATA signal)
▼ Connect to the signal. Also, remove one 2-type NOR P-type MOS transistor (DATA signal transistor).
▲ ▼ the source side of the remaining P-type MOS transistor
By connecting to the signal, the input signal OE, ▲
A three-state circuit having ▼ (inversion signal of OE), DATA, and ▲ ▼ (inversion signal of DATA) is obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a three-state circuit according to the first embodiment of the present invention. In the figure, OE, ▲ ▼ (inverted signal of OE), DATA, ▲ ▼ (inverted signal of DATA) are input terminals, Y is an output terminal, Q1P, Q1N, Q2P, Q2N, Q3P, Q3N, Q4P, Q4N
Indicates a MOS transistor, Vcc indicates a power supply terminal, and GND indicates ground.

When the OE signal is high level, Q1P is turned off and Q1N is turned on. Since the OE signal is high level, the ▲ ▼ signal is
It goes low, Q2P turns on and Q2N turns off. When the DATA signal is set to low level in this state, Q3P turns on.
Then, Q3N turns off. In addition, since the ▲ ▼ signal is at high level and Q1N and Q3P are on, the gate potential of Q4P becomes high level and Q4P turns off. Since Q2P is ON, the gate potential of Q4N becomes High level and Q4 is ON.
Then, the output Y becomes Low level.

When the DATA signal is set to high level, Q3P turns off and Q3N turns on.
Becomes Q1N because the signal becomes LOW level.
Is turned on and Q3P is turned off, the gate potential of Q4P is L
It becomes ow level and Q4N turns on. Further, since Q2P and Q3N are ON, the gate potential of Q4N becomes Low, Q4N turns OFF, and the output Y becomes High level. That is, for the DATA signal,
Output Y becomes a normal output, and when the connection of DATA signal and ▲ ▼ signal is exchanged, it becomes an inverted output.

Next, when the OE signal goes low, Q1P turns on and Q1N turns off.
It becomes FF and the gate potential of Q4P is irrespective of ON / OFF of Q3P.
High level, Q4P turns off. Also, because the ▲ ▼ signal goes high, Q2P turns off, Q2N turns on, and the gate potential of Q4N goes low regardless of whether Q3N is on or off, and Q4N turns off. Therefore, the output Y is in a high impedance state.

FIG. 2 shows a three-state circuit of the second embodiment.
The difference from the first embodiment is the connection of Q3P and Q3N. In the first embodiment, the source side of Q3P is connected to Vcc and the source side of Q3N is connected to GND, but in the second embodiment, Q3P and Q3N are connected. The source side of is connected to the DATA input.

Here, OE signal is High level, Q1N and Q2P are ON, Q1P and Q
When 2N is OFF and output Y depends on DATA and ▲ ▼ signals, Q3P is ON and Q3N is OFF when DATA signal is at low level. As a result, the high level which is the DATA signal is supplied to the gate of Q4P through Q1N and Q3P and to the gate of Q4N through Q2P, and the output Y becomes low level. In this case, if there is no Q3P, the high level is supplied only by the gate Q1N of Q4P, but Q1N is an N-type MOS transistor and does not turn on unless the gate potential is higher than the source potential by V _T or more. The gate potential becomes V _CC −V _{T and} Q4P
May not be completely turned off and a leak current may occur. Therefore, Q3P is required to fully swing the gate potential of Q4P to V _CC . The same applies to Q3N, and Q3N is provided to prevent a leak current from occurring in Q4N when the DATA signal is at the low level. Where V _T
Represents the threshold voltage of the MOS transistor.

〔The invention's effect〕

As described above, the 3-state circuit according to the present invention has two fewer MOS transistor elements than the conventional 3-state circuit, so that the chip size is reduced or the same chip size is used for a product having many 3-state terminals. In this case, the effect of increasing the usage rate of the MOS transistor to other functions in the above is obtained.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a 3-state circuit which is a first embodiment of the present invention, and FIG. 2 is a circuit configuration diagram of a 3-state circuit which is a second embodiment of the present invention. Further, FIG. 3 and FIG. 4 are a circuit configuration diagram and a block diagram of a conventional three-state circuit. Input terminal …… OE, ▲ ▼ (OE inverted signal), DATA, ▲
▼ (DATA inverted signal), output terminal: Y, MOS transistor: Q1P, Q1N, Q2P, Q2N, Q3P, Q3N, Q4P, Q4N, power supply terminal: Vcc, ground: GND.

Claims (1)

[Claims] 1. A first power supply terminal, a second power supply terminal, a data input terminal, an inverted data input terminal, an output control signal input terminal, an inverted output control signal input terminal and an output terminal, and a gate common to the data input terminal. A first transistor of a first conductivity type and a second transistor of a second conductivity type connected to each other, and the first conductivity type having a source / drain path connected between the first power supply terminal and the output terminal. Type third transistor, the second conductivity type fourth transistor having a source / drain path connected between the second power supply terminal and the output terminal, the first power supply terminal, and A fifth transistor of the first conductivity type having a source / drain path connected to the gate of the third transistor and a gate connected to the output control signal input terminal, the inverted data input terminal and the third transistor. of A second transistor of the second conductivity type having a source / drain path connected to the gate of the transistor and having a gate connected to the output control signal input terminal; and the inverted data input terminal and the fourth transistor. A source / drain path is connected between the gate and the gate, and the gate is connected to the inverted output control signal input terminal.
A second transistor having a conductive type seventh transistor, a source / drain path connected between the second power supply terminal and the gate of the fourth transistor, and a gate connected to the inverted output control signal input terminal; A three-state circuit having a conductive type eighth transistor, the source-drain path of the first transistor being connected between the first power supply terminal and the gate of the third transistor; The source / drain path of the second transistor is connected to the second
Is connected between the power supply terminal of the first transistor and the gate of the fourth transistor, and the source / drain path of the first transistor is connected between the inverted data input terminal and the gate of the third transistor. A three-state circuit characterized in that the source / drain path of the second transistor is connected between the inverted data input terminal and the gate of the fourth transistor.