JPH0683055B2 - Level shifter circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter circuit formed on an integrated circuit, and more particularly to a complementary insulated gate field effect transistor (hereinafter referred to as CMOS) used as a sense amplifier for RAM or the like. (Referred to below) as an input to the output of the differential amplifier.

[Conventional technology]

Conventionally, this type of level shifter circuit is used as a level shifter circuit that receives the output of a differential amplifier having a CMOS structure. A conventional circuit is shown in FIG. 3 and its operation waveform is shown in FIG. N-channel insulated gate field effect transistor (hereinafter referred to as MOS transistor) M15 in FIG.
Gate signal of P channel MOS transistor M14 and N
Transistor M15 is used as the gate potential of M13, which is determined by passing current between channel MOS transistor M13.
Is a load transistor close to a constant power source. Using the P-channel MOS transistor M16 as a driving transistor,
The input signal D is given to the gate to form a ratio type inverting circuit. At this time, the gm ratio of the transistors M15 and M16 is set so that the output F becomes a sufficiently high level with respect to the low level of the input signal D. The low level of the input signal D has reached the ground potential.

[Problems to be solved by the invention]

The level shifter circuit described above is an N-channel MOS transistor because the inverting circuit composed of the MOS transistors M15 and M16 is a ratio type as shown in the operation waveform of FIG.
Since the current capacity of the P-channel MOS transistor M16 is several times higher than the current capacity of the transistor M15, when the input signal D changes from high level to low level and the output F of the inverting circuit changes from low level to high level, Since the transistor M16 having a large capacity turns on, the change is fast, but conversely, when the input changes from low level to high level and the output F changes from high level to low level, the change is due to the current of the transistor M15 having a small load current. Had the drawback of being several times slower than the former.

[Means for solving problems]

According to the present invention, a first insulated gate field effect transistor of a first conductivity type having a source connected to a first power source is used as a load transistor, and a source of a second layer conductivity type opposite to the first conductivity type is used as a source. A second insulated gate field effect transistor connected to a second power supply as a drive transistor, and a first inverting circuit for inputting an input signal to the gate of the driving transistor; and a configuration similar to the first inverting circuit. In a level shifter circuit including a second inverting circuit that receives an input signal having a phase opposite to that of the input signal, a third inverting circuit that receives the output of the first inverting circuit, and A fourth inverting circuit having an output of the third inverting circuit as an input; and a third insulated gate field effect transistor of the first conductivity type having a gate input of the output of the fourth inverting circuit; Second inversion A series connected circuit in which the first conductivity type fourth insulated gate field effect transistor is connected in series, the output of which is used as a gate input, and one end of the series connected circuit is connected to the output end of the first inverting circuit. The end is connected to the first potential.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This circuit is a level shifter circuit which receives the output of a differential amplifier, and a predetermined gate formed by a driving P-channel MOS transistor M6 having a gate input of an input signal D and N-channel MOS transistor M1 and P-channel MOS transistor M2. It is composed of a ratio-type inverting circuit (hereinafter referred to as an inverting circuit) including a load transistor M5 to which a potential is applied, and an N-channel MOS transistor M3 and a P-channel MOS transistor M4, which are opposite in phase to the input signal D described above. The inverting circuit that receives the input signal output from the other differential amplifier is used. Normal CMOS with N-channel MOS transistor M9 and P-channel MOS transistor M10 with the output of the inverting circuit of transistors M5 and M6 as input
The inverting circuit of the configuration and its output are input, and M11 and M1
Using the normal CMOS configuration inverting circuit by 2, the latter is connected in series with an N-channel MOS transistor M8 whose gate input is the output and an N-channel MOS transistor M7 whose gate input is the output of the inverting circuit of the transistors M3 and M4. The source of the transistor M7 is set to the ground potential, and the drain of the transistor M8 is connected to the node B.

The operation of this circuit will be described with reference to FIG. Input signal D
Is low level and is high level, node B is high level, node C is low level, node A is low level,
The node E is at a high level. Therefore, in the series connection portion of M7 and M8, the gate input of M7 is turned off at the low level, so that the conduction path from the node B to the ground potential (hereinafter referred to as GND) is only the load transistor M5.

Next, when the input signal D changes from the low level to the high level and the signal changes from the high level to the low level, the change of the node B to the low level initially changes only by M5. Therefore, the node A changes from the low level to the low level. Since it changes quickly to high level, the N-channel MOS transistor M7 that inputs it to the gate is turned on. At that time, since node E is still at high level, M8 is also turned on. Since a conduction path to the circuit is created and it is possible to help bring the position of the node B to the low level, the operation waveform of the conventional circuit becomes faster than the waveform of F in FIG.

Further, when the potential of the node B, which is the input of the inverting circuit by M9 and M10, is detected as low level, the output changes, and accordingly, the output E of the inverting circuit of M11 and M12 also becomes low level, so M7 is turned off. , The GND conduction path disappears, and M5
Since only the load transistor of is a conduction path to the ground potential, the input logic threshold of the inverting circuit of M5 and M6 does not become too low due to M7 and M8.

Next, when the input signal D changes from the high level to the low level and the signal changes from the low level to the high level, the node E is at the low level, the N-channel MOS transistor M8 having this as a gate input is off, and the load transistor Node B is the ratio between M5 and the driving transistor M6.
Since the potential of the node B is determined, the change from the low level to the high level of the node B is as fast as the conventional one.

As described above, according to the present invention, when the input signal changes from the low level to the high level, the conduction path to the GND is temporarily provided, and the output changes from the high level to the low level. There is an effect that it can be done faster.

[Brief description of drawings]

1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the level shifter circuit of FIG. 1, FIG. 3 is a circuit diagram of a conventional level shifter circuit, and FIG. FIG. 4 is a waveform diagram showing the operation of the level shifter circuit of FIG. M1, M3, M5, M7, M8, M9, M11 …… N channel MOS transistor, M2, M4, M6, M10, M12 …… P channel MOS transistor, D …… Input signal.

Claims (1)

[Claims] 1. A first conductivity type first insulated gate field effect transistor having a source connected to a first power source as a load transistor, and a source of a second conductivity type which is a conductivity type opposite to the first conductivity type. A second insulated gate field effect transistor connected to a second power supply as a drive transistor, and a first inverting circuit for inputting an input signal to the gate of the driving transistor; and a configuration similar to the first inverting circuit. And a second inverting circuit for receiving an input signal having a phase opposite to that of the input signal, the level shifter circuit comprising:
A third inverting circuit having the output of the inverting circuit as an input, and a fourth inverting circuit having the output of the third inverting circuit as an input, and the gate of the output of the fourth inverting circuit is provided. A series connection in which the first conductivity type third insulated gate field effect transistor and the first conductivity type fourth insulated gate field effect transistor whose gate input is the output of the second inverting circuit are connected in series. One end of the circuit is connected to the output end of the first inverting circuit, and the other end of the series connection circuit is connected to the first
Level shifter circuit characterized by being connected to the electric potential of.