JPH0683062B2 - Semiconductor circuit - Google Patents

Description

The present invention relates to a semiconductor circuit composed of a MOS transistor (also called an insulated gate field effect transistor) and suitable as an output stage buffer of an integrated circuit.

The output section from the CPU (Central Processing Unit), memory, and other integrated circuits (hereinafter referred to as IC) of the computer is usually TTL (Tra
nsistor Transistor Logic) is required to have a large drive capacity, and in addition to the output states “1” and “0”, a high impedance state function (3-state function) may be required. In many cases, the stage buffer has an E / E (enhancement / enhancement) push-pull configuration (on / off states of the drive-side element and the load-side element are inversely related). A conventional example of an output stage buffer of an IC using a single power supply is shown in FIG.

In FIG. 1, MOS type transistors 1 to 6 are, for example, N-channel type, transistors 1 and 3 are depletion type (called D type), and transistors 2 and 4 to 6 are enhancement type (called E type). The configuration of this circuit includes a data signal d and an inverter 10 'that receives the signal and outputs a reverse phase signal. The signals d and d are push-pull transistors that output a signal D in phase with the signal d and a reverse phase signal. The signals D and are input to the buffers 20 'and 30, and are input to the gates of the load side transistor 5 and the drive side transistor 6 of the output stage buffer 40, respectively. In the figure, Vc is the power supply and the arrow is the ground side.

In the above circuit, for example, the output of the output stage buffer 40
When outputting “1” to Dout, if Vc = 5V and the signal d becomes “1”, and the signal becomes “0”, the signal D becomes 5V, and becomes substantially the ground potential, and “Vc−Vth” ( Vth is transistor 5
Output voltage, which is the threshold voltage of. In this state, the transistor 5 has a large threshold voltage due to the back gate bias effect. For example, the substrate concentration N _A = 8 × 10 ¹⁴ pieces / cm ³ (P-type substrate), the gate oxide film thickness to
At x = 1000Å, Vth is 0 at back gate bias voltage OV.
At 9V, Vt at back gate bias voltage minus 3.5V
It becomes h1.5V, and only about 3.5V can be obtained at the output Dout. That is, the transistor 5 operates as a pentode, and as shown by the load characteristics in FIG. 2, the current I cannot be quickly taken depending on the output voltage Vout.

By the way (normal memory (for example, general-purpose memory)) One TTL (fan-out 1) and a capacity of 100PF are connected as an output load, and the voltage V _OH that judges the output as “1” is 2.4V. In order to increase the output speed, a fairly large output stage buffer is required, but if the output stage buffer is unnecessarily increased to increase the output speed, for example, an output short current at "1" output will flow excessively and destroy the device. There is a risk. This is because, for example, if the output terminal Dout is erroneously grounded, a large current flows from the power supply Vc to the ground via the transistor 5. If the output stage buffer is unnecessarily large, the chip area becomes large, which is not efficient. This is a serious problem especially in an IC having a plurality of outputs.

Here, FIG. 3 shows a voltage waveform at the time of "1" output of the circuit in FIG. 1 of the output stage buffer in which the normally used output short circuit current is suppressed to about 10 mA. As can be seen from this figure, the time “t ₂ −t ₁ ” from when the output terminal Dout starts to change to when it reaches 2.4 V is about 40 ns, which impedes high-speed operation. It is also conceivable to raise the voltage at point D to increase the output Dout at a high speed, but if the output Dout is kept high, the voltage reduction from the "1" level to the "0" level is delayed,
After all, the problem of obstructing high-speed operation and the amount of current flowing from the output Dout through the transistor 6 become large, which causes a problem of voltage fluctuation of the ground power supply.

The present invention has been made in view of the above circumstances, and comprises level holding means for forcibly setting the output voltage of the MOS drive circuit to a value lower than the power supply voltage after boosting the gate voltage of the transistor of the MOS drive circuit. By doing so, it is intended to provide a semiconductor circuit which can solve the conventional problems.

An embodiment of the present invention will be described below with reference to the drawings. Fourth
The drawing is a circuit diagram showing the same embodiment, and is an example of a case corresponding to that of FIG. 1. Therefore, corresponding parts will be denoted by the same reference numerals and description thereof will be omitted. It can be considered that the newly provided MOS transistors 7 to 16 are all N-channel type, of which transistors 7, 9, 11, 12, 14, 14 and 16 are D-type, and the others are all E-type.
Use as a mold. In this circuit configuration, the data signal d is supplied to the input of the delay circuit 50 including two stages of inverters, the output A is connected to one end of the capacitor C1, and the other end of the C1 is connected to the output D of the buffer 20 '. It A level compensating transistor (level holding means) 11 is connected between the output D and the power supply Vc, and the gate of the transistor 11 is connected to the power supply Vc side. Similarly, a data signal is supplied to the input of the delay circuit 60 including a two-stage inverter, the output B is connected to one end of the capacitor C2,
The other end of the C2 is connected to the output of the buffer 30. A level compensation transistor (level holding means) 16 is connected between the output and the power supply Vc, and the gate of the transistor 16 is connected to the power supply Vc side.

Next, the circuit operation of FIG. 4 will be described. First output stage buffer
When outputting "1" to the output Dout of 40, input d is "0"
From “1” to “1” and from “1” to “0”, output D
Begins to be charged by transistor 1. Then, after an appropriate delay time determined by the delay circuit 50, the output terminal A rises from "0" to "1", and the voltage of the output terminal D is raised by the coupling with the capacitor C1. In this state, all parasitic capacitances other than the capacitance C1 of the output terminal D are Co, the potential of the output terminal D immediately before the output terminal A changes from "0" to "1" is Vo, and the output terminal A is
Let V _{A be} the amount of change in potential of V and the potential of output D after output A is "1" is V _P, and switch W is switched from a to b in the equivalent circuit of FIG. corresponds to, from the time (C1 + Co) Vo + C 1 V a = (C1 + Co) V P Becomes If Vo = 3V, C1 = 5Co, V _A = V _C = 5V, then V _P = 7V, the transistor 5 operates in three poles, and V _C (= 5V) is output to the output Dout. . Note that the transistor 1 cuts off when the output D exceeds "V _G -Vth" 3.5V, so the power is supplied from the output D through the transistor.
There is no reverse current flow to V _C. That is, the transistor 1 functions as a unidirectional conducting element. The level compensating transistor 11 can prevent the potential of D, which has risen above the power supply V _C , from decreasing to the voltage “V _G −Vth” at which the transistor 1 turns on after a long time due to junction leakage. The potential of D is kept below V _C (= 5V). However, through transistor 11, output D
Since the current flows back to the power supply V _C more, the discharge time constant at the output terminal D needs to be at least such that the power supply voltage V _C can be obtained at the output Dout.

FIG. 6 shows operation waveforms when the output stage buffer has the same size as in FIG. That is, the output Dout is temporarily 5V
It is up. Thus the output "1" of the determination voltage V _OH = 2.4V to rise time "t '2 _{-t' 1} 'is improved to about 20 ns. Further, if the same output speed as that of the conventional one is set, the size of the output stage buffer can be reduced. Further, the potential of the output terminal D is discharged to the power supply V _C through the transistor 11 after a certain period of time, and finally drops to 5 V, so that the pentode operation of the transistor 5 lowers the driving capability of the transistor, thus reducing the output short-circuit current. it can. However, the output short-circuit current becomes large during the operation of the triode of the transistor 5, but since the period is extremely short,
Even if an output short-circuit current flows, the element is not destroyed.

In addition to the bootstrap capacitor (eg, C1 in FIG. 4), a unidirectional conducting element (eg, 1 in FIG. 4) for charging from an independent path is provided, and level holding means (eg, 11 in FIG. 4) is provided. ) Is provided on a different route,
When the bootstrap capacitance is charged through the path of the unidirectional conducting element and the terminal of this capacitance rises to a high voltage level due to the bootstrap action, the unidirectional conducting element itself is turned off to start the boot. It is possible to prevent backflow from the terminals of the strap capacitor. Further, as described above, by making the unidirectional energization path and the path of the level holding means independent, it is possible to consider the balance relationship between the impedance of the unidirectional energization path and the impedance of the level holding means path. It is possible to have a simple configuration in which these impedance values can be decided independently. . Further, since both paths can be set independently, the potential of the bootstrap circuit (specifically, charge setting for boosting, time setting for potential clamping of operating waveform, etc.) can be arbitrarily set. The operation speed can be increased.

In the circuit of FIG. 4, the operation when "0" is output to the output terminal Dout can be considered in the same manner as when outputting "1". That is, as the voltage at the output end increases, the transistor 6 operates as a triode as in the above case, and the same advantages are obtained.

FIG. 7 shows another embodiment of the present invention. Delay circuit here
70 is a one-stage inverter of transistors 17 and 18,
A bootstrap circuit 80 including transistors 19 and 20 and a capacitor C3 is provided, and a resistor 21 is used as a level compensation element. This circuit outputs E when the signal d changes from "0" to "1".
The point changes from "1" to "0" after an appropriate delay time. Then the circuit
The F point of 80 changes from "0" to "1", and at this "1" voltage, the capacitance C3
The "1" voltage on the opposite side (gate side of transistor 19) is raised. That is, the output terminal D is pulled up to the power source voltage V _C or more, and thus the transistor 5 operates as a triode.

Generally, the output speed is faster on the discharging side than on the charging side, so
As shown in FIG. 7, countermeasures may be taken only on the charging side, that is, the transistor 5 side.

With the above-mentioned configuration, the level holding means 11 and 21 quickly lower the point D to the level of the power supply voltage V _C , that is, quickly increase the on-resistance of the transistor 5 so as to penetrate the power supply V _C and the ground. The current can be made small, and the output Dout can be quickly lowered to 3.5 V (see FIG. 6) to prepare for the next power down to "0" level, so that the power down to "0" becomes faster. In addition, the amount of current (charge) required to drop from 3.5V to OV is smaller than that from 5V to OV, so fluctuations in the voltage of the ground power supply can be reduced. By the way, when the capacitance C at the output Dout is 100PF, when the voltage is reduced from V = 5 [V], the charge becomes Q = CV = 100 × 5 = 500 × [PC], but from V = 3.5 [V] When power is cut off, the current is greatly reduced as Q = CV = 100 x 3.5 = 350 [PC].

It should be noted that the present invention is not limited to the above-described embodiment, and for example, in the embodiment, the output stage buffer 40 has the E / E configuration, but it may have the E / D configuration. Also, the transistors 1 and 3 may be I-type transistors that are VthOV instead of E-type. However, in this case, in order to prevent a backflow from the output terminal D to the power supply V _C , it is necessary that the threshold voltage Vth is cut off by the back gate bias effect. The gate capacitance of the transistor may be used as the capacitance C3 and the like in FIG.
You may install capacity separately.

As described above, according to the present invention, after the gate voltage of the transistor of the MOS drive circuit is boosted, the level holding means for forcibly setting the output voltage of the MOS drive circuit to a value lower than the power supply voltage is provided. It is possible to provide a semiconductor circuit that enables high-speed operation, has a small output short-circuit current, has a small fluctuation in power supply due to a continuous current flow, and has an advantageous chip area.

[Brief description of drawings]

FIG. 1 is a conventional output stage buffer circuit diagram, FIG. 2 is a load characteristic diagram of an E-type transistor, FIG. 3 is an operation waveform diagram of the conventional circuit, and FIG. 4 is a circuit diagram of an embodiment of the present invention. FIG. 5 is a capacitor equivalent circuit diagram of the same circuit, FIG. 6 is an operation waveform diagram of FIG. 4, and FIG. 7 is a circuit diagram of another embodiment of the present invention. 1 to 20 ...... MOS transistors, 20 ', 30 ...... push-pull buffer, 40 ...... output stage buffer, 50, 60, 70 ...... delay circuit, 11,16,21 ...... level holding unit, C ₁ ~ C ₃ …… Capacity.

Claims (1)

[Claims] 1. A MOS type drive circuit formed on a semiconductor chip for outputting a signal to the outside of the chip, and an output voltage deriving transistor of the drive circuit between an output end of the drive circuit and a power supply voltage supply end. Voltage boosting means for boosting the gate of the output voltage deriving transistor of the drive circuit to a voltage equal to or higher than the power supply voltage by a capacitor provided in the gate of the drive circuit and performing a bootstrap action when deriving the output voltage of the drive circuit,
An element provided between the boosted voltage output section of the boosting means and the power supply voltage supply terminal and acting as a resistance is provided, and after the voltage of the gate is boosted by the boosting means, the gate voltage of the transistor is changed to the resistance effect. Level holding means for forcibly setting the voltage at the output end of the drive circuit to a value lower than the power supply voltage by the threshold voltage of the transistor, by discharging the voltage to the power supply voltage through the element. A unidirectional conducting element that supplies the voltage that is the source of the boosted voltage to one terminal portion, and after supplying the voltage that is the source of the boosting voltage to one terminal portion of the capacitor by the conducting element. A delay circuit that supplies a delayed signal to the other terminal of the capacitor to generate the boosted voltage in the boosting means,
The semiconductor circuit, wherein the MOS drive circuit constitutes an output stage buffer of an integrated circuit.