JPH0683063B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a CMOS logic circuit including a CMOS (complementary insulated gate type) selection circuit as a basic constituent element. The present invention relates to a semiconductor integrated circuit.

(Prior Art) Generally, CMOS logic circuits are being used in place of N-channel MOS circuits in the field of logic LSI because of their features such as low power consumption. In this case, if the CMOS logic circuit is configured by the conventional design method, there is a drawback that it requires about twice as many elements as the N-channel MOS circuit. Therefore, in order to reduce the number of elements, it is necessary to devise a circuit technology (precharge circuit). System, domino circuit system, dynamic circuit system, etc.).
However, in the precharge circuit system, half of the clock cycle is used for the precharge operation when it is adopted in the synchronous circuit, so that there is a problem that the time for the operation operation is halved. Further, since the output result of the circuit adopting the precharge circuit system is in a high impedance state, it is vulnerable to a noise signal, and there is a problem that the circuit malfunctions due to the problem of charge sharing. Further, although a circuit adopting the dynamic circuit system, for example, a dynamic shift register is useful for holding memory, the output result is in a high impedance state, so that the output signal line can be wired long (far away). It is difficult and there is a problem that the number of clock signal lines to be used increases.

(Problems to be Solved by the Invention) The present invention basically solves the problems associated with adopting a precharge circuit system or a dynamic circuit system in order to reduce the number of elements of a CMOS logic circuit as described above. It was made to solve the problem, and is a basic CMOS consisting of an extremely small number of elements.
To provide a semiconductor integrated circuit in which various kinds of desired logic circuits can be realized by using circuits and wiring between the logic circuits can be easily performed, and the number of elements and a wiring area can be reduced as a whole. To aim.

[Structure of Invention]

(Means for Solving Problems) As a result of considering the logic characteristics of various logic circuits, the constituent elements of the logic circuit are alternatives, that is, A * S + B * (where,
It has been found that most of the parts are expressed by the logical expression of the symbol * is a logical product and + is a logical sum. Therefore, the semiconductor integrated circuit of the present invention is formed by using, as a basic constituent element, a selection circuit represented by the above logical formula, that is, a CMOS logic circuit having a static circuit configuration for selecting one of two inputs according to a logic level of a selection signal input. It is configured to include a CMOS logic circuit.

Then, in each of the CMOS selection circuits, three input nodes and one output node are formed in the central portion of each side of the square area, and the CMOS selection circuits are arranged in an array in a spaced manner. The pattern of the area where these CMOS selection circuits are formed
By selecting the layout of each input node and output node that shortens the wiring length by rotating by 90 degrees or by arranging so as to form a mirror image, and selectively between the nodes of each CMOS selection circuit on the wiring area. It is characterized in that a gate array is formed by wiring.

(Operation) Since three input nodes and one output node are arranged in the center of each side of the square area to form a CMOS circuit of static circuit configuration, the area where these CMOS selection circuits are formed By arranging the pattern in 90 ° units or arranging so as to form a mirror image thereof, it is possible to select the arrangement of each input node and output node that shortens the wiring length. Since the CMOS logic circuit has a static circuit configuration, there is no room for problems associated with adopting a precharge circuit system or a dynamic circuit system, and it is possible to reduce the number of elements and the input / output wiring area. .

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

The gate array LSI shown in FIG. 1 is a basic component C
1 schematically shows a state in which the MOS selection circuit SL is arranged on, for example, a 10 mm square LSI chip 10, and 11 is the selection circuit SL.
The area between them is a wiring area. Above CMOS selection circuit SL
Is constructed as shown in FIG. 2, FIG. 3, or FIG. That is, the CMOS selection circuit of FIG. 2 has a P-channel MOS transistor T _P and an N-channel MOS transistor.
One end of each T _N corresponds to the first and second input nodes 21 and 22, each gate of the transistors T _P and T _N serves as a selection signal input node 23, and the other ends of the transistors T _P and T _N The interconnection node is the output node 24. The P-channel transistor T _P becomes conductive / non-conductive in response to low level / high level of the gate input, and the N-channel transistor T _N becomes conductive / non-conductive in response to high level / low level of the gate input. Become. Therefore, in the selection circuit, when the inputs B and A are input to the first and second input nodes 21 and 22, respectively, and the selection signal S is input to the selection signal input node 23, three inputs A and B are input. , S has one output Q (= S * A
It has a function represented by a logical expression that produces + * B), and its configuration is composed of one P-channel transistor and one N-channel transistor, respectively, and has a very small number of elements, which is a simple configuration. The above-mentioned selection circuit can realize various CMOS logic circuits singly or in combination with each other (which will be described later). For example, as shown in FIG. As shown in (a) to (c), input nodes of three inputs A, B, S and one output Q
It is desirable to place the output node of. That is, the selection circuit region SL ′ is configured to have a size of 20 μ to 40 μ square, for example,
It is desirable to dispose the four nodes (three input nodes 21, 22, 23 and one output node 24) separately at the center of each side of the quadrangular area. The arrangement relationship of the above four nodes is based on the three arrangement relationships shown in FIGS. 5A to 5C, and each selection circuit area SL ′ is rotated by 90 degrees or a mirror image thereof is formed. By arranging in such a manner as described above, it is possible to have 8 configurations, that is, 24 configurations for each of the above-mentioned three layout relationships, and it is only necessary to determine the layout relationship so as to shorten the wiring length.

The selection circuit of FIG. 3 has a CMOS AND gate 31 having one input terminal connected to the first input node 21 and one input terminal connected to the second input node 22 for inputting a selection signal. CMOS AND gate with the other input connected to node 23
32, a CMOS inverter 33 inserted and connected between the input node 23 of the selection signal S and the other input terminal of the CMOS AND gate 31, and the outputs of the two AND gates 31 and 32 are input. And a two-input OR gate 34 that produces an output Q (= S * A ++ B). Further, in the selection circuit shown in FIG. 4, the first N-channel transistors T _N1 and T _N2 are connected in series between the first input node 21 and the second input node 22, and the V _CC power supply terminal And a ground terminal, a P-channel transistor T _P and a third N-channel transistor T _N3 are connected in series, and the gates of the transistors T _P and T _N3 are connected to the selection signal input node 23. The series connection point of the transistors T _P and T _N3 is the transistor T _N1 , T _N2.
Connected to each gate of the above transistors T _N1 and T _N2
Is connected to the output node 24.
The transistors T _P and T _N3 form an inverter, and the output Q = S * A ++ B is obtained at the output node 24.

In the selection circuit shown in FIG. 2, when the input A of the second input node 22 and the selection signal S input are both high level, the high level of the output Q is weak, that is, V which is a completely high level. _{The CC} power supply potential does not become 5 V but becomes 5 V-V _TN (threshold voltage of N-channel transistor T _N ). Further, when both the input B of the first input node 21 and the selection signal S input are low level, the low level of the output Q is weak, that is, the ground potential O _V which is a complete low level does not occur and O _V + V _TP (P The threshold voltage of the channel transistor T _P ). in this way,
If the high level or low level of the output Q is weak, the operation margin of the circuit is reduced, but it is possible to sense the input as high level or low level in the subsequent stage, and it is possible to adjust the ion implantation amount in the LSI manufacturing process. Thus, by suppressing the back gate bias effect to a minimum, the level of the output Q can be set within a practical operating range. Of course, if necessary, an inverter may be inserted in the subsequent stage of the selection circuit to reinforce the level of the output Q.

On the other hand, in the selection circuit of FIG. 4, when the input A of the second input node 22 and the selection signal S input are both high level, the high level of the output Q is weak, but the first input node
When the input B of 21 and the selection signal S input are low level,
Since the N-channel transistor T _N1 is gate-controlled by the selection signal close to the V _CC power supply potential, the low level of the output Q becomes sufficiently low (strong).

Next, application examples in which various CMOS logic circuits are configured based on the selection circuit of FIG. 2 will be described with reference to FIGS. 6 to 9. The corresponding CMOS logic circuits of conventional examples will be compared with each other. Are shown in FIGS. 10 to 13.
That is, in the inverter shown in FIG. 6, the first input node 21 in the basic selection circuit is connected to the V _CC power supply line, the second input node 22 is connected to the ground line, and the selection signal input node 23 is connected. Output Q = O * A +
1 * = is obtained. A conventional inverter corresponding to this inverter has a P-type circuit connected as shown in FIG.
Channel transistor 100, N-channel transistor 101
Consists of. The AND circuit shown in FIG. 7 applies the input A to the second input node 22 in the basic selection circuit, connects the first input node 21 to the ground line, and selects the input node 23 for the selection signal.
Output Q = A * B + O *
= A * B is obtained. A conventional AND circuit corresponding to this AND circuit has a large number of elements (three P-channel transistors 111, 112, 113) connected in a circuit as shown in FIG.
And three N-channel transistors 114, 115, 116) are required. The OR circuit shown in FIG. 8 applies the input A to the first input node 21 in the basic selection circuit, connects the second input node 22 to the V _CC power supply line, and selects the input node 2 for the selection signal.
Output Q = A * + 1 * by giving input B to 3
B = A * + (A +) * B = A * + A * B + * B
= A * (+ B) ++ B = A + B is obtained. The conventional OR circuit corresponding to this OR circuit requires a large number of elements (three P-channel transistors 121, 122, 123 and three N-channel transistors 124, 125, 126) connected in a circuit as shown in FIG. The exclusive OR circuit shown in FIG. 9 is a combination of two basic selection circuits. The basic circuit at the preceding stage is an inverter that obtains an output by using the input A as a selection signal as shown in FIG. In the basic circuit of the subsequent stage, the input A is given to the first input node 21, the output of the inverter of the previous stage is given to the second input node 22, and the input B is given to the input node 23 for the selection signal. Given, output Q = A *** B = AB
(The symbol is an exclusive OR). A conventional exclusive OR circuit corresponding to this exclusive OR circuit has a large number of elements (6 P-channel transistors 131 to 136 and 6 N-channel transistors 137 to 142) connected in a circuit as shown in FIG. ) Is required.

Since the exclusive OR circuit of FIG. 9 has a weak output Q level, an inverter may be added in the subsequent stage if necessary.

As described above, when various CMOS logic circuits are formed by using the CMOS selection circuit shown in FIG. 2 as a basic constituent element, the AND circuit, the OR circuit, and the exclusive OR circuit are about the same as those of the circuit structure by the conventional design method. It can be realized with 1/3 the number of elements. Therefore, the CM can be used as a part of all the circuits in the semiconductor integrated circuit (a part occupying about 5% or more of the total number of elements).
Include the OS selection circuit in a regular or irregular arrangement,
Using this CMOS selection circuit as a basic component, two or more types of CM
By configuring the OS logic circuit, it is possible to reduce the number of elements, shorten the input / output wiring length of the CMOS logic circuit, and eventually reduce the wiring area. In this case, the gate array LSI
When the present invention is applied to, the effect of reducing the cost due to the reduction of the number of elements and the reduction of the wiring region can be remarkably obtained. ) Can be reduced to about 50%. An inverter, an AND circuit, an OR circuit, and an exclusive OR circuit can be formed by applying inputs to the CMOS selection circuit shown in FIG. 4 as shown in FIGS. 6 to 9. .

[Effects of the Invention] As described above, according to the semiconductor integrated circuit of the present invention, a desired CMOS logic circuit having a static CMOS selection circuit as a basic constituent element is formed as at least a part of the circuit. . Therefore, there is no room for the problems associated with the adoption of the precharge circuit system or the dynamic circuit system for this CMOS logic circuit, and the effects such as the reduction in the number of elements and the input / output wiring area can be obtained. This effect can be obtained to some extent even in an LSI in which the CMOS logic circuit occupies a small proportion of all circuits, but is particularly remarkable in a gate array LSI.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing an array of a CMOS selection circuit which is a basic constituent element in a gate array LSI according to an embodiment of the present invention, and FIGS. 2 to 4 are CMOS in FIG. 1, respectively.
FIG. 5 (a) is a circuit diagram showing a different circuit example of the selection circuit.
1 to (c) are diagrams showing different arrangement examples of three input nodes and one output node in the CMOS selection circuit in FIG. 1, and FIGS. 6 to 9 respectively correspond to the CMOS in FIG. Inverter with selection circuit as a basic component,
A circuit diagram showing an AND circuit, an OR circuit, and an exclusive OR circuit,
10 to 13 are conventional CMOS logic circuit diagrams corresponding to the circuits of FIGS. 6 to 9, respectively. SL ... CMOS selection circuit, SL '... CMOS selection circuit area, T _P ...
... P-channel MOS transistor, T _N , T _{N1 to} T _N3 ... N-channel MOS transistor, 21 ... first input node, 22 ...
… Second input node, 23 …… Third input node, 24 ……
Output node.

Claims (8)

[Claims] 1. An input node and three input nodes each formed at the center of each side of a square area,
One of the two inputs is selected according to the logic level of the selection signal input, and it is formed between the CMOS selection circuits of static circuit configuration in which they are spaced apart and arranged in an array, and the CMOS selection circuits described above. A wiring area for selectively wiring between circuits is provided, and by arranging the pattern of the area in which each of the CMOS selection circuits is formed to rotate 90 degrees or to form a mirror image, the wiring length can be shortened. A semiconductor integrated circuit, characterized in that a gate array is formed by selecting the arrangement of the respective input nodes and output nodes and selectively wiring between the respective nodes on the wiring region. 2. The claim according to claim 1, wherein the number of elements of said CMOS selection circuit is about 5% or more of the total number of elements.
The semiconductor integrated circuit according to the item. 3. In the CMOS selection circuit, one P-channel MOS transistor and one N-channel MOS transistor are connected in series between a first input node and a second input node. 2. The semiconductor integrated circuit according to claim 1, wherein each gate of the transistor is connected to a selection signal input node, and a series connection point of the both transistors is connected to an output node. 4. The CMOS selection circuit, wherein a first N-channel MOS transistor and a second N-channel MOS transistor are connected in series between a first input node and a second input node, and a power supply terminal is provided. One P-channel MO between the ground and ground
An S transistor and a third N channel MOS transistor are connected in series, and the gates of the one P channel transistor, the third N channel transistor and the second N channel transistor are connected to a selection signal input node. And a series connection point of the one P-channel transistor and the third N-channel transistor is connected to the gate of the first N-channel transistor, and the first N-channel transistor and the second N-channel transistor are connected. The semiconductor integrated circuit according to claim 1, wherein the serial connection point of is connected to the output node. 5. A first input node of the CMOS selection circuit is connected to a power supply terminal, a second input node is connected to a ground terminal, and an input signal is input to a selection signal input node,
5. The semiconductor integrated circuit according to claim 3, wherein an inverter that outputs an inverted signal of the input signal is formed at an output node. 6. A first input node of the CMOS selection circuit is connected to a ground terminal, a first input signal is input to a second input node, and a second input signal is input to a selection signal input node. This allows the first input signal and the second
5. The semiconductor integrated circuit according to claim 3 or 4, wherein an AND circuit that outputs a logical product signal of the input signal and the input signal is formed. 7. A first input signal is input to a first input node of the CMOS selection circuit, a second input node is connected to a power supply terminal, and a second input signal is input to a selection signal input node. This allows the first input signal and the second
5. The semiconductor integrated circuit according to claim 3, wherein an OR circuit that outputs a logical sum signal of the input signal and the input signal is formed. 8. A CMOS in the preceding stage, comprising two said CMOS selection circuits.
For the selection circuit, the first input node is connected to the power supply terminal, the second input node is connected to the ground terminal, the first input signal is input to the selection signal input node, and the subsequent CMOS selection circuit is connected. On the other hand, the first input signal is input to the first input node, the inverted signal of the first input signal output from the CMOS selection circuit in the previous stage is input to the second input node, and the selection signal is input. An exclusive OR circuit that outputs an exclusive OR signal of the first input signal and the second input signal to the output node by inputting the second input signal to the node is formed. The semiconductor integrated circuit according to claim 3 or 4, wherein: