JPH0683069B2 - Series-parallel type A / D converter - Google Patents

Description

The present invention relates to an analog / digital converter (A / D converter) for converting an analog voltage into a digital value, and more particularly to a series-parallel type A
The present invention relates to an A / D converter called a / D converter.

[Conventional technology]

Parallel type of upper 3 bits and lower 3 bits for simplification
Consider a serial-parallel A / D conversion method that uses an A / D converter and overlaps the upper and lower bits by 1 bit to obtain a 5-bit conversion result.

With the serial-parallel A / D conversion method, in the case of a two-stage configuration, the parallel A / D converter at the first stage roughly performs A / D conversion to obtain the upper bits, and then performs A / D conversion at the first stage from the input signal. Then, the minutes are subtracted and the rest is A / D converted again by the parallel A / D converter to obtain the lower bits, and the upper bits and the lower bits are combined to obtain a conversion result with a predetermined resolution. One bit overlap when adding the upper bit and the lower bit means that the conversion of the second stage is performed within the range of 2 LSB of the upper bit, and the conversion error of the first stage is corrected at the time of the conversion of the second stage. be able to. Therefore, since the accuracy of the A / D converter in the first stage is 1/2 LSB of the resolution in the first stage, the accuracy required for the elements forming the A / D converter is also moderate. Specifically, since the upper bits and the lower bits do not overlap, 5
In order to obtain the conversion result of 5 bits, ± 1/2 LSB precision of 5 bits is required, but in order to obtain the conversion result of 5 bits by overlapping 1 bit from upper 3 bits and lower 3 bits. Since the accuracy of 3 bits ± 1/2 LSB is sufficient, the required accuracy is four times different. This difference becomes more remarkable as the resolution increases and the requirement for element accuracy becomes more stringent.

Here, a method of obtaining the lower bits and a method of adding the upper bits and the lower bits will be considered. When subtracting the amount of A / D conversion at the first stage from the input signal to obtain the lower bits, if the A / D conversion result at the first stage is subtracted as it is, positive and negative values of both signs are generated as the input of the second stage. For example, a 3-bit A / D converter converts an analog input voltage Vin from 0 to Vr and outputs a digital code from "000" to "111". At this time, the relationship between the input voltage and the output code is as shown in FIG. When the output code is represented by a normal decimal number, when 0 ≦ Vin <Vr ₀ , D = 0 (1) When Vr (i−1) ≦ Vin <Vr (i) D = i where i
Is an integer of 1 to 7 (2) When Vr7 ≦ Vin <Vr, D = 7 (3).

Assuming that the A / D conversion result is N and the analog voltage corresponding to the conversion result is Vad (N), Vad (N) is Vad (N) = N · Vr / 8 (as shown in FIG. 2). 4) As shown in FIG. 2, when the input voltage Vin is Vr3 = Vin <Vr4 (5) Vr3 = 7Vr / 16 and Vr4 = 9Vr / 16 (6), the output is D = 4. The analog voltage corresponding to this conversion result is Vad4 = 8Vr / 16 (7). Therefore, if you subtract the result of A / D conversion at the first stage from the input signal as is to obtain the lower bits,
Depending on the magnitude of the input signal, both positive and negative signs are generated as the second stage input as follows. That is, when the subtracted result is Vdif, 7Vr / 16 ≦ Vin <8Vr / 16 −Vr / 16 ≦ Vdif <0 (8) 8Vr / 16 ≦ Vin <9Vr / 16 0 ≦ Vdif <Vr / 16 ( 9) As a result, when the upper bit and the lower bit are overlapped by one bit and added, subtraction is actually required, and the hardware function becomes complicated. A / of a single power supply
It is inconvenient if the input voltage of the D converter is either positive or negative. Therefore, when subtracting the A / D conversion result of the means from the input signal, subtracting 1LSB less from the input signal from the A / D conversion result of the first stage makes the input of the second stage A / D conversion positive or negative. There is only one code. In the above 3-bit A / D converter, when subtracting the 1-stage less ALSB value from the input signal when subtracting the A / D conversion result of the first stage from the input signal, the subtracted voltage is D
= 4-1 = 3. That is, Vad3 = 6Vr / 16 (10) is subtracted. Therefore, the result of subtraction Vd
If 'becomes Vr / 16 ≤ Vdif'<3Vr / 16 (11), which is only a positive sign. Also, the original A / D is used as the upper bit when the upper bit and the lower bit are added.
If the value 1 LSB less than the conversion result is used as the output code of the A / D converter in the first stage and the corresponding D / A converted value is subtracted from the input signal to obtain the second stage input, the second stage input is It becomes a sign, and there is no need to consider subtraction when adding the upper bit and the lower bit.

However, if the A / D conversion result of each stage is originally "0" and a value smaller by 1 LSB is used as the output code of the A / D converter, the output code will be negative and inconvenience will occur. "Is output as is. Therefore, when the input of the parallel type A / D converter is originally "0" or "1", the output code is 0.

In this way, in the serial-parallel A / D conversion method, the high-order bit and the low-order bit are overlapped and added to obtain a predetermined A / D
In the method that obtains the conversion result, the parallel A / D converter at the first stage outputs an A / D value that is 1 LSB less than the normal A / D conversion result.
A converter that outputs a D / A converter correspondingly is an excellent IC for a single power supply. This method is Japanese Patent Application Sho 59
-079504 is proposed.

When using a multi-stage configuration, use the A / D converter that outputs the conventional A / D conversion result as is, only for the final parallel A / D conversion.
Otherwise, the above A / D converter may be used.

[Problems to be solved by the invention]

In the above serial-parallel A / D conversion method, it is considered that the parallel A / D conversion at each stage is cyclically executed by the same parallel A / D converter. If so, the conversion speed becomes slower, but the chip area and power consumption become much smaller, and there are many advantages when considering integration with other digital signal processing circuits.

However, when using a parallel A / D converter that outputs a value 1 LSB smaller than the original conversion result as a parallel A / D converter, the A / D conversion result at the final stage is also Output a value 1 LSB smaller. Therefore, it is necessary to add "1" to the obtained code to make it a correct code. In order to execute this, it is sufficient to add "1" to the least significant bit when adding the upper bit and the output code of the final stage.

However, as described above, the output code is "0" both when the input of the parallel A / D converter is originally the input which should be converted to "1" and when it is the input which should be originally converted to "0". "Is output. Therefore, if "1" is always added to the least significant bit, the output code will be "1" even if the input voltage is 0.
The correct conversion cannot be made. Therefore, in the conventional state, a cyclic serial-parallel A / D converter cannot be configured using a parallel A / D converter that outputs a value 1 LSB smaller than the conversion result.

In order to avoid this, the output code of the parallel A / D converter is output as it is as before, and when the upper bit and the lower bit are added, 1LSB of the upper bit is subtracted from the upper beat. A method can be considered. However, in this method, there is a problem in that the addition is required to be performed in the subtraction and the logic becomes complicated and the amount of hardware increases.

An object of the present invention is to provide a cyclic serial-parallel type A / D converter that solves the above problems by changing the comparison voltage only for the comparator that sends out the least significant bit.

[Means for solving problems]

The serial-parallel type A / D converter of the present invention is the parallel type A / D converter
This is a parallel type A / D converter that outputs a value 1 LSB smaller than the converted result as an output code, except for the N bit parallel type A / D converter.
If the A / D conversion result is "0", the output is "0", and if the input voltage is higher than the comparison voltage of each comparator, each comparator that constitutes the N-bit parallel A / D converter will output "1". This is a comparator that outputs and outputs "0" if the input voltage is smaller than the comparison voltage. The final parallel A / D conversion is performed when the upper bit and the lower bit are overlapped by 1 bit and added to obtain the output code. Only when the output code of the above is added, the output of the comparator having the reference voltage of the reference voltage / 2 ^{N + 1} among the comparators forming the N-bit parallel type A / D converter is added to the least significant bit to output the digital output. Configured to get the code.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, the parallel type A / D converter outputs the following code according to the input V _IN . However, Vref is a reference voltage.

That is, the input is Except when, the output code is the value with 1LSB smaller from the A / D conversion result.

The input of the second parallel A / D conversion to obtain the lower bit takes the difference between the input signal and the value obtained by D / A converting the value 1 LSB smaller than the first A / D conversion result. It is 4 times to match. Therefore, the input signal is V _IN (1) and the result of A / D conversion by the conventional A / D converter is m
Then, the output code of the A / D converter in the present invention is m
It becomes -1, and the input V _IN (2) for the second A / D conversion is as follows.

However, when m = 0, the output code is “0” and V _IN is V _IN (2) = 4V _IN (1) (b).

In order to realize the above, the switches of the capacitor array in the figure are switched as follows. During the period in which the switch Sr is turned on and the input is sampled, S _{0 to} S ₇ are connected to the input terminal side. Then S ₀ to S ₇ to switch to the reference voltage side or the ground side in response to the output of the comparators as the calculation period after turning off the switch Sr. However, switch Si is the output of the comparator
If Qi _-1 is "1", it is switched to the reference voltage side, and if Qi _-1 is "0", it is switched to the ground side. Note that S ₀ is always switched to the reference voltage side.

The output of the comparator outputs Qi = "1" when the input of the comparator is larger than the comparison voltage, and outputs Qi = "0" when the input of the comparator is smaller than the comparison voltage. Further, by formulating a charge conservation equation between the input sampling period and the calculation period, the equations (a) and (b) can be derived. The V _IN (2) thus obtained is again A / D converted by the parallel A / D converter to obtain the lower bit.

The obtained upper bit and lower bit are overlapped by one bit and added, but the lower bit is a value smaller by 1 LSB except when the input is "0".

In the present invention, when adding the high-order bit and the low-order bit,
In parallel A / D conversion when calculating the lower bit, the comparison voltage among the comparators that make up the parallel A / D converter (N is the resolution of the parallel A / D converter, and in the example of FIG. 1, N = 3, so the comparison voltage is The output of the comparator, ie, Q ₀ , is added to the least significant bit. Q ₀ is input If it is smaller, it is “0”, If it is larger, it is "1", so by adding this value to the least significant bit, the output code becomes a value that has been A / D converted correctly. The output code of the parallel A / D converter of the present invention outputs a value 1 LSB smaller than the output code of the conventional parallel A / D converter, as described above. As a result, when adding the output of the first stage and the output of the second stage, it is possible to prevent addition and subtraction from occurring. However, in the present invention, the first stage A / D
Since the same parallel type A / D converter is used for the conversion and the A / D conversion of the second stage, not only the output code of the first stage but also the output code of the second stage is 1LSB from the conventional A / D conversion result. It is a small value. Therefore, if the output result of the second stage is added as it is, the obtained addition result is
It is 1 LSB smaller. (However, when the input is 0, the output code is correct at 0.) Therefore, it is necessary to add 1LSB with an adder, but if 1 is simply added, the addition result will be 1 even when the input is 0. Will end up. To avoid this, 0 is added only when the input is 0, and 1 is added when the input is other than that. As a result, the added result becomes the correct A / D conversion result. To do so, add the output Q0 of the comparator, which is the lowest of the comparators that make up the parallel A / D converter and whose comparison voltage is Vr / 2 ^{N + 1} (Vr / 16 in the example of 3 bits). It should be done. Because Q0 outputs 0 if the input is 0 (when Vin <16 / Vr), 1 otherwise.
Is output, the necessary function can be obtained by adding the least significant comparator output.

Further, in order to add Q ₀ at the final conversion, as shown in FIG. 1, a switch may be provided so that it is closed only at the final conversion.

〔The invention's effect〕

According to the present invention, by adding the output of the least significant comparator in the final parallel type A / D conversion to the least significant bit, a parallel type A that outputs a value 1 LSB smaller than the A / D conversion result.
The / D converter can be used to perform cyclic serial-parallel A / D conversion. Further, as compared with the case of using the parallel type A / D converter which outputs the A / D conversion result as it is, it is not necessary to perform the subtraction in the addition portion, the logic is simplified and the amount of hardware can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the input / output relationship of a conventional A / D converter. Q _{0 to} Q ₇ …… Comparator, C _{0 to} C ₇ , Cf …… Capacitor, S
_{0 to} S ₇ , Sr …… Switch.

Claims (1)

[Claims] 1. A high-order first N-bit digital output is obtained by subjecting an input signal to A / D conversion by a parallel-type A / D converter having a resolution of N bits (N is a positive integer). A value obtained by multiplying the difference between the D / A converted value of the first digital output of the A / D converter and the input signal by 2 ^N-1 is used as the second input of the N-bit parallel type A / D converter. A / D conversion is performed by the parallel type A / D converter to obtain a lower second N-bit digital output, and the upper first N-bit digital output and the lower second N-bit digital output are 1 bit. Overlap and add (2N-
1) To obtain a digital code of bits and to obtain lower bits, a value obtained by D / A converting the second N digital output of the N-bit parallel A / D converter and the N-bit parallel A / D conversion A value obtained by multiplying the difference from the second input of the converter by 2 ^N-1 is A / D converted as a third input of the N-bit parallel A / D converter to obtain a third N-bit digital output, The method of overlapping the addition result by 1 bit and adding it to obtain the lower bits is repeated, and the parallel A / D conversion is performed M times (M is an integer of 2 or more) (MN-M + 1). ) In a serial A / D converter that obtains a digital output of bits, the parallel A / D converter is a parallel A / D converter whose output code is a value 1 LSB smaller than the result of A / D conversion, However, if the A / D conversion result of the N-bit parallel type A / D converter is "0", the output is "0", and the N-bit parallel type Each comparator that constitutes the A / D converter is a comparator that outputs “1” if the input voltage is higher than the comparison voltage of each comparator and outputs “0” if the input voltage is lower than the comparison voltage. When the bits are overlapped by 1 bit and added to obtain the output code, the final parallel A /
Only when the D conversion output code is added, the least significant bit is added with the output of the comparator of the N-bit parallel type A / D converter whose comparison voltage is the reference voltage / 2 ^{N + 1} A serial / parallel A / D converter characterized by obtaining an output code.