JPH0683070B2 - A / D converter - Google Patents

Description

The present invention relates to an analog / digital converter (A / D converter) for converting an analog voltage into a digital value, and further a serial / parallel A / D conversion. It is related to an A / D converter called a vessel.

(Prior Art) Parallel type of upper 3 bits and lower 3 bits for simplification
Consider a serial-parallel A / D conversion method in which an A / D converter is used and the upper bit and the lower bit are overlapped by 1 bit to obtain a conversion result of 5 bits.

With the serial-parallel type A / D conversion method, in the case of a two-stage configuration, the parallel type A / D converter at the first stage roughly performs A / D conversion to obtain the upper bits, and then performs A / D conversion at the first stage from the input signal. Subtract the minute, A / D convert the rest again with the parallel A / D converter to obtain the lower bits,
The upper bit and the lower bit are combined to obtain a conversion result with a predetermined resolution. One bit overlap when adding the high-order bit and the low-order bit means that the conversion of the second stage is performed within the range of 2 LSB of the high-order bit, and the conversion error of the first stage is corrected during the conversion of the second stage. be able to. Therefore, since the accuracy of the A / D converter in the first stage is 1/2 LSB of the resolution in the first stage, the accuracy required for the elements forming the A / D converter is also moderate. Specifically, do not overlap the high-order bit and the low-order bit.
To obtain the conversion result of 5 bits, the accuracy of ± 1/2 LSB of 5 bits is required, but to obtain the conversion result of 5 bits by overlapping the upper 3 bits and the lower 3 bits by 1 bit. Since the accuracy of ± 1 / 2LSB of 3 bits is sufficient, the required accuracy is four times different. This difference becomes more remarkable as the resolution increases and the requirement for element accuracy becomes more stringent.

Here, a method of obtaining the lower bits and a method of adding the upper bits and the lower bits will be considered. When subtracting the amount of A / DH conversion at the first stage from the input signal to obtain the lower bits, if the A / D conversion result at the first stage is subtracted as it is, positive and negative values of both signs are generated as the input of the second stage.

A three-bit A / D converter will be taken as an example and specifically described.

Generally, a conventional A / D converter converts an analog input voltage V _IN of 0 to Vr and outputs a digital code of “000” to “111”. At this time, the relationship between the input voltage and the output code is as shown in FIG. When the output code is represented by a normal decimal number, when 0 ≦ V _IN <Vr ₍₀₎ , D = 0 (1) Vr ₍ i ₋₁₎ ≦ V _IN <r ₍ i ₎ , D = i where i Is an integer of 1 to 6 (2) Vr ₍₇₎ ≤ V _IN <Vr D = 7 (3) where Vr ₍ m ₎ = {(2m + 1) / 16} Vr, m is an integer of 0 to 7 ( 4)

Assuming that the A / D conversion result is N and the analog voltage corresponding to the conversion result is Vad _(N) , Vad _(N) is Vad _(N) = N · Vr / 8 as shown in FIG. (5) As shown in Fig. 3, the input voltage V _IN is Vr ₍₃₎ ≤ V _IN <Vr ₍₄₎ (6) Vr ₍₃₎ = 7Vr / 16, Vr ₍₄₎ = 9Vr / 16 (7) , The output is D = 4. The analog voltage corresponding to this conversion result is Vad ₍₄₎ = 8Vr / 16 (8). Therefore, if the result of A / D conversion at the first stage (8Vr / 16) is subtracted as it is from the input signal to obtain the lower bits, depending on the size of the input signal, as the second stage input, Produces both signs. That is,
When the subtracted result is Vdif, 7Vr / 16 ≦ V _IN <8Vr / 16 −Vr / 16 ≦ Vdif <0 (9) 8Vr / 16 ≦ V _IN <9Vr / 16 0 ≦ Vdif <Vr / 16 ( 10) As a result, when the upper bit and the lower bit are overlapped by one bit and added, subtraction is actually required, and the hardware function becomes complicated. A / of a single power supply
It is inconvenient if the input voltage of the D converter is either positive or negative. This will be specifically described with reference to FIG. When subtracting the first-stage A / D conversion result from the input signal, the first-stage A / D
By subtracting 1 LSB less from the conversion result from the input signal, the subtracted voltage becomes a voltage corresponding to D-1 = 4-1 = 3. That is, Vad ₍₃₎ = 6Vr / 16 (11) is subtracted. Therefore, the result of subtraction V
_{The dif ′} is Vr / 16 ≦ V _{dif ′} <3Vr <16 (12), and has only one positive sign. Since the result of subtraction becomes the input signal of the second stage, the input of the second stage has only a positive one sign. Generally, only one sign is positive or negative, but in the above example, only one sign is positive.

Therefore, the value of the upper bit when adding the upper bit and the lower bit is 1LSB less than the original A / D conversion result as the output code of the A / D converter in the first stage (“3” in this example). , The corresponding D / A converted value (also Vad ₍₃₎
Is subtracted from the input signal to obtain the second-stage input, the second-stage input has only a positive sign. If the input in the second stage is only one positive sign, the A / D conversion result is also only one positive sign, so when adding the high-order bit and the low-order bit, only addition is performed and there is no subtraction. . If both positive and negative signs occur in the input of the second stage, the A / D of the second stage
The converter needs an A / D converter that can handle both positive and negative inputs, and also needs to add (subtract) positive and negative numbers when adding.

However, if the A / D conversion result of each stage is originally "0" and a value smaller by 1 LSB is used as the output code of the A / D converter, the output code will become negative and inconvenience will occur. In that case, 0 "is output as it is. Therefore, when the input of the parallel type A / D converter is originally "0" or "1", the output code is 0 in both cases.

In this way, in the serial-parallel A / D conversion method, the high-order bit and the low-order bit are overlapped and added, and the predetermined A / D
In the method that obtains the D conversion result, the parallel A / D converter at the first stage outputs an A / D value that is 1 LSB less than the normal A / D conversion result.
A converter that outputs a D / A converter correspondingly is an excellent IC for a single power supply. This method is described in detail in Japanese Patent Application No. 59-079504.

When using a multi-stage configuration, use the A / D converter that outputs the conventional A / D conversion result as is only for the final parallel A / D converter, and use the above A / D converter otherwise. Good.

(Problems to be Solved by the Invention) In the serial / parallel A / D conversion method described in the section (Prior Art) above, the parallel A / D conversion of each stage is cyclically made into the same parallel type A / D conversion. Consider running with a / D converter. If so, the conversion speed becomes slower, but the chip area and power consumption become much smaller, and there are many advantages when considering integration with other digital signal processing circuits.

However, if a parallel type A / D converter that outputs a value 1 LSB smaller than the original conversion result is used as the parallel type A / D converter, the final stage A / D conversion result will also be 1 LSB. Output a small value. Therefore, it is necessary to add "1" to the obtained code to make it a correct code. To do this, "1" may be added to the least significant bit when adding the output code of the upper bit and the output code of the last stage.

However, as explained in the (Prior Art) section, parallel A /
When the input of the D converter is originally converted to "0" or "1" Vref is the reference voltage of the parallel A / D converter, Np is the resolution of the parallel A / D converter, V _IN is the input voltage of the parallel A / D converter), and the output code of the parallel A / D converter Is "0", so A in the final stage
Input that output code of / D conversion result is "0" (No is the resolution of the entire series-parallel A / D converter),
If "1" is added to the least significant bit, the output of the serial / parallel A / D converter becomes "1", and even if the input is 0, "0" will not be output as the output. To avoid this, when adding "1" to the least significant bit, it is judged whether the conversion result of the final stage is originally "0" or "1", and it is originally "0". "1" in the least significant bit except when
Must be added.

Therefore, if the parallel A / D conversion is cyclically performed by the same parallel A / D converter in the conventional method, the input of the parallel A / D converter will be “only” when the conversion is at the final stage. 0 "
Therefore, it becomes necessary to determine whether or not the control system and the adder are complicated.

(Means for Solving the Problems) The means provided by the present invention for solving the above problems are as follows: The input signal is a parallel type A / D converter having a resolution of N bits (N is a positive integer). A higher first N-bit digital output is obtained by D / D conversion, and the difference between the value obtained by D / A converting the first digital output of the N-bit parallel A / D converter and the input signal is 2
A value obtained by multiplying by ^N-1 is used as the second input of the N-bit parallel A / D converter, A / D converted by the parallel A / D converter, and the second
Of the upper N-bit digital output and the lower second N-bit digital output are overlapped by 1 bit and added (2N-1)
In order to obtain a digital code of bits and to obtain lower bits, a value obtained by D / A converting the second N-bit digital output of the N-bit parallel A / D converter and the N-bit parallel A / D
A value obtained by multiplying the difference from the second input of the converter by 2 ^{N-1 is} A / D-converted as the third input of the N-bit parallel A / D converter to obtain a third value.
The operation of obtaining the N-bit digital output of the above and adding it by overlapping it with the above addition result by 1 bit to obtain the lower bits is repeated M times (M is an integer of 2 or more) in parallel type A / D. A serial-parallel A / D converter that performs conversion to obtain a (MN-M + 1) -bit digital output, wherein the parallel A / D converter is "0" when the input is a reference voltage.
When the input is 0, it is converted so that it becomes “2 ^N ”, but the output code outputs the value obtained by subtracting 1 LSB from the normal A / D conversion result; when the reference voltage is Vref, the input voltage V _IN is Outputs “0” and the input voltage is Will output "1" and The output increases by 1 as the input voltage decreases; Outputs a binary code that is a decimal number n (1n2 ^N
-2), the input voltage is Then, a binary code of (2 ^N -1) is output; when the digital output of the parallel A / D converter is D / A converted, the digital output of the parallel A / D converter is m in decimal. If so, the result of D / A conversion is "0" and "1" of the (MN-M + 1) bit code obtained by repeating addition with the upper bit and the lower bit overlapping by 1 bit It is characterized in that the code obtained by the above is used as an output code.

(Operation) In the present invention, when converting the lower bit, the upper bit is converted within the range of 2 LSB, and the upper bit and the lower bit are set to 1
A serial-parallel A / D conversion method that overlaps bits and adds to obtain the A / D conversion result.When the same parallel A / D converter is used to convert upper bits and lower bits, the parallel A / D
When using a parallel type A / D converter that makes the output code of the converter 1LSB smaller than the actual conversion result, the A
Simplifies the control system and adder by eliminating the need to judge whether the input of the parallel A / D converter is originally "0" during / D conversion.

(Example) Next, an Example is given and this invention is demonstrated in more detail.

One embodiment of the present invention is shown in FIG. In the figure, an example using a 3-bit parallel A / D converter is shown for the sake of simplicity. An example in which the upper 3 bits and the lower 3 bits are obtained by performing the A / D conversion twice and the results are overlapped by 1 bit and added to obtain the output code from the conversion result of 5 bits will be described below.

The 3-bit parallel A / D converter shown in FIG. 1 outputs the following code according to the input V _IN of the parallel A / D converter. Vref is a reference voltage.

That is, when the reference is Vref, conversion is performed to be "0" when the input is Vref and 2 ^N when the input is 0, and the value 1 LSB smaller than the conversion result is used as the output code. However, if the input is In the case of, the A / D conversion result becomes "0", and if it is reduced by 1LSB, it becomes negative, so the output code is "0".
The D / A converter also outputs a value corresponding to an output code that is 1 LSB smaller than the original conversion result. That is, if the output code is "m", the value of mVref / 8 is subtracted from the input measured with Vref as the reference. Here, a 3-bit parallel A / D converter and a D / A
This is described in the example of the converter. If m is the output code,
If the reference voltage is Vref, 1 LSB (quantization step) of the 3-bit D / A converter is Vref / 2 ³ = Vref / 8, so the output of the D / A converter corresponding to the output code m is m・ Vref / 8. In order to obtain the lower bit, the remaining voltage after subtraction is multiplied by 4 and the input range is adjusted to be the input based on Vref of the second parallel A / D converter. Figure 2 shows the relationship between the input voltage and the input of the second parallel A / D conversion. If the input signal with Vref as the reference is V _IN (1) and the original conversion result is “n” and “n−1” is the output code, parallel for the second parallel A / D conversion. Input V _IN (2) with reference to Vref to the type A / D converter is And the value based on ground Is the input of the second parallel A / D conversion. In order to realize this, the switches of the capacitor array in FIG. 1 are switched as follows. That, S ₀ to S ₇ period for sampling an input to the switch Sr is turned ON is connected to the S ₀ to S ₇ are input terminal side, then after OFF the switch Sr, the computation period by the output of the comparators Is switched from the reference voltage side to the ground side. At this time, the switch Sr is output Q _1-1 of comparator if "H" reference voltage side, Q _1-1 is "L" is long if switched to the ground side. However, S ₀ is always switched to the reference voltage side. However, the comparator outputs Q ₁ = “H” if the input of the comparator is larger than the comparison voltage of each comparator, and outputs Q ₁ = “L” if it is smaller than the comparison voltage. Formulas (1) and (2) are established by forming the formulas of charge conservation during the input sampling period and the calculation period. The lower bit is obtained by converting the input of the second parallel A / D conversion obtained in this way.

The high-order bit and the low-order bit obtained by conversion are overlapped by 1 bit and added, but each code has a value that is 1 LSB smaller, and the code has a reference voltage of "0" and a ground voltage of 2 ³ Since they are codes (in decimal), we have to correct them to normal codes.

In the present embodiment, the high-order bit and the low-order bit obtained as described above are overlapped by one bit and added, and the result is inverted to obtain a normal output code. This will be specifically described. Input signal voltage is It was. When 3-bit A / D conversion is performed on the basis of Vref, it is "110" (decimal 6), but the output code is "101" because the value 1 LSB smaller is used as the output code. At this time, the input voltage for the second A / D conversion is The second A / D conversion result is "011" and the output code is "010". When the high-order bit and the low-order bit are overlapped by one bit and added, the result is "10110", which is inverted and "01001" becomes the output code. This value is, of course, the result of A / D conversion of V _IN (1) into 5 bits. The advantage of this method is that the input is If so, output code "00000", In that case, “00001” is output, and it is not necessary to detect whether the input is “0” during A / D conversion at the final stage, and the correct result can be automatically obtained (as described above, in the conventional example It was necessary to detect whether the input was "0" during A / D conversion at the final stage). Therefore, in this embodiment, the control system and the adder are simpler than the conventional example. Further, since the addition result of the high-order bit and the low-order bit can be inverted only by providing one inverter in the output line of each bit, it can be incorporated as a part of the output buffer and the hardware increase can be ignored.
Therefore, since the control system and the adder are simplified, the amount of hardware is reduced and the probability of error is reduced.

(Effects of the Invention) As described above, according to the present invention, it is possible to provide a high-precision A / D converter that can simplify the control system and adder parts and has a small amount of hardware. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. If all the capacitances of C _{0 to} C _{7 in} this diagram are C, the capacitance value of Cf is
It is 2C. FIG. 2 is a diagram showing the relationship between the input voltage V _IN (1) and the input V _IN (2) of the parallel type A / D converter at the time of the second A / D conversion. FIG. 3 is a diagram showing the relationship between the input and output of the 3-bit A / D converter.

Claims (1)

[Claims] 1. A high-order first N-bit digital output is obtained by subjecting an input signal to A / D conversion by a parallel-type A / D converter having a resolution of N bits (N is a positive integer). A value obtained by multiplying the difference between the D / A converted value of the first digital output of the A / D converter and the input signal by 2 ^N-1 is used as the second input of the N-bit parallel type A / D converter. The parallel A / D converter performs A / D conversion to obtain a lower second N-bit digital output, and outputs the upper first N-bit digital output and the lower second N-bit digital output. In order to obtain a digital code of (2N-1) bits by adding them by overlapping them by 1 bit and further obtaining the lower bit, the second of the N-bit parallel type A / D converters is used.
2 ^N-1 times the difference between the value obtained by D / A converting the N-bit digital output of the above and the second input of the ^N- bit parallel A / D converter. A / D as the third input of
The calculation is repeated to obtain the third N-bit digital output, and the addition result is overlapped by 1 bit and added to obtain further lower bits, and the operation is repeated M times (M is an integer of 2 or more) in total. Perform parallel A / D conversion (MN
In a serial-parallel type A / D converter that obtains a digital output of −M + 1) bits: The parallel type A / D converter is “0” when the input is the reference voltage and “2 ^N ” when the input is 0. However, the output code is the value obtained by subtracting 1LSB from the normal A / D conversion result; if the reference voltage is Vref, the input voltage V _IN is Outputs “0” and the input voltage is Will output "1" and The output increases by 1 as the input voltage decreases; Outputs a binary code that is a decimal number n (1n2 ^N
-2), the input voltage is Then, a binary code of (2 ^N -1) is output; when the digital output of the parallel A / D converter is D / A converted, the digital output of the parallel A / D converter is m in decimal. If so, the result of D / A conversion is (MN-M +) obtained by repeating the addition in which the upper bit and the lower bit are overlapped by 1 bit.
1) Serial-parallel type A / D characterized in that a code obtained by inverting "0" and "1" of a bit code is used as an output code.
converter.