JPH0683216B2 - Receiver with collision detection function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a CSMA / CD system (Carrier) as an access system.
The present invention relates to a receiver with a collision detection function for detecting a collision with a data transmission in a bus type local network using a Sense Multiple Access With Collision Detection method).

[Conventional technology]

In FIG. 5, a dipulse code is considered as the 1B2B code, and an example applied to optical transmission is, for example, "32M using CSMA / CD control.
A transmission / reception system including a conventional receiver with a collision detection function shown in "Study on b / S optical star transmission system" (Technical report of the Institute of Electronics and Communication Engineers CS83-110, 1983) is shown. In the figure,
(1) is a transmitter, (2) is a dipulse encoding circuit,
(3) is a light emitting element drive circuit, (4) is a light emitting element, (5)
Is an optical fiber, (6) is an optical fiber, (7) is an optical fiber, (8) is a receiving device, (9) is a light receiving element, (1)
(0) is a preamplifier circuit, (11) is a partial response (1, -1) filter (hereinafter abbreviated as PR (1, -1) filter), (12) is a first comparison circuit, and (14) is. Is a timing extraction circuit, (15) is the first shift register, (16) is register 1, (17) is register 2, (18) is register 3,
(24) is a block synchronization circuit, (25) is a first code rule violation detection circuit (hereinafter abbreviated as the first CRV detection circuit), (29).
Is a collision determination circuit.

FIG. 6 is a waveform diagram of each part of a conventional receiver with a collision detection function. In the figure, (10a) is an optical signal received first (hereinafter abbreviated as a main signal), (10b) is an optical signal received later (hereinafter abbreviated as a collision signal), and (11a) is a partial of the main signal. Response (1, -1) filter output (hereinafter abbreviated as main signal PR (1, -1) filter output), (11b) is a collision response partial response (1, -1) filter output (hereinafter collision signal PR (Abbreviated as (1, -1) filter output),
(11c) is the output of the partial response (1, -1) filter that combines the main signal and the collision signal (hereinafter PR (1,
-1) Abbreviated as filter output. ), (12a) is the first comparison circuit output, (14a) is the first clock, (16a) is the register 1 output, and (25a) is the first coding rule violation detection circuit output (hereinafter referred to as the first CRV detection). (Abbreviated as circuit output), (30) is +
Side thresholds, (31a) and (31b), are the sample phases of the first clock.

FIG. 7 is a phase relationship diagram between the main signal and the collision signal. In the figure, (11d) shows the PR (1, -1) filter output eye pattern of the main signal, and (11e) shows that the phase difference with the main signal is 0. PR when
(1, -1) filter output eye pattern, (11f) has a phase difference from the main signal PR (1, -1) filter output eye pattern when
1) is the sample phase of the first clock.

FIG. 8 is an explanatory diagram showing the coding rules of each part in the conventional receiver with a collision detection function.

Next, the operation will be described. The signal flow will be described with reference to FIG. In the transmitter (1), the packet transmission data is encoded by the dipulse encoding circuit (2) (0 → 10, 1 → 01)
After that, the light emitting element driving circuit (3) causes the light emitting element (4)
Is intensity-modulated and output as an optical signal to the optical fiber (5). The output signal of the optical fiber (5) is input to the optical star coupler (6). The optical star coupler (6) outputs an input optical signal to each output optical fiber including the optical fiber (7) at an equal level. The output of the optical fiber (7) is input to the light receiving element (9) of the receiving device (8) and converted into a photoelectric signal. The output signal of the light receiving element (9) is amplified by the preamplifier circuit (10) and then input to the PR (1, -1) filter (11).

The operation after the PR (1, -1) filter (11) will be described with reference to FIG. In the figure, it is assumed that the collision signal (10b) is received while the main signal (10a) is being received. The PR (1, -1) filter (11) has a function of subtracting a signal obtained by delaying the input signal by 1 / 2f ₀ [seconds] from the input signal. The output of the PR (1, -1) filter (11) is (11a) for the main signal (10a) and (11c) for the collision signal (10b), and the waveform at the time of collision is the combination of both (11b). Become.

A method of detecting a collision from the output of the PR (1, -1) filter (11) will be described with reference to FIG. There are 4 types of transmission data, 2
Classified as bit data. PR after dipulse coding
The transmission data passed through the (1, -1) filter (11) is 3
It is converted into a value waveform (AC waveform in the sense of having + and-amplitudes). The zero level of the ternary waveform is “0” that can be obtained by subtracting 0 and 0 of the dipulse encoder output and “0 ^* ” that can be obtained by subtracting 1 and 1. The first comparison circuit (12) discriminates the ternary waveform by the threshold value (30) which is shifted slightly above the zero level. The output of the first comparing circuit (12) at the time of non-collision is sampled at the first clock (14a) having a frequency of 2f ₀ [Hz], and consecutive 3 bits are accumulated in the first shift register (15). Register 1 (16) of the first shift register (15)
The waveform of the output Q ₁ of is (16a) in FIG. FIG. 8 shows the outputs Q ₃ , Q ₂ , Q of the register 1 (16), the register 2 (17) and the register 3 (18) corresponding to the sampled result of the PR (1, -1) filter (11) output. Indicates ₁ . When a collision occurs, a zero level is transferred above the threshold value (30) by the collision signal, and the first comparison circuit (12) detects this and outputs (12a) in FIG. In FIG. 8, the case where the second Q ₂ in the 3-bit sequence changes is shown as a coding rule violation 3-bit sequence. When a zero level occurs in the output of the PR (1, -1) filter (11), it is easy to detect the coding rule violation 3-bit sequence even if the collision signal level is small. The first CRV detection circuit (25) determines the output of the first shift register (15) Q ₁ , Q ₂ , and Q ₃ every 1 / f ₀ [second] for the presence of a code rule violation and determines the code rule. If a violation is detected, the sixth
Collision determination circuit (29) for the detection pulse shown in Figure (25a)
Output to. The clock for detecting the violation of the coding rule with a cycle of 1 / f ₀ [second] is set by the block synchronization circuit (24) to the main signal (10
Immediately after the start of reception of a), the sample result for the zero level of the output of the PR (1, -1) filter (11) is output to the output Q ₂ of the second register (17) of the first shift register (15). It is synchronously pulled in to the phase, and thereafter held in this phase and output.

In FIG. 8, there are two types of zero level, “0” and “0 ^* ”, but “0 ^* ” is generated by subtraction of 1 and 1 (ON and ON of optical signal) and is a light receiving element ( Since a lot of shot noise occurs in 9), it is better not to use it for collision detection because the coding rule violation is likely to occur due to noise even when there is no collision.
Hereinafter, the description will be made assuming that the code rule violation occurring at "0 ^* " is ignored.

The collision determination circuit (29) counts the number of output pulses of the CRV detection circuit (25), and when the count value exceeds a specified value, determines that a collision has occurred and outputs a detection signal.

Next, a case where it is difficult to detect a collision in the conventional receiving device with a collision detection function will be described with reference to FIG. (11d) is P
This is the eye pattern of the main signal at the output of the R (1, -1) filter (11). After identification by the first comparison circuit (12), the first
Frequency in the first register (16) of the shift register (15) of
The phase sampled on the first clock at 2f ₀ [Hz] (3
1) is shown in the figure. (11e) is an eye pattern of a signal that collides with the main signal with a phase difference of 0 (the break point of the encoding block temporally overlaps the main signal and the collision signal). The zero level of the main signal due to the collision is transferred to ± hmax. The first comparison circuit (12) detects a code rule violation when it is transferred to the + side, but cannot detect it when it is transferred to the-side. (11f) is the phase difference from the main signal It is the eye pattern of the signal that collided with. The zero level of the main signal due to the collision is transferred by ± hmin. In this case, +
Since the amplitude transferred to the side is small, a missed detection may occur.

[Problems to be solved by the invention]

As described above, in the conventional receiver with a collision detection function, since there is only one comparator circuit that detects fluctuations due to a zero-level signal collision, and there is only one collision sampling point, therefore, there is a difference in collision phase. However, there is a drawback that the amount of transfer at the zero level is small and it is easy to miss the collision detection.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a receiver with a collision detection function capable of improving the deterioration of the collision detection characteristics due to the collision phase.

[Means for Solving Problems] A reception device with a collision detection function according to the present invention is a transmission signal transmitted by intensity-modulating packet transmission data having a bit rate f ₀ [bits / second] after being converted into a 1B2B code. And a PR (1, -1) filter that performs AC conversion by subtracting a signal obtained by delaying the received signal by 1 / 2f ₀ [sec] from the received signal, and the PR (1, -1) filter output Input the PR (1,
-1) A first comparison circuit for discriminating a signal by a threshold value slightly shifted from the zero level of the filter output to the upper side, and PR (1,-
1) A second comparison circuit for discriminating signals with a threshold value slightly shifted to the lower side of the zero level of the filter output, and the output of the first comparison circuit is sampled by sampling with the first clock of frequency 2f ₀ [Hz]. The outputs of the first CRV detection circuit and the second comparison circuit, which detect the violation of the code transition rule by monitoring the subsequently obtained continuous 3-bit pattern every cycle 1 / f ₀ [second], are compared with the first comparison circuit. 1st frequency 2f ₀ [Hz] to sample the output of
Second obtained through a phase shift circuit that delays the clock of
3 consecutive clocks sampled at each clock
A second CRV detection circuit for monitoring a bit pattern every cycle 1 / f ₀ [second] to detect a code transition rule violation, and a first or second CRV detection circuit.
Of the CRV detection circuit output having a delay time of 1 / f ₀ [seconds], the delay circuit output having the first input, and the second or first CRV detection circuit output having the second And a logical sum circuit as an input, and outputs the logical sum circuit output as a collision detection signal.

[Action]

The receiver with collision detection function according to the present invention is PR (1,-
1) The first and second comparison circuits having threshold values above and below the zero level generated in the filter output make it possible to detect whether the zero level transfer due to a collision is above or below. In addition, the output of the first comparison circuit is set to the frequency 2f ₀
By sampling the output of the second comparison circuit with the second clock, which is obtained by sampling the first clock of [Hz] and delaying the first clock through the phase shift circuit, Even if the transfer amount at the signal zero level is the minimum, the transfer amount more than that is obtained in the other clock phase. Furthermore, the first and second frequencies 2f
Two CRV pulses may be generated in the same bit due to the difference in the clock phase of ₀ [Hz]. At this time, the first ( Or, the output of the second CRV detection circuit is 1 / f
₀ [seconds] After delaying and ORing, it is input to the collision determination circuit. By the above means, the collision miss rate can be improved.

Example of Invention

FIG. 1 shows the configuration of a transmission / reception system including an embodiment of a receiver with a collision detection function according to the present invention. In the figure,
The same reference numerals as those in FIG. 5 denote the same parts, (13) is the second comparison circuit, (19) is the second shift register, and (20).
Is a register 4, (21) is a register 5, (22) is a register 6, and (26) is a second coding rule violation detection circuit (hereinafter referred to as a second CR).
Abbreviated as V detection circuit. ), (27) are delay circuits, (28) is OR
The gate (23) is a phase shift circuit.

FIG. 2 is a waveform diagram of each part of the receiver with a collision detection function shown in FIG. 1 when considering the biphasic code as the 1B2B code. In the figure, (13a) is the output of the second comparison circuit, (20a ) Is the output of the register 4, (26a) is the output of the second coding rule violation detection circuit (hereinafter abbreviated as the second CRV detection circuit output), (27a) is the delay circuit output, (24a) is the block synchronization circuit output, ( 28a) is the output of the OR circuit, (32) is the-side threshold value, (33a), (33b) are the first clock, (34a),
(34b) are the respective sample phases of the second clock.

FIG. 3 is a phase relationship diagram of the main signal and the collision signal. In the figure, (11f) is the PR (1, -1) filter output of the collision signal in the phase where the signal collision at the + side threshold is the most difficult to detect. Eye pattern, (11g) is the PR (1, -1) filter output in the phase where the collision signal is the most difficult to detect with the-side threshold,
(32) is a-side threshold.

Next, the operation will be described. Referring to FIG. 1, the receiver with a collision detection function according to the present invention is different from the conventional one in a second comparison circuit (13), a second shift register (19) (register 4 (20), register 5 (21)). , Register 6 (22)),
A second CRV detection circuit (26), a delay circuit (27), an OR circuit (28), and a phase shift circuit (23) are added, and the other parts perform the same operations as in the conventional case.

In FIG. 1, the output of the PR (1, -1) filter (11) is input to the second comparison circuit (13). A second comparator circuit (13) has a threshold slightly below the zero level of the PR (1, -1) filter output and detects when the zero level is driven down by a signal collision. In the second shift register (19), the frequency 2f output from the timing extraction circuit (14)
The first clock of ₀ [Hz] is set to τ by the phase shift circuit (23).
[Second] The output of the second comparison circuit (13) is sampled by the second clock obtained with a delay and the continuous 3-bit sequence is stored in the second shift register (19). Second CRV
The detection circuit (26) is the first of the second shift register (19).
Output Q ₆ of register (20), output of second register (21)
Q _5, detects the coding rule violation pattern from the output Q ₄ of the third register (22).

A method of detecting a coding rule violation pattern will be described with reference to FIGS. 2 and 4. The operation of the first comparison circuit (12) having a threshold value on the + side of the output level of the PR (1, -1) filter (11) is the same as that of the conventional example (FIGS. 6 and 8). PR (1,-
1) The second comparator circuit (13) having the threshold value (32) on the minus side of the filter (11) output zero level detects that the zero level is transferred to the lower side of the threshold value (32) by the collision signal, Second
Output (13a) in the figure. In FIG. 4, 3
A case where the second Q ₅ in the bit sequence changes is shown as a coding rule violation 3 bit sequence. As described above, by providing the comparator circuits (12) and (13) having threshold values above and below the PR (1, -1) filter (11) output zero level, the zero level can be increased or decreased by the collision signal. It is possible to detect the violation of the coding rule even if it is transferred to.

Next, the effect of giving a difference to the clock phase of the frequency 2f ₀ [Hz] input to the first shift register (15) and the second shift register (19) will be described with reference to FIG. In FIG. 3, the sampling point (34) of the second shift register (19) is the first shift register (15).
The sampling point (33) is delayed by τ [seconds].
(11f) is the sampling point (3
In 3), the break block A of the collision signal coding block
Is generated, and the collision signal eye pattern collides in a phase in which the amplitude has the minimum value h. At the first sampling point (33), collision oversight is likely to occur as in the conventional case. But,
At the second sampling point (34), a large collision signal amplitude (h ₁ ) is obtained at this time, and collision detection can be easily performed. (11g) is a collision signal eye pattern in which a collision signal encoding block B occurs at the sampling point (34) of the second shift register and the collision signal amplitude becomes the minimum value h. In this case, collision oversight occurs at the sampling point (34), but a large collision signal amplitude (h ₂ ) is obtained at the sampling point (33), and collision detection can be performed easily. As described above, the difference between the sampling points in the first shift register (15) and the difference in the second shift register (19) makes it possible to improve the collision miss. Note that the PR (1, -1) filter (11) output zero level "0"
Since the waveform (generated from the subtraction of 0 and 0) has an upper right waveform, the clock of the first shift register (15) sampling the output of the first comparison circuit (12) having a threshold value on the + side is on the − side. It is advantageous to set the phase ahead of the clock of the second shift register (19) for sampling the output of the second comparison circuit (13) having a threshold value, because collision error detection is less likely to occur.

Next, the effect of the delay circuit (27) will be described with reference to FIG. In Fig. 2, the phase difference between the main signal (11a) and the collision signal (11b) at the PR (1, -1) filter (11) output is Is. At this time, the first comparison circuit (12) and the second comparison circuit (13) transfer the zero level exceeding the thresholds (30) and (32) by the collision signal at the sampling points (33a) and (34a), respectively. Is detected. Outputs Q ₃ and Q of the register 1 (16) and the register 4 (20) of the first shift register (15) and the second shift register (19)
₆ becomes (16a) and (20a). First CRV detection circuit (2
5) and the second CRV detection circuit (26) are sampled at the same clock of the cycle 1 / f ₀ [sec] output from the block synchronization circuit (24), so CRV detection pulses are output at the same time slot. (25a, 26a). If the CRV number is counted in the collision determination circuit (29) by taking the logical sum as it is, only one CRV is counted and the collision detection is delayed. The delay circuit (27) outputs the output of the first CRV detection circuit (25) to 1 / f ₀
[Second] Delayed output, so the CRV count is
It is counted as 2 in 9). 1 / f with delay circuit
Even if the delay is ₀ [seconds], the CRV pulse will be generated two time slots ahead (since the CRV is not detected in the "0 ^* " part), so that the CRV pulse does not overlap.

When the sample phases of the first shift register (15) and the second shift register (19) are the same phase, the CRV pulse is output from only one of the CRV detection circuits, so the delay circuit (27) has no effect. When the sample phase of the first shift register (15) is different from that of the second shift register (19), CRV pulses may be simultaneously output from the two CRV detection circuits, and the delay circuit (27 ) Effect is exhibited.

〔The invention's effect〕

As described above, according to the present invention, the first comparison circuit for discriminating the signal by the threshold value slightly deviated to the upper side of the zero level of the output of the PR (1, -1) filter and the PR (1, -1) filter are provided. A second comparator circuit for discriminating a signal by a threshold value slightly shifted to the lower side of the zero level of the output, and sampling the output of the first comparator circuit with the first clock of frequency 2f ₀ [Hz], First
By sampling the output of the second comparison circuit with the second clock obtained by delaying the clock of
Even if the coded block break of the collision signal occurs for either clock, the sample point and the coded block break do not match for other clocks, and a large collision signal amplitude is obtained. To be Therefore, the zero-level fluctuation due to the collision signal can be surely detected, and the collision can be surely detected regardless of the collision phase.

In addition, 1 / f that receives the output of the first or second CRV detection circuit
By placing a delay circuit having a delay time of ₀ [second] after the first CRV detection circuit or the second CRV detection circuit, even if the CRV pulses are output from the two CRV detection circuits at the same time, they are separately output. It is possible to count and efficiently detect collision.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is 1B.
FIG. 3 is a waveform diagram of respective parts of the transceiver with a collision detection function shown in FIG. 1 when a biphasic code is considered as a 2B code, FIG. 3 is a phase relationship diagram of a main signal and a collision signal, and FIG. FIG. 5 is an explanatory view showing coding rules of each part in the receiver with collision detection function, FIG. 5 is a configuration diagram showing a transmission / reception system including a conventional receiver with collision detection function, and FIG. 6 considers biphasic code as 1B2B code. 5 is a waveform diagram of each part of the receiver with a collision detection function shown in FIG. 5, FIG. 7 is a phase relationship diagram of a main signal and a collision signal, and FIG. 8 is a code rule of each part in a conventional receiver with a collision detection function. FIG. In the figure, (1) is a transmitter, (2) is a 1B2B encoding circuit,
(3) is a light emitting element drive circuit, (4) is a light emitting element, (8)
Is a receiver, (9) is a light receiving element, (10) is a preamplifier circuit, (11) is a partial response (1, -1) filter, (12) is a first comparison circuit, and (13) is a first comparator circuit. 2 comparison circuit, (14) timing extraction circuit, (15) first shift register, (19) second shift register, (24) block synchronization circuit, (25) first code rule Violation detection circuit, (26) second code rule violation detection circuit, (23) phase shift circuit, (27) delay circuit, (28) OR circuit, (29)
Is a collision determination circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A transmission signal received by converting the packet transmission data having a bit rate f ₀ [bits / sec] into a 1B2B code and intensity-modulating the transmission signal, and converting the reception signal from the reception signal to 1 / 2f ₀
[Second] Partial response (1, -1) filter that performs AC conversion by subtracting the delayed signal, and input of the partial response (1, -1) filter output as the partial response (1, -1) filter output A first comparing circuit for discriminating a signal with a threshold value slightly deviated to the upper side of the zero level, and a signal discrimination with a threshold value slightly deviated to the lower side of the zero level of the partial response (1, -1) filter output. The output of the second comparison circuit and the output of the first comparison circuit are sampled at the first clock having a frequency of 2f ₀ [Hz], and a continuous 3-bit pattern obtained after sampling is sampled every cycle 1 / f ₀ [second]. A first code rule violation detection circuit for monitoring and detecting a code transition rule violation, and an output of the second comparison circuit for a first frequency 2f ₀ [Hz] for sampling the output of the first comparison circuit. Ku The detecting the monitoring code transition rule violation three bits pattern continuing obtained after sample sampled at a second clock obtained through a phase shift circuit for delaying the click every period 1 / f ₀ [sec] No. 2 code rule violation detection circuit, a delay circuit having a delay time of 1 / f ₀ [seconds] with the first or second code rule violation detection circuit output as an input, and the delay circuit output as a first Collision detection characterized by comprising a logical sum circuit having an input and an output of the second or first coding rule violation detection circuit as a second input, and outputting the logical sum circuit output as a collision detection signal. Receiver with function.