JPH0683580A - Buffer memory - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity of a buffer memory. CONSTITUTION:The buffer memory of the first-in first-out system where a memory 1 whose data width bits are M bits and whose address bits are N bits is provided with a write port operated by a memory write signal and a read port operated by a memory read signal and write and read are implemented independently has a data register 6 whose bit width is M bits and a multiplexer 7 selecting an output of the memory 1 to a data output of a data register 6 when a prescribed condition is established and leading the data to the read port.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in-first-out system buffer memory used in an information processing apparatus or the like.

[0002]

2. Description of the Related Art In a first-in-first-out buffer memory, which is often used in an information processing apparatus, particularly a pipeline type circuit in which a plurality of processors are arranged in series, various processes are required depending on the state of data accumulation. For example, when reading is performed more frequently than writing, the buffer memory is in an empty state, but the reading side circuit needs to detect this and stop reading.

Conventionally, in this processing, an empty signal is output when the buffer memory is in an empty state, and the reading side circuit does not receive the data on the data bus until the empty signal is released, and waits for the reading operation. It was common.

[0004]

In this conventional buffer memory, the processing of the processor in the subsequent stage is faster than that of the processor in the preceding stage, and when the buffer memory becomes empty for a long time or frequently, the latter stage memory is While the processor is on standby, processing time is wasted, and a circuit for performing these processings is required, resulting in an increase in hardware. Further, when it is desired to perform a process corresponding to another state instead of the empty state, for example, when a certain specified value in the buffer memory capacity is satisfied, this cannot be dealt with.

[0005]

A buffer memory of the present invention is a write port that operates with a memory write signal and a read port that operates with a memory read signal for a set of memories having a data width of M bits and an address of N bits. In a first-in-first-out type buffer memory capable of independently performing writing and reading, an M-bit width data register and an output of the memory when the certain condition is satisfied. A multiplexer for switching to the data output of the data register and leading to the read port is provided.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, a memory block 1 is a memory block having an M-bit width and a depth of N bits, a write address pointer 2 is a register for holding a write address to the memory block 1, and a read address pointer 3 is a memory block 1. A register for holding a read address from the data counter, the data number counter 4 is a counter that is incremented each time the memory is written, and decremented each time the memory is read, and the comparator 5 has a value of the data number counter 4 of "0".
, A data register 6 is a register having a width of M bits and a depth of 1 bit, and a multiplexer 7 is a switching circuit for switching the output of the memory block 1 and the output of the data register 6 in response to the empty signal. Is.

The former processor (not shown) writes in advance to the data register 6 the data indicating the memory empty to be output to the latter processor (not shown) connected to the read port when the memory block 1 is empty, and performs the processing. Start. When the memory block 1 becomes empty, the data number counter 4 becomes "0", the comparator 5 switches the multiplexer 7, the data in the data register 6 is output to the read port, and the subsequent processor immediately executes the processing routine at the time of memory empty. To do.

According to the present embodiment, it is possible to eliminate the waiting dead time of the subsequent processor when the buffer memory is empty.

FIG. 2 is a block diagram showing a second embodiment of the present invention, and the constituent parts in the embodiment shown in FIG. 1 are designated by common reference numerals.

In this embodiment, the data number register 8
Is added, and the comparator 7 uses the data number register 8 as a comparison target with the data number counter 4.

In FIG. 2, prior to the processing, the processor writes in advance an arbitrary number of data in the data number register 8 and an arbitrary data in the data register 6, and starts the processing. When the number of data in the memory block 1 becomes equal to the set value of the data number register 8, the comparator 5 switches the multiplexer 7, the data of the data register 6 is output to the read port, and the subsequent processor immediately executes a predetermined routine.

According to the present embodiment, it is possible to input arbitrary data to the subsequent processor when an arbitrary number of data is accumulated in the buffer memory.

FIG. 3 is a block diagram showing a third embodiment of the present invention. The data number counter 4 and the comparator 5 in the embodiment shown in FIG.
Is provided.

The arbiter 9 is a control signal generation circuit of the multiplexer 7. The initial value is the memory block 1 side, the data register 6 side when the data register W signal is input, and the memory block after the memory read signal is input. Generates a signal for recovery control to the 1 side.

In FIG. 3, while the front-stage processor and the rear-stage processor are processing through the memory block 1, when the front-stage processor writes arbitrary data into the data register 6, the arbiter 9 immediately causes the multiplexer 7 to transfer the data to the data register 6.
The data is read in the memory read process of the next post-processor, and the post-processor interrupts the present process and executes a predetermined routine.

After that, the arbiter 9 switches the multiplexer 7 back to the memory block 1 side, and the latter-stage processor can continue to read and execute the data remaining in the memory 1 after the completion of the predetermined processing.

According to the present embodiment, it is possible to immediately input arbitrary data to the subsequent processor regardless of the current contents of the buffer memory during processing, and to immediately return to the original processing after the completion of predetermined processing. The flexibility of can be increased.

FIG. 4 is a block diagram of a fourth embodiment of the present invention. Instead of the write address pointer 2 and the read address pointer 3 in the embodiment shown in FIG. 3, a write address pointer 10 and a read address pointer, respectively. An address pointer 11 is provided. The write address pointer 10 and the read address pointer 11 are the write address pointer 2 and the read address pointer 11, respectively.
This is a register in which a reset input is added to the read address pointer 3.

In FIG. 4, when the processor of the front stage and the processor of the rear stage are processing through the memory block 1 and the processor of the front stage writes arbitrary data to the data register 6,
The arbiter 9 immediately switches the multiplexer 7 to the data register 6 side, the data is read by the memory reading process of the next post-stage processor, and the post-stage processor interrupts the present process and executes a predetermined routine.

At the same time, the write address pointer 10 and the read address pointer 11 are initialized, and then the arbiter 9
Switches the multiplexer 7 back to the memory block 1 side, and after the processing by the latter stage processor is completed, processing is newly performed according to the data written in the memory by the former stage processor.

According to the present embodiment, it is possible to discard all the current contents of the buffer memory during processing, and immediately input arbitrary data to the processor at the subsequent stage, which makes it possible to enhance processing flexibility.

[0023]

The present invention has the effect of reducing the amount of hardware because it is not necessary to provide an empty processing circuit by adopting the above-described configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

[Explanation of symbols]

 1 Memory Block 2 Write Address Pointer 3 Read Address Pointer 4 Data Number Counter 5 Comparator 6 Data Register 7 Multiplexer 8 Data Number Register 9 Arbiter 10 Write Address Pointer 11 Read Address Pointer

Claims (4)

[Claims] 1. A write port that operates with a memory write signal and a read port that operates with a memory read signal are provided for a set of memories having a data width of M bits and an address of N bits, and writing and reading are performed independently. In a first-in-first-out system buffer memory that can be performed by: an M-bit width data register, and when a certain condition is satisfied, the output of the memory is switched to the data output of the data register, and the read port A buffer memory characterized in that a multiplexer is provided for leading to. 2. A data number counter that is incremented by the memory write signal and decremented by the memory read signal, and a comparator that outputs an empty signal when the data number counter is “0” are provided.
2. The buffer memory according to claim 1, wherein the multiplexer performs the switching in response to the empty signal. 3. A data number counter incremented by the memory write signal and decremented by the memory read signal, a set of N-bit data number registers, and the contents of the data number counter and the data number register are compared. 2. The buffer according to claim 1, further comprising: a data number comparator that outputs a data number matching signal when the data numbers match, and the multiplexer performs the switching when the data number matching signal is output. memory. 4. An arbiter for generating a control signal such that the write signal to the data register is received by the data register and the memory read signal is received by the multiplexer by the memory read signal. Buffer memory according to 1.