JPH0685000A - Semiconductor element mounting structure, tape carrier package using the same, electro-optical device, and electronic printing device - Google Patents
Semiconductor element mounting structure, tape carrier package using the same, electro-optical device, and electronic printing deviceInfo
- Publication number
- JPH0685000A JPH0685000A JP23382992A JP23382992A JPH0685000A JP H0685000 A JPH0685000 A JP H0685000A JP 23382992 A JP23382992 A JP 23382992A JP 23382992 A JP23382992 A JP 23382992A JP H0685000 A JPH0685000 A JP H0685000A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- mounting structure
- output terminal
- element mounting
- pitch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 230000003287 optical effect Effects 0.000 claims 1
- 239000011295 pitch Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 229920001342 Bakelite® Polymers 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 2
- 239000004637 bakelite Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】安価で汎用性の高い半導体素子の実装構造を提
供する。
【構成】回路基板の出力端子３に対して、半導体素子１
を平行あるいは垂直に実装するのではなく、０゜から９
０゜の範囲で傾けて実装することにより、半導体素子の
出力端子９のピッチよりも、回路基板２あるいはそれに
接続された電子素子の端子ピッチが小さい場合に置いて
も、同じ該半導体素子１を用いて電子装置を構成できる
ようにする。
(57) [Abstract] [Purpose] To provide a mounting structure of a semiconductor device which is inexpensive and has high versatility. [Structure] The semiconductor element 1 is connected to the output terminal 3 of the circuit board.
Not mounted in parallel or vertically, but from 0 ° to 9
By mounting the semiconductor element 1 in a tilted manner within a range of 0 °, even if the terminal pitch of the circuit board 2 or the electronic elements connected thereto is smaller than the pitch of the output terminals 9 of the semiconductor element, the same semiconductor element 1 can be provided. Use to configure an electronic device.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子の実装構造
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting structure.
【０００２】[0002]
【従来の技術】従来の半導体素子の実装構造について図
に基づき具体的に説明する。図４は従来の半導体素子の
実装構造を示す平面図である。図４において、回路基板
２上には出力端子３・入力端子４・出力配線パターン５
・入力配線パターン６等が形成され、その所定の位置に
半導体素子１が実装されている。この時、半導体素子１
は、回路配線基板２の出力端子５と半導体素子１の主た
る出力端子辺７のなす小さい方の角が９０゜になるよう
に実装していた。2. Description of the Related Art A conventional mounting structure of a semiconductor device will be specifically described with reference to the drawings. FIG. 4 is a plan view showing a conventional semiconductor element mounting structure. In FIG. 4, an output terminal 3, an input terminal 4, and an output wiring pattern 5 are provided on the circuit board 2.
The input wiring pattern 6 and the like are formed, and the semiconductor element 1 is mounted at a predetermined position thereof. At this time, the semiconductor device 1
Was mounted such that the smaller angle between the output terminal 5 of the circuit wiring board 2 and the main output terminal side 7 of the semiconductor element 1 was 90 °.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら上記従来
技術は、半導体素子１の出力端子９のピッチよりも回路
基板２の出力端子３のピッチ、あるいはその回路基板２
に接続されている電子素子の入力端子のピッチが小さい
場合には、それぞれのピッチを整合させる別の基板を介
して実装する等の方法が必要で、実装構造として非常に
大きいサイズになってしまうという問題を有し、１機種
の半導体素子で対応できる電子素子の範囲は、回路基板
の出力端子あるいは電子素子の入力端子のピッチが、そ
の半導体素子の出力端子ピッチよりも大きい場合に限ら
れていた。そのため回路基板あるいは電子素子の接続端
子のピッチが小さくなると新しい半導体素子を製作する
必要があり製造コストが高くなってしまっていた。However, in the above prior art, the pitch of the output terminals 3 of the circuit board 2 is more than the pitch of the output terminals 9 of the semiconductor element 1, or the circuit board 2 thereof.
If the pitch of the input terminals of the electronic device connected to the device is small, it is necessary to use a method such as mounting via another substrate that matches the pitches, which results in a very large mounting structure. However, the range of electronic devices that can be handled by one type of semiconductor device is limited to the case where the pitch of the output terminals of the circuit board or the input terminals of the electronic device is larger than the output terminal pitch of the semiconductor device. It was Therefore, when the pitch of the connection terminals of the circuit board or the electronic element becomes small, it is necessary to manufacture a new semiconductor element, which increases the manufacturing cost.
【０００４】そこで、本発明の半導体素子の実装構造
は、上記の問題点を解決するために該半導体素子の出力
端子辺と該回路配線基板の主たる出力配線パターンのな
す小さい方の角が０゜を超え９０゜未満になるように半
導体素子を傾けて実装する。Therefore, in the mounting structure of the semiconductor element of the present invention, in order to solve the above problems, the smaller angle between the output terminal side of the semiconductor element and the main output wiring pattern of the circuit wiring board is 0 °. The semiconductor element is mounted by inclining so that the angle exceeds more than 90 degrees and less than 90 degrees.
【０００５】その目的とするところは、安価で汎用性の
高い半導体素子の実装構造の提供することである。An object of the invention is to provide a mounting structure of a semiconductor device which is inexpensive and has high versatility.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体素子の実
装構造は、少なくとも１辺に出力端子を装備し、少なく
ともその主たる出力端子辺と対向する辺に入力端子を装
備する半導体素子を用い、少なくとも出力配線パターン
及び入力配線パターンを装備した回路配線基板の所定の
パターン上に該半導体素子を実装する実装構造におい
て、該半導体素子の出力端子辺と該回路配線基板の主た
る出力端子パターンのなす小さい方の角が０゜を超え９
０゜未満になるように半導体素子を傾けて実装したこと
を特徴とする。A semiconductor element mounting structure of the present invention uses a semiconductor element having at least one side equipped with an output terminal and at least a side opposite to a main output terminal side provided with an input terminal. In a mounting structure in which the semiconductor element is mounted on a predetermined pattern of a circuit wiring board equipped with at least an output wiring pattern and an input wiring pattern, an output terminal side of the semiconductor element and a main output terminal pattern of the circuit wiring board have a small size. The angle on one side exceeds 0 ° and it is 9
It is characterized in that the semiconductor element is mounted so as to be tilted so as to be less than 0 °.
【０００７】[0007]
［実施例１］図１は、本発明の半導体素子の実装構造を
示す主要平面図である。同図において回路配線基板２上
には出力配線パターン５、出力端子パターン７、入力配
線パターン６及び入力端子パターン８が形成されてい
る。その回路配線基板２の所定の位置に半導体素子１が
各配線パターンと位置合わせされて実装されている。半
導体素子１は、ギャングボンディングにより回路基板２
にインナーリードボンディングされている。半導体素子
１には、出力端子辺７に沿って出力端子９が装備され、
同様に入力端子辺８に沿って入力端子１０が装備されて
いる。出力端子及び入力端子のレイアウトは、出力端子
９及び入力端子１０は全てを半導体素子１の１つの辺に
集中させて設けてもいいし複数の辺に設けても良い。ま
た本実施例では、テープキャリアパッケージ（以下ＴＣ
Ｐと言う）での実施例として、回路基板２の材料はポリ
イミドフィルムを用いたが、セラミック・ガラスセラミ
ック等のセラミック材料やエポキシ樹脂・ガラスエポキ
シ樹脂・フェノール・紙フェノール・ベークライト・紙
ベークライト樹脂等の樹脂材料でもよい。また回路配線
についても片面配線・両面配線またはそれ以上の多層配
線でもよい。半導体素子１は、出力端子辺７と回路基板
２の出力端子３が角度θをなすように傾けて実装されて
いる。この時のθの値は、０゜＜θ＜９０゜の範囲で回
路基板２の出力端子３のピッチに半導体素子１の出力端
子９のピッチが整合するように定める。このように半導
体素子１を回路基板２の出力端子３に対して角度θだけ
傾けて実装することにより、回路基板２の出力端子３の
ピッチが半導体素子１の出力端子９のピッチよりも小さ
い値をとる場合でも、専用の半導体素子を新たに設計・
製作する必要がない。従って少ない種類の半導体素子で
多種のＴＣＰ等の半導体装置及び電子光学装置等の電子
装置を設計・製作することができるため製造コストの削
減が可能である。[Embodiment 1] FIG. 1 is a main plan view showing a mounting structure of a semiconductor device of the present invention. In the figure, an output wiring pattern 5, an output terminal pattern 7, an input wiring pattern 6 and an input terminal pattern 8 are formed on the circuit wiring board 2. The semiconductor element 1 is mounted at a predetermined position on the circuit wiring board 2 in alignment with each wiring pattern. The semiconductor element 1 has a circuit board 2 formed by gang bonding.
Inner lead bonded to. The semiconductor element 1 is equipped with an output terminal 9 along the output terminal side 7,
Similarly, an input terminal 10 is provided along the input terminal side 8. Regarding the layout of the output terminals and the input terminals, all of the output terminals 9 and the input terminals 10 may be provided concentrated on one side of the semiconductor element 1 or may be provided on a plurality of sides. Further, in this embodiment, a tape carrier package (hereinafter referred to as TC
As an example in (P), a polyimide film was used as the material of the circuit board 2, but ceramic materials such as ceramics and glass ceramics, epoxy resin, glass epoxy resin, phenol, paper phenol, bakelite, paper bakelite resin, etc. Other resin materials may be used. The circuit wiring may be single-sided wiring, double-sided wiring, or multilayer wiring of more than that. The semiconductor element 1 is mounted so that the output terminal side 7 and the output terminal 3 of the circuit board 2 are tilted so as to form an angle θ. At this time, the value of θ is determined so that the pitch of the output terminals 9 of the semiconductor element 1 matches the pitch of the output terminals 3 of the circuit board 2 within the range of 0 ° <θ <90 °. By mounting the semiconductor element 1 at an angle θ with respect to the output terminal 3 of the circuit board 2 in this manner, the pitch of the output terminals 3 of the circuit board 2 is smaller than the pitch of the output terminals 9 of the semiconductor element 1. Even if you take
No need to make. Therefore, it is possible to design and manufacture various types of semiconductor devices such as TCP and electronic devices such as an electro-optical device with a small number of types of semiconductor elements, so that it is possible to reduce manufacturing costs.
【０００８】［実施例２］図２は、本発明の半導体素子
の実装構造を液晶表示装置（以下ＬＣＤと言う）に用い
た一実施例であり、図２ａはＬＣＤ全体の平面図、図２
ｂは図２ａのＡ−Ａ’断面図である。図２ａ及び図２ｂ
においてＬＣＤ２１の各電極基板には半導体素子を実装
するスペース２４が設けてある。この実装スペース２４
にはＬＣＤの表示電極につながっている、半導体素子１
用の出力配線パターン２５と、同じく半導体素子１用の
入力配線パターン２６が装備されている。これら配線パ
ターン群の所定の位置に半導体素子１が位置決めされフ
ェイスダウン実装により実装されている。また入力配線
パターン２６にはバス基板２３が異方性導電膜（以下Ａ
ＣＦと言う）２８により接続されている。端子ピッチの
構成は、本実施例でも、実施例１と同様に次のような端
子ピッチ構成となっている。[Embodiment 2] FIG. 2 is an embodiment in which the semiconductor element mounting structure of the present invention is used in a liquid crystal display device (hereinafter referred to as LCD). FIG. 2A is a plan view of the entire LCD.
2B is a sectional view taken along the line AA ′ of FIG. 2A. 2a and 2b
In each of the electrode substrates of the LCD 21, a space 24 for mounting a semiconductor element is provided. This mounting space 24
The semiconductor element 1 connected to the display electrode of the LCD
And an input wiring pattern 26 for the semiconductor element 1 are also provided. The semiconductor element 1 is positioned at a predetermined position of these wiring pattern groups and mounted by face-down mounting. In addition, the input wiring pattern 26 has the bus substrate 23 with an anisotropic conductive film (hereinafter referred to as A
28). In this embodiment, the terminal pitch has the following terminal pitch structure as in the first embodiment.
【０００９】ＬＣＤの表示部の表示パターン２７のピッ
チＰＬは、半導体素子１の出力端子９のピッチよりも小
さいピッチとなっているが、半導体素子１を斜めに傾け
て実装することにより、出力端子ピッチの更に小さい半
導体素子を使用することなく電子装置を製作することが
できた。本実施例では、電子表示素子としてＬＣＤを用
いたが、プラズマディスプレイ、ＥＬ（エレクトロルミ
ネッセンス）ディスプレイ、光電管ディスプレイ、ＬＥ
Ｄディスプレイ等でも同様に本実施例の半導体素子の実
装構造を用いることが可能である。The pitch PL of the display pattern 27 of the display section of the LCD is smaller than the pitch of the output terminals 9 of the semiconductor element 1. However, by mounting the semiconductor element 1 at an angle, the output terminals An electronic device could be manufactured without using a semiconductor element having a smaller pitch. Although an LCD is used as an electronic display element in this embodiment, a plasma display, an EL (electroluminescence) display, a phototube display, and an LE are used.
Similarly, a D display or the like can also use the mounting structure of the semiconductor element of this embodiment.
【００１０】［実施例３］図３は、本発明の半導体素子
の実装構造を感熱式電子印字装置（以下電子印字装置と
言う）に用いた一実施例であり、図３ａは電子印字装置
全体の平面図、図３ｂは図３ａのＢ−Ｂ’断面図であ
る。実施例２と同様に本発明の半導体素子の実装構造を
用いている。[Embodiment 3] FIG. 3 is an embodiment in which the mounting structure of the semiconductor element of the present invention is used in a thermosensitive electronic printing device (hereinafter referred to as an electronic printing device). FIG. 3a shows the entire electronic printing device. FIG. 3B is a sectional view taken along line BB ′ of FIG. 3A. Similar to the second embodiment, the semiconductor element mounting structure of the present invention is used.
【００１１】[0011]
【発明の効果】以上説明したように本発明の半導体素子
の実装構造を用いることにより、安価で生産性の高い電
子光学装置や電子印字装置等の電子機器を提供すること
が可能となる。As described above, by using the semiconductor element mounting structure of the present invention, it is possible to provide electronic equipment such as an electro-optical device and an electronic printing device which are inexpensive and have high productivity.
【図１】本発明の半導体素子の実装構造の一実施例を示
す図。FIG. 1 is a diagram showing an embodiment of a semiconductor element mounting structure of the present invention.
【図２】本発明の半導体素子の実装構造の一実施例を示
す図。FIG. 2 is a diagram showing an embodiment of a semiconductor element mounting structure of the present invention.
【図３】本発明の半導体素子の実装構造の一実施例を示
す図。FIG. 3 is a diagram showing an example of a semiconductor element mounting structure of the present invention.
【図４】従来の半導体素子の実装構造の実施例を示す
図。FIG. 4 is a diagram showing an example of a conventional semiconductor element mounting structure.
１．半導体素子 ２．回路基板 ３．回路基板の出力端子 ４．回路基板の入力端子 ５．出力配線パターン ６．入力配線パターン ７．出力端子辺 ８．入力端子辺 ９．半導体素子の出力端子 １０．半導体素子の入力端子 ２１．液晶表示素子 ２２．電子印字素子 ２３．バス基板 ２４．実装スペース ２５．出力配線パターン ２６．入力配線パターン ２７．表示パターン ２８．異方性導電膜（ＡＣＦ） 1. Semiconductor element 2. Circuit board 3. Output terminal of circuit board 4. 4. Circuit board input terminal Output wiring pattern 6. Input wiring pattern 7. Output terminal side 8. Input terminal side 9. Output terminal of semiconductor device 10. Input terminal of semiconductor device 21. Liquid crystal display device 22. Electronic printing element 23. Bus board 24. Mounting space 25. Output wiring pattern 26. Input wiring pattern 27. Display pattern 28. Anisotropic conductive film (ACF)
Claims (4)
くともその主たる出力端子辺と対向する辺に入力端子を
装備する半導体素子を用い、少なくとも出力配線パター
ン及び入力配線パターンを装備した回路配線基板の所定
のパターン上に該半導体素子を実装する実装構造におい
て、該半導体素子の出力端子辺と該回路配線基板の主た
る出力端子パターンのなす小さい方の角が０゜を超え９
０゜未満になるように半導体素子を傾けて実装したこと
を特徴とする半導体素子の実装構造。1. A circuit wiring board equipped with at least one side of an output terminal and a semiconductor element having at least a side opposite to a main output terminal side thereof and an input terminal, and at least provided with an output wiring pattern and an input wiring pattern. In the mounting structure in which the semiconductor element is mounted on the predetermined pattern, the smaller angle between the output terminal side of the semiconductor element and the main output terminal pattern of the circuit wiring board exceeds 0 °.
A semiconductor element mounting structure, wherein the semiconductor element is mounted so as to be tilted to be less than 0 °.
ことを特徴とするテープキャリアパッケージ。2. A tape carrier package comprising the semiconductor element mounting structure according to claim 1.
ことを特徴とする電子光学装置。3. An electron optical device using the semiconductor element mounting structure according to claim 1.
ことを特徴とする電子印字装置4. An electronic printing apparatus using the semiconductor element mounting structure according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23382992A JP3269128B2 (en) | 1992-09-01 | 1992-09-01 | Liquid crystal display device, electronic printing device, and semiconductor element mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23382992A JP3269128B2 (en) | 1992-09-01 | 1992-09-01 | Liquid crystal display device, electronic printing device, and semiconductor element mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0685000A true JPH0685000A (en) | 1994-03-25 |
| JP3269128B2 JP3269128B2 (en) | 2002-03-25 |
Family
ID=16961220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23382992A Expired - Fee Related JP3269128B2 (en) | 1992-09-01 | 1992-09-01 | Liquid crystal display device, electronic printing device, and semiconductor element mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3269128B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100665840B1 (en) * | 2004-12-10 | 2007-01-09 | 삼성전자주식회사 | Daisy-chain memory module and its formation method |
| JP2007129046A (en) * | 2005-11-02 | 2007-05-24 | Murata Mfg Co Ltd | Mounting structure of capacitor array |
| JP2009145439A (en) * | 2007-12-12 | 2009-07-02 | Mitsubishi Electric Corp | Liquid crystal display |
| WO2014024440A1 (en) * | 2012-08-08 | 2014-02-13 | シャープ株式会社 | Display device |
-
1992
- 1992-09-01 JP JP23382992A patent/JP3269128B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100665840B1 (en) * | 2004-12-10 | 2007-01-09 | 삼성전자주식회사 | Daisy-chain memory module and its formation method |
| JP2007129046A (en) * | 2005-11-02 | 2007-05-24 | Murata Mfg Co Ltd | Mounting structure of capacitor array |
| JP2009145439A (en) * | 2007-12-12 | 2009-07-02 | Mitsubishi Electric Corp | Liquid crystal display |
| WO2014024440A1 (en) * | 2012-08-08 | 2014-02-13 | シャープ株式会社 | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3269128B2 (en) | 2002-03-25 |
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