JPH0685067A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0685067A JPH0685067A JP23796192A JP23796192A JPH0685067A JP H0685067 A JPH0685067 A JP H0685067A JP 23796192 A JP23796192 A JP 23796192A JP 23796192 A JP23796192 A JP 23796192A JP H0685067 A JPH0685067 A JP H0685067A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- terminal
- impedance
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 230000001681 protective effect Effects 0.000 abstract 2
- 238000009434 installation Methods 0.000 abstract 1
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 2
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
入出力端子に印加される過電圧や静電気等の外部からの
サージから内部回路を保護するための入出力保護回路を
備えた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an input / output protection circuit for protecting an internal circuit from external surges such as overvoltage and static electricity applied to input / output terminals.
【０００２】[0002]
【従来の技術】図２において、従来の半導体チップ１
は、電源端子ＶＤＤと、この電源端子ＶＤＤと電気的に
接続された電源配線ＶＤＤ１（実線で示した）と、接地
端子Ｇと、この接地端子Ｇに電気的に接続された接地配
線Ｇ１（点線で示した）と、入出力端子Ｐ１，Ｐ２，Ｐ
３とを備えている。このチップ１の入出力部分の電気的
等価回路を、図３に示す。2. Description of the Related Art In FIG. 2, a conventional semiconductor chip 1 is used.
Is a power supply terminal VDD, a power supply wiring VDD1 (indicated by a solid line) electrically connected to the power supply terminal VDD, a ground terminal G, and a ground wiring G1 (dotted line) electrically connected to the ground terminal G. , And input / output terminals P1, P2, P
3 and 3. An electrically equivalent circuit of the input / output portion of the chip 1 is shown in FIG.
【０００３】図３において、入出力端子Ｐ１と接地端子
Ｇとの間には、入出力保護回路ＩＰ１があり、また接地
端子Ｇからの配線インピーダンスＺ１がある。同様に、
入出力端子Ｐ２，Ｐ３には、それぞれ入出力保護回路Ｉ
Ｐ２，ＩＰ３があり、さらに配線インヒーダンスＺ２，
Ｚ３がある。In FIG. 3, an input / output protection circuit IP1 is provided between the input / output terminal P1 and the ground terminal G, and a wiring impedance Z1 from the ground terminal G is provided. Similarly,
The input / output terminals P2 and P3 are connected to the input / output protection circuit I, respectively.
There are P2 and IP3, and wiring inherence Z2
There is Z3.
【０００４】従来の入出力端子に入出力保護回路を具備
した半導体装置において、電源ＴＳＶＤＤと送出端子Ｇ
とは、パッケージの制約から図１に示すように、チップ
１の相対向する位置に配置されている。従って、電源端
子ＶＤＤ及び接地端子Ｇからの距離の大小により、図２
では、配線インピーダンスＺ１，Ｚ２，Ｚ３は次の関係
がある。In a conventional semiconductor device having an input / output terminal with an input / output protection circuit, a power supply TSVDD and a transmission terminal G
Due to the limitation of the package, as shown in FIG. Therefore, depending on the distance from the power supply terminal VDD and the ground terminal G,
Then, the wiring impedances Z1, Z2 and Z3 have the following relationship.
【０００５】Ｚ１＞Ｚ２＞Ｚ３ このように、接地端子Ｇからの位置によりインピーダン
スが異なる。Z1>Z2> Z3 As described above, the impedance varies depending on the position from the ground terminal G.
【０００６】[0006]
【発明が解決しようとする課題】従来の入出力端子に保
護回路を具備した半導体装置では、電源端子ＶＤＤ及び
接地端子Ｇからの距離により、各入出力保護回路に有す
る電源及び接地電位のインピーダンスＺ１，Ｚ２，Ｚ３
が異なり、特に電源端子ＶＤＤ及び接地端子Ｇからの距
離が大きい場合電源及び接地電位のインピーダンス差も
大きく、入出力保護回路機能に支障を来たし、静電気等
の外部ノイズに弱くなり、信頼性上の問題点があった。In the conventional semiconductor device having the protection circuit at the input / output terminal, the impedance Z1 of the power supply and the ground potential in each input / output protection circuit depends on the distance from the power supply terminal VDD and the ground terminal G. , Z2, Z3
, And especially when the distances from the power supply terminal VDD and the ground terminal G are large, the impedance difference between the power supply and the ground potential is large, which hinders the function of the input / output protection circuit and weakens the external noise such as static electricity. There was a problem.
【０００７】本発明の目的は、前記問題点を解決し、外
部ノイズに強く、高信頼性を確保した半導体装置を提供
することにある。An object of the present invention is to solve the above problems and to provide a semiconductor device which is resistant to external noise and ensures high reliability.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置の構
成は、各入出力端子に具備される入出力保護回路に設け
られる電源及び接地電位を有する配線のインピーダンス
を互いに等価となす手段を設けたことを特徴とする。According to the structure of the semiconductor device of the present invention, means for making the impedances of the wirings having the power supply and the ground potential provided in the input / output protection circuit provided at each input / output terminal mutually equivalent are provided. It is characterized by that.
【０００９】[0009]
【実施例】図１は本発明の第１の実施例の半導体装置に
おける半導体チップを示す平面図である。1 is a plan view showing a semiconductor chip in a semiconductor device according to a first embodiment of the present invention.
【００１０】図１において、本実施例は、入出力端子Ｐ
１に付加インピーダンスＺ１１が設けられ、同様に入出
力端子Ｐ２，Ｐ３にそれぞれ付加インピーダンスＺ１
２，Ｚ１３が設けられる。これらの付加インピーダンス
Ｚ１１，Ｚ１２，Ｚ１３は、各部で一定となるように、
付加される。即ち、次に示すように、設定される。In FIG. 1, the present embodiment has an input / output terminal P.
1 is provided with an additional impedance Z11, and similarly, the additional impedance Z1 is respectively provided to the input / output terminals P2 and P3.
2, Z13 are provided. These additional impedances Z11, Z12, and Z13 are constant in each part,
Is added. That is, it is set as shown below.
【００１１】Ｚ１１＝Ｚ−Ｚ１ Ｚ１２＝Ｚ−Ｚ２ Ｚ１３＝Ｚ−Ｚ３ ここで、Ｚは、接地端子Ｇからの最遠端部配線インピー
ダンスである。また、Ｚ１，Ｚ２，Ｚ３は図３で示した
インピーダンスである。Z11 = Z-Z1 Z12 = Z-Z2 Z13 = Z-Z3 where Z is the farthest end wiring impedance from the ground terminal G. Further, Z1, Z2 and Z3 are impedances shown in FIG.
【００１２】このように、入力端子Ｐ１，Ｐ２，Ｐ３に
具備した入力保護回路の接地電位配線が、それぞれ接地
端子ＧからのインピーダンスＺ１，Ｚ２，Ｚ３を有して
いる場合、各接地電位配線にそれぞれインピーダンスＺ
１１，Ｚ１２，Ｚ１３を付加させ、それぞれ入出力端子
Ｐ１，Ｐ２，Ｐ３の接地電位配線インピーダンスをＺと
することによって、達成できる。As described above, when the ground potential wirings of the input protection circuits provided in the input terminals P1, P2, P3 have impedances Z1, Z2, Z3 from the ground terminal G, respectively, Impedance Z respectively
This can be achieved by adding 11, Z12 and Z13 and setting the ground potential wiring impedance of the input / output terminals P1, P2 and P3 to Z, respectively.
【００１３】本第１の実施例では、接地電位配線に注目
したものであり、同様に電源配線に注目して、付加イン
ピーダンスを求めることもできる。また、接地と電源双
方に対しても、付加インピーダンスが求められる。In the first embodiment, attention is paid to the ground potential wiring, and similarly, attention can be paid to the power supply wiring to obtain the additional impedance. Further, additional impedance is required for both the ground and the power supply.
【００１４】[0014]
【発明の効果】以上説明したように、本発明の半導体装
置は、各入出力保護回路の電源及び接地電位配線インピ
ーダンスに電源及び接地端子から最遠端部インピーダン
スとの差分を付加することによって、電源及び接地端子
から最遠端部インピーダンスと等価に構成することで、
各入出力保護回路の機能を安定化し、静電気強度の入出
力端子依存も無くなり、信頼性の向上につながる効果を
有する。As described above, in the semiconductor device of the present invention, by adding the difference between the power supply and ground potential wiring impedance of each input / output protection circuit and the farthest end impedance from the power supply and ground terminal, By configuring the impedance farthest from the power supply and ground terminal,
This has the effect of stabilizing the function of each input / output protection circuit and eliminating the dependence of electrostatic strength on the input / output terminals, leading to improved reliability.
【図１】本発明の第１の実施例の半導体装置におけるチ
ップ内電源及び接地電位配線のレイアウトを示す平面図
である。FIG. 1 is a plan view showing a layout of in-chip power supply and ground potential wirings in a semiconductor device according to a first embodiment of the present invention.
【図２】従来のチップ内電源及び接地電位配線のレイア
ウトを示す平面図である。FIG. 2 is a plan view showing a layout of a conventional on-chip power supply and ground potential wiring.
【図３】図２の入出力保護等価回路を示す回路図であ
る。FIG. 3 is a circuit diagram showing an input / output protection equivalent circuit of FIG.
ＶＤＤ 電源端子 ＶＤＤ１ 電源配線 Ｇ 接地端子 Ｇ１ 接地配線 １ チップ Ｐ１，Ｐ２，Ｐ３ 入出力端子 Ｚ１１，Ｚ１２，Ｚ１３ 付加インピーダンス ＩＰ１，ＩＰ２，ＩＰ３ 入出力保護回路 Ｚ１，Ｚ２，Ｚ３ 接地端子からの配線インピーダン
スVDD power supply terminal VDD1 power supply wiring G grounding terminal G1 grounding wiring 1 chip P1, P2, P3 input / output terminals Z11, Z12, Z13 additional impedance IP1, IP2, IP3 input / output protection circuit Z1, Z2, Z3 wiring impedance from grounding terminal
Claims (2)
路に設けられる電源及び接地電位を有する配線のインピ
ーダンスが前記各入出力端子ごとに相違しないように、
等価となす手段を設けたことを特徴とする半導体装置。1. The impedance of a wiring having a power supply and a ground potential provided in an input / output protection circuit provided in each input / output terminal is different for each input / output terminal.
A semiconductor device provided with means for making it equivalent.
に設けたインピーダンスである請求項１に記載の半導体
装置。2. The semiconductor device according to claim 1, wherein the equivalent means is an impedance provided near each input / output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23796192A JP2884938B2 (en) | 1992-09-07 | 1992-09-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23796192A JP2884938B2 (en) | 1992-09-07 | 1992-09-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0685067A true JPH0685067A (en) | 1994-03-25 |
| JP2884938B2 JP2884938B2 (en) | 1999-04-19 |
Family
ID=17023034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23796192A Expired - Lifetime JP2884938B2 (en) | 1992-09-07 | 1992-09-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2884938B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0826243A4 (en) * | 1995-05-12 | 2000-07-19 | Sarnoff Corp | ELECTROSTATIC DISCHARGE PROTECTION FOR A MACRO-CELL ARRAY |
| JP2009176773A (en) * | 2008-01-21 | 2009-08-06 | Mitsumi Electric Co Ltd | Semiconductor device |
| JP2010028109A (en) * | 2008-06-17 | 2010-02-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
-
1992
- 1992-09-07 JP JP23796192A patent/JP2884938B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0826243A4 (en) * | 1995-05-12 | 2000-07-19 | Sarnoff Corp | ELECTROSTATIC DISCHARGE PROTECTION FOR A MACRO-CELL ARRAY |
| JP2009176773A (en) * | 2008-01-21 | 2009-08-06 | Mitsumi Electric Co Ltd | Semiconductor device |
| JP2010028109A (en) * | 2008-06-17 | 2010-02-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2884938B2 (en) | 1999-04-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990112 |