JPH0686193A - Matrix type display device - Google Patents

Abstract

(57) [Summary] [Structure] The system of the input television signal is discriminated by the system discrimination circuit 105, and a control signal is generated by the control signal generation circuit 106 according to the discrimination result by the discrimination circuit 105 and the input television signal is generated. Time compression processing circuit 103
The time-compressed video signal is subjected to time compression processing, and a DC level signal is inserted by the non-image part processing circuit 107 in a period other than the effective video period of the time-compressed video signal, and the video signal processed in this way is determined according to the determination result. The image is displayed on the image display unit 109 according to the control signal. [Effect] Even when a television signal in which the number of scanning lines, aspect ratio, number of pixels, etc. of the display device is not input is input, it is possible to realize a display screen according to the aspect ratio of the input television signal. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display device such as a liquid crystal display, and more particularly to a multimedia type matrix display device capable of displaying a plurality of types of television signals.

[0002]

2. Description of the Related Art In recent years, high-definition television broadcasting has started and a high-definition television receiver has been developed.
In place of T (cathode ray tube), a high-definition television receiver having a matrix type display device such as a liquid crystal display device, which is light and thin, has been developed.

In such a high-definition television receiver having an aspect ratio of 16: 9, a plurality of conventional television signals having an aspect ratio of 4: 3 (NTSC system, PAL system, EDTV system, etc.) or a plurality of systems such as video signals of a personal computer are used. There is a need for a receiver capable of displaying the television signal of the.

In the CRT high-definition television receiver, a method has already been announced in which a plurality of television signals are displayed by converting the input television signal into a method that conforms to the standard of the television receiver. There is.

However, in a matrix type display device such as a liquid crystal display device, it is considered possible to display television signals of a plurality of systems having different aspect ratios and the like without performing system conversion by its unique scanning method. However, the present situation is that effective proposals have not been made yet.

[0006]

Under the above circumstances, for example, when displaying an input television signal having a different aspect ratio and number of scanning lines, the television signal system itself conforms to the standard of the receiver. A method of converting to a method is used, but such a method requires performing interpolation processing of the number of scanning lines and conversion processing of horizontal and vertical frequencies, which requires a large-scale memory such as a field memory. This requires a large number of processing clocks, which is a large scale in terms of circuit scale and method.

For example, when displaying a signal such as a television having an aspect ratio of 4: 3 on a high-quality wide-aspect matrix display device, the vertical direction of the video display screen is displayed in the full vertical direction of the matrix display device. If so, a non-image portion can be formed on the left and right of the video display screen due to the difference in aspect ratio as shown in FIG. 7, but the video signal for one line of the matrix display device including the non-image portion is not time-compressed. However, if writing is attempted to all the pixels in one line, there is a problem in that the horizontal time of the input television signal exceeds one horizontal period.

[0008]

In order to solve the above-mentioned problems, a matrix type display device of the present invention is a system discriminating means for discriminating a system of an input television signal and a control for generating a control signal according to the discrimination result. Signal generating means, time compression processing means for time-compressing an input television signal in accordance with a discrimination result, and non-picture portion processing for inserting a DC level signal into a period other than an effective video period of the time-compressed video signal. And a video display means for displaying the signal-processed video signal by a control signal according to a determination result.

[0009]

With the above structure, even when a television signal is input which does not match the number of scanning lines, aspect ratio, number of pixels, etc. of a matrix type display device such as a liquid crystal display,
A video display screen corresponding to the aspect ratio of the input television signal can be realized.

Further, as a method thereof, since it has a simple structure which does not perform complicated processing such as system conversion, an increase in circuit scale can be suppressed to a small extent.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the matrix type display device of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of a matrix type display device of the present invention.

In FIG. 1, the television signal input from the input terminal 101 is sent to the input signal processing circuit 102. The input signal processing circuit 102 performs filter processing for removing unnecessary noise and the like contained in the input television signal, gain adjustment necessary for signal processing in the subsequent stage, and clamp processing. The video signal subjected to these processes is sent to the time compression processing circuit 103, the sync separation circuit 104, and the system discrimination circuit 105, respectively.

Then, the sync separation circuit 104 detects the horizontal sync signal and the vertical sync signal in the input television signal. The detected horizontal synchronizing signal and vertical synchronizing signal are sent to the input signal processing circuit 102 and the system discriminating circuit 105. In the input signal processing circuit 102, these two types of synchronization signals are used for forming a clamp pulse, for example.

On the other hand, the system discriminating circuit 105 discriminates the system of the input television signal by examining the characteristics of the system of each television signal from the synchronizing signal and the video signal supplied from the input signal processing circuit 102. . The determination result is the control signal generation circuit 10 of the next stage.
6 to generate a clock for performing signal processing in this system, a control signal for signal processing and image display, and the like.

Then, the time compression processing circuit 103 time-compresses the video signal processed by the input signal processing circuit 102. The time compression processing here is performed in units of one horizontal period of each input television signal, and the horizontal frequency in video display is not changed. The state of this time compression processing is shown in FIG. 2 which is a signal waveform diagram after the time compression processing and after the non-image area processing.

In the case of FIG. 2, as an example, 1/2 time compression is performed with the horizontal synchronizing signal of the input television signal as a reference. In the case of this example, the period from the output of the time-compressed video signal to the arrival of the next horizontal synchronizing signal is not particularly defined as a video signal. However, in the subsequent non-picture section processing circuit 107, there is no problem because the parts other than the effective video signal section in FIG. 2 are replaced with the DC level for displaying the non-picture section.

As a result, the horizontal frequency of the finally time-compressed video signal is not different from that of the input television signal. Here, the compression ratio for the input television signal is set to 1/2, but this is not particularly limited. However, it is desirable that the number be divided by an integer because it can be easily obtained in the circuit configuration.

As described above, in the non-picture area processing circuit 107, processing for inserting a DC level signal in order to display the non-picture area in a portion other than the effective video signal area is performed. Then, the video signal processed by the non-image part is subjected to a filter process in the display signal processing circuit 108 or a signal process for display according to the type of display device, for example, one horizontal period or one vertical period in the liquid crystal display. Processing for AC drive that inverts the polarity of the video signal supplied to the pixel in units, performed on the video signal supplied according to the input / output characteristics that represent the relationship between the potential supplied to the pixel and the brightness at the time of display Video signal correction processing and the like are performed.

In the video display section 109, the input television signal is supplied by the video signal from the display signal processing circuit 108 in the preceding stage and the control signal according to the system of the input television signal from the control signal generation circuit 106. The video display screen according to the method is reproduced.

The overall signal processing flow of the matrix type display device of the present invention has been described above. A block diagram further embodied for facilitating understanding of the matrix type display device of the present invention is shown, and a matrix is shown. An embodiment of the matrix type display device of the present invention will be described in the form of embodying the type display device and the input television signal.

First, as the image display unit 109, for example, the aspect ratio is 16: 9, the number of pixels is 1000 vertical × 1200 horizontal.
We assume a liquid crystal panel that conforms to the Hi-Vision standard.
In this liquid crystal panel, when a high-definition signal (1125 scanning lines, aspect ratio 16: 9, interlace ratio 2: 1, field frequency 60 Hz) is supplied as an input television signal, the high-definition image is displayed on the entire screen of the liquid crystal panel. Can display video.

The structure of the image display unit 109 is shown in FIG.
As shown in. To briefly explain this, a video signal subjected to the signal processing up to the preceding stage is input to the input terminal 301. A clock corresponding to the input television signal system and the number of pixels of the liquid crystal panel is input to the input terminal 302. This clock shift register 303
Operates and latches the potential of the video signal for one pixel in the latch 304 every one clock. The H reset pulse of the shift register is input to the input terminal 314 in order to determine the start position of the image display in the horizontal period of the image signal. The H reset pulse causes the shift register to start latching the potential of the video signal with respect to the leftmost pixel of the video display screen.

The input terminal 305 has 1200 lines for one line.
After the latching of the potential of the video signal for each pixel is completed, a transfer pulse is input, and the potential of the video signal for 1200 pixels for one line of the liquid crystal panel is transferred from the latch 304 to the signal electrode driving circuit 306 at one time. Then, after further buffering, the potential of the video signal is supplied to each pixel electrode line 307. On the other hand, a scan pulse is supplied to the input terminal 308 every horizontal period.

Then, the scan electrode selection circuit 309 selects a scan electrode for displaying an image. Scan electrode driving circuit 310
Supplies to the scanning electrode line 311 a signal for writing the potential of the video signal supplied to the pixel electrode line 307 to all the pixels in the selected scanning electrode.
A TFT is provided at the intersection of the pixel electrode line 307 and the scanning electrode line 311.
The liquid crystal is connected through switch elements such as, and the potential of the video signal is supplied to each selected pixel for display. By performing this for all the scanning electrodes, a television image for one field is displayed on the display panel 312.

A V reset pulse is supplied to the input terminal 313 every vertical period to signal the start of one vertical period.
By this V reset pulse, the scan electrode selection circuit 309
Selects sequentially from the scan electrodes at the upper end of the image display screen.
A television image is displayed by repeating the above operation.

First, signal processing when a high-definition signal is supplied to this system will be described.

In FIG. 1, the video signal subjected to the signal processing by the input signal processing circuit 102 is sent to the time compression processing circuit 103 at the next stage. FIG. 4 shows the time compression processing circuit 103.
3 is a configuration example of the non-image part processing circuit 107. A video signal is input to the input terminal 401 of FIG.
Control signals corresponding to the high-definition signals are supplied to control signals 410 to 410 from the control signal generation circuit 106 in FIG. The AD converter 411 AD-converts the input video signal by the write clock from the input terminal 406.

The frequency of the write clock is determined by the number of pixels of the matrix type display device, the horizontal frequency of the input television signal, the aspect ratio, etc., and one line of the liquid crystal panel of the embodiment of the present invention using the high definition signal as an input. Since the number of pixels is 1,200, it is about 50 MHz.

After that, the digitized video signals are supplied to the line memories 412 and 413. These line memories read and write the video data for each horizontal period, and one of the line memories reads the video data. When it is in the state, the other is switched so that it is in the write state. This is to prevent the write of the line memory and the overtaking of the read address in the time compression processing.

Therefore, the input terminals 402, 404, 407,
The timing of each reset pulse of 408 and the memory select pulse of the input terminal 405 is as shown in FIG. 5, for example. The line memory used here has at least the data capacity of one line of the television signal in the system having the largest number of pixels in one horizontal period among the inputted television signals, and its address is a reset pulse. Return to address 0 only by. The write address and read address operate independently of each other.

A read clock is input to the input terminal 403, but when a high-definition signal is input, it is not necessary to perform time compression processing. Therefore, the video data is read at a clock of about 50 MHz which is the same frequency as the write clock. To do. The data selector 414 uses the memory select pulse from the input terminal 405 to select each line memory 41.
Of 2, 413, the video data from the line memory in the read state is selected every horizontal period and sent to the non-image section processing circuit 107 in the next stage. In the non-picture area processing circuit 107, the data selector 415 is for inserting non-picture areas on the left and right of the video display screen when displaying video signals having different aspect ratios.

The input terminal 409 is supplied with DC level data for displaying a non-picture portion, and the input terminal 410 is supplied with a video / non-picture portion select pulse for determining a period for inserting the non-picture portion. However, when the high-definition signal is input, it is not necessary to insert the non-image part. And DA converter 4
16 performs DA conversion with the same clock as the line memory read clock, and outputs from the output terminal 417.

The video signal is a display signal processing circuit 1 shown in FIG.
At 08, processing such as AC conversion of a video signal for AC driving of the liquid crystal panel is processed and supplied to the video display unit 109. When the high-definition signal is input, the clock of the input terminal 302 in FIG.
The H reset pulse of 4 is supplied at the time when the effective video signal section starts.

In the scan electrode selection circuit 309, since the number of lines of the liquid crystal panel is 1000, for example, the conventional interlaced scan in which the scan electrodes are skipped every other line or selected, or the same signal is supplied to two lines of the scan electrodes. At the same time, writing is performed, and in the next field, video display is performed by a scanning method by selection such that the combination of the two lines is shifted by one line.

Next, signal processing when a conventional NTSC signal is input will be described.

The NTSC signal is a television signal having 525 scanning lines, an aspect ratio of 4: 3, an interlace ratio of 2: 1 and a field frequency of 59.94 Hz.

The video signal signal-processed by the input signal processing circuit 102 is sent to the time compression processing circuit 103.
In the embodiment of the present invention, as a method of displaying an NTSC signal with an aspect ratio of 4: 3 on a liquid crystal panel with an aspect ratio of 16: 9, the vertical direction of the video display screen is displayed in the full vertical direction of the liquid crystal panel. FIG. 7 shows how the image is displayed in that case.

When the NTSC signal is input, the write clock in FIG. 4 is about 17 MHz calculated from the number of pixels in one line and the aspect ratio. However, in reality NT
Since the video band of the SC signal is narrower than that of the high-definition signal, the same video signal may be displayed for two pixels on the scanning electrodes of the liquid crystal panel. In this case, the write clock is halved to about 8.5 MHz. Become. Here, we decided to sample the video data for each pixel,
Hz.

The input terminal 403 is supplied with a read clock having a frequency capable of displaying all video data of 1200 pixels on one line of the liquid crystal panel including a non-picture portion within one horizontal period of the NTSC signal. That is 17 MH
When the video data of the effective video signal section is read without performing time compression by the z read clock and 1200 pixels of one line are displayed with a 17 MHz clock by adding a non-image section, it takes about 70 μsec. The horizontal period is about 63.5 μsec, which is impossible in terms of time.

Because of the simplicity of the circuit, the embodiment of the present invention uses a read clock having a frequency of about 34 MHz, which is twice the frequency of the write clock. The video signal is time-compressed to ½ by reading with this read clock.

In the non-image section processing circuit 107 in the next stage,
When the vertical direction of a video display screen with an aspect ratio of 4: 3 is displayed in the full vertical direction of a liquid crystal panel with an aspect ratio of 16: 9, there is no image corresponding to the left and right margins of the video display screen caused by the difference in aspect ratio. To display the part, 1 /
The DC level data is inserted by the data selector 415 in the period other than the effective video signal portion of the video signal time-compressed to 2.

Then, the video data is DA converted by the DA converter 416 by the same clock as the read clock of the line memory. Thereafter, the video signal is subjected to signal processing such as AC conversion of the video signal in the liquid crystal display in the display signal processing circuit 108, and then sent to the video display unit 109.

About 34 MHz is applied to the input terminal 302 in FIG.
Clock is supplied. Further, an H reset pulse is input to the input terminal 314 to determine which position in the horizontal direction in the liquid crystal panel having an aspect ratio of 16: 9, including the non-image area, to display an NTSC signal having an aspect ratio of 4: 3. It The transfer pulse is input to the input terminal 305 after the potential of the video signal for 1200 pixels is latched. The timing of these signals is as shown in FIG.

In the scan electrode selection circuit 309, the number of scanning lines of the NTSC signal is 525, the interlace ratio is 2: 1 and the number of lines of the liquid crystal panel of one embodiment of the present invention is 1000. The same signal is simultaneously written in two lines of the scan electrodes, and the next two lines are interlaced scans in which the two lines are selected in an interlaced manner, or four lines of the scan electrodes are selected.
The same signal is simultaneously written to the lines, and in the next field, the image display is performed by a scanning method by selection such that the combination of the four lines is shifted by two lines.

Other input television signals, such as E
DTV and various personal computer signals can also be displayed by the same method.

Needless to say, the present invention is not limited to the specific numerical values, circuit configurations, display devices and the like shown in the embodiments.

[0048]

Since the matrix type display device such as the liquid crystal display device of the present invention has the above-mentioned structure, a television signal in which the number of scanning lines, aspect ratio, number of pixels, etc. of the display device is not suitable. Even when input, a display screen according to the aspect ratio of the input television signal can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a matrix type display device of the present invention.

FIG. 2 is a signal waveform diagram after the time compression processing and the non-image portion processing of the time compression processing circuit of FIG.

3 is a block diagram showing a main part of the video display unit of FIG. 1. FIG.

4 is a block diagram showing essential parts of a time compression processing circuit and a non-image area processing circuit of FIG. 1. FIG.

5 is a timing diagram of write reset, read reset, and memory select pulse of the line memory of FIG.

6 is a timing diagram of signals in the video display unit of FIG.

FIG. 7 is an explanatory diagram of a display when the display device and the television signal have different aspect ratios.

[Explanation of symbols]

 102 Input Signal Processing Circuit 103 Time Compression Processing Circuit 104 Sync Separation Circuit 105 Method Discrimination Circuit 106 Control Signal Generation Circuit 107 Non-Image Area Processing Circuit 108 Display Signal Processing Circuit 109 Video Display Section 303 Shift Register 304 Latch 306 Signal Electrode Driving Circuit 307 Pixel electrode line 309 Scan electrode selection circuit 310 Scan electrode drive circuit 311 Scan electrode line 312 Display panel 411 AD converter 412, 413 Line memory 414, 415 Data selector 416 DA converter

Claims (1)

[Claims] 1. A television signal of a specific standard,
In a matrix type display device such as a liquid crystal display that can be displayed and has a suitable number of scanning lines, aspect ratio, number of pixels, etc., the system discrimination means for discriminating the system of the input television signal and the discrimination result by the system discrimination means Control signal generating means for generating a corresponding control signal, time compression processing means for time-compressing the input television signal according to the discrimination result by the system discrimination means, and video signal time-compressed by the time compression processing means A non-image part processing means for inserting a DC level signal in a period other than the effective video period, and a video display means for displaying the signal-processed video signal by a control signal according to a determination result. Matrix display device.