JPH10276411A - Interlace / progressive scan conversion circuit - Google Patents

Abstract

(57) Abstract: An I / P (interlaced / progressive) scan conversion circuit can be converted for P scan without deteriorating image quality, and the circuit scale can be reduced. SOLUTION: A decoder 10 converts an NTSC signal for I scanning into digital R, G, B signals and separates a synchronizing signal, and controls reading / writing of a line memory 14 by setting the frequency of a read clock to twice the write clock. And a control circuit 16 for outputting a line switching signal for P scanning.
A zero-level data interpolation circuit 20 for switching video data and zero-level data read from the line memory 14 for each line and outputting them as R, G, and B signals for P-scanning; A synchronizing signal generation circuit 18 for converting one field data of I-scan into one frame data of P-scan as it is, and scanning a scan line not scanned by I-scan with zero level data of P-scan The image is replaced with a line to supplement the missing pixel data and displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an image by progressive scanning (non-interlaced scanning) such as PDP (plasma display panel) or LCD (liquid crystal display panel).
The present invention relates to an interlace / progressive scan conversion circuit used to display an image of an analog video signal for interlace scan (interlaced scan) such as an SC signal and a MUSE signal. NTSC signal is general-purpose NTSC
(National Television System
emCommittee), which indicates a composite color television signal, and the MUSE signal is a MUSE (Multiple Multiple) signal.
Sub-Nyquist Sampling Encoding) signal for HDTV.

[0002]

2. Description of the Related Art In recent years, displays using an address / display separation type driving method (ADS subfield driving method) or a matrix driving method, such as PDPs and LCDs, have been developed. These PDPs and LCDs are used for progressive scanning. In many cases, it is assumed that the digital video signal is directly driven. An interlace / progressive scan conversion circuit used for displaying an image of an analog video signal for interlace scan on a display device such as a PDP or an LCD generally doubles the number of pixels in the vertical direction per field. , It is necessary to double the sampling frequency.

A conventional interlaced / progressive scan conversion circuit, as shown in FIG.
In order to double the pixel density, the video data is written to the line memory for each scanning line, and is read twice at twice the speed of the write clock, thereby eliminating the deterioration of the pixel density.
As shown in FIG. 4, a method of generating and displaying one piece of progressive scan frame data from video data of two consecutive fields has been adopted.

[0004]

However, in the conventional example shown in FIG. 3, since one line of video data is scanned twice and displayed, scanning lines which should be displayed by one scanning line, Are displayed as video data of two scanning lines,.
There is a problem that the thickness of one line is equivalent to two lines and the image quality is worse than in the case of interlaced scanning. FIG.
In the figure, a solid line indicates a scan line of the current field, and a dotted line indicates a scan line of the next field.

[0005] Further, in the conventional example shown in FIG.
The video data of the + 1st two fields is converted to the Mth 1
Since a field memory is required for synthesizing video data of one frame, there is a problem that the circuit scale is increased. In addition, since the video data of two fields having a time difference is synthesized, it is not possible to cope with a moving image. In order to cope with the moving image, a circuit for motion adaptation processing is required, and the circuit size is further increased. was there. In FIG. 4, indicated by a solid line,
Represents the scan line of the N-th current field and is indicated by a dashed line, represents the scan line of the (N + 1) -th current field, and the dotted line represents the scan line of the next field in each field.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and can convert a digital video signal for progressive scanning without deteriorating the image quality as compared with the case of interlaced scanning, and eliminates the need for a field memory. An object of the present invention is to provide an interlaced / progressive scan conversion circuit capable of reducing the circuit scale.

[0007]

SUMMARY OF THE INVENTION The present invention provides an interlace / progressive scan conversion circuit for converting an analog video signal for interlaced scanning into a digital video signal for progressive scanning. Digital video signals (for example, R, G, B
Signal) and a decoder for separating a synchronizing signal from an analog video signal for interlaced scanning, a line memory for storing one line of a digital video signal output from the decoder, and writing a frequency of a read clock. A control circuit for controlling the reading and writing of the digital video signal in the line memory at twice the frequency of the clock, and outputting a line switching signal for progressive scanning, and reading from the line memory based on the line switching signal of the control circuit. A zero-level data interpolation circuit that switches between a digital video signal and pre-generated zero-level data line by line and outputs the digital video signal for progressive scanning, and a progressive-scanning digital signal based on a synchronization signal output from a decoder. Generate sync signal And it is characterized in that formed by and a synchronizing signal generating circuit that.

An analog video signal for interlaced scanning is converted into a digital video signal (for example, R,
G, B signals) and then stored in a line memory. Since the frequency of the clock for reading the digital video signal from the line memory is controlled to twice the frequency of the write clock by the control circuit, this frequency conversion converts the digital video signal into video data that matches the timing of progressive scanning. The zero-level data interpolation circuit
On the basis of the progressive scan line switching signal output from the control circuit, the video data read from the line memory and the previously generated zero level data are switched for each line and output as a progressive scan digital video signal. The synchronization signal generation circuit generates and outputs a synchronization signal for progressive scanning based on the synchronization signal output from the decoder.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. In FIG. 1, reference numeral 10 denotes a decoder.
The decoder 10 converts an analog NTSC signal input to the input terminal 12 into digital R, G, B signals, and separates and outputs synchronization signals (horizontal and vertical synchronization signals) from the input NTSC signal. Is configured. The decoder 10 is, for example, an analog NT
An A / D (analog / digital) conversion circuit for converting an SC signal into a digital video signal, a matrix circuit for converting a luminance signal (Y) and a color difference signal (BY, RY) into R, B, G signals; It is mainly composed of a sync separation circuit and the like.

A line memory 14 for storing one line of data is connected to the output side of the R, G, B signals of the decoder 10, and a control circuit 16 and a control circuit 16 are connected to the output side of the synchronization signal of the decoder 10. A synchronization signal generation circuit 18 is coupled. The control circuit 16 generates a read / write control signal (including a write clock WCK and a read clock RCK) based on the synchronization signal output from the decoder 10, outputs the signal to the line memory 14, and outputs a progressive scan signal. It is configured to generate a line switching signal and output it to a zero level data interpolation circuit 20 described later. The frequency of the read clock RCK output from the control circuit 16 to the line memory 14 is set to twice the frequency of the write clock WCK.

The synchronizing signal generation circuit 18 is configured to generate a synchronizing signal for progressive scanning based on the synchronizing signal from the decoder 10 and output the synchronizing signal to a synchronizing signal output terminal 22. The zero-level data interpolation circuit 20 switches between video data read from the line memory 14 and internally generated zero-level data on a line-by-line basis based on a line switching signal output from the control circuit 16. The digital video signal is output to a video signal output terminal 24 as a digital video signal for progressive scanning. The zero level data is set to, for example, data representing a black level on which a color burst of an NTSC signal (composite color television signal) is superimposed.

Next, the operation of FIG. 1 will be described with reference to FIG. For convenience of explanation, it is assumed that one field is composed of three scanning lines and one frame is composed of six scanning lines. Analog NTSC input to input terminal 12
The signals are converted by the decoder 10 into digital R, G, B
The signal is converted to a signal, written to the line memory 14, and read. Since the frequency of the clock RCK for reading the R, G, and B signals from the line memory 14 is twice the frequency of the write clock WCK, the R, G,
The B signal has been converted to video data that matches the timing of progressive scanning.

The zero-level data interpolation circuit 20 outputs R, R read from the line memory 14 based on a line switch signal for progressive scanning output from the control circuit 16.
The G and B video data and the internally generated zero level data are switched for each line to produce a digital video signal for progressive scanning, which is output to the video signal output terminal 24. The synchronization signal generation circuit 18 generates a synchronization signal for progressive scanning based on the synchronization signal from the decoder 10 and outputs the signal to the synchronization signal output terminal 22.

For this reason, a display device for displaying an image by progressive scanning, such as a PDP or an LCD, which is connected to the subsequent stage of the video signal output terminal 24 and the synchronizing signal output terminal 22, is as shown in FIGS. 2 (a) and 2 (b). In addition, one field data of the interlaced scan is directly converted into one frame data of the progressive scan and displayed, and a scan line which is not scanned by the interlace scan is changed to a scan line of zero level data of the progressive scan (zero). Level scanning line) to display the insufficient pixel data.

That is, as shown on the left side of FIG. 2A, each of the video data of the scanning lines of N fields to be displayed by the interlaced scanning NTSC signal is shown on the right side of FIG. As shown in FIG. 5, N fields, which are displayed as video data of scanning lines of M frames to be displayed by R, G, B signals for progressive scanning, and as shown on the left side of FIG. The unscanned scan line after one line of each of the scan lines is a zero level scan line (1) after one line of each of the M frame scan lines, as shown on the right side of FIG. ), (2), and (3). That is, zero level scanning lines (1), (2),
(3) is displayed as video data of zero level (for example, black level).

Also, as shown on the left side of FIG. 2B, N + to be displayed by an NTSC signal for interlaced scanning is used.
As shown on the right side of FIG. 3B, each of the video data of the scanning line of one field is the video of the scanning line of the M + 1 frame to be displayed by the R, G, and B signals for progressive scanning. The unscanned scan lines which are displayed as data and are one line before each of the N + 1 field scan lines as shown on the left side of FIG. , M + 1
The scan lines of the frame are displayed in place of the zero-level scan lines (4), (5), and (6) one line before. That is, the zero level scanning line (4),
(5) and (6) are displayed as video data of zero level (for example, black level).

In the above embodiment, the case where the analog video signal for interlaced scanning is an NTSC signal has been described. However, the present invention is not limited to this. For example, the analog video signal for interlaced scanning is a MUSE signal. It can also be used in the case of

In the above embodiment, the decoder uses the A / D
A conversion circuit, a matrix circuit, a synchronization separation circuit, and the like are mainly used to convert an analog video signal for interlaced scanning into digital R, G, and B signals, and to separate a synchronization signal from the analog video signal for interlaced scanning. Although the present invention has been described, the present invention is not limited to this, and may be any device that converts an analog video signal for interlaced scanning into a digital video signal and separates a synchronization signal from the analog video signal for interlaced scanning.

[0019]

The interlace / progressive scan conversion circuit according to the present invention converts an analog video signal for interlace scan into digital R, G, B signals and separates a synchronizing signal, and a digital R, G, B signal.
A line memory for storing one line of the G and B signals and having a read clock frequency twice as high as the write clock; video data and zero level data read from the line memory based on a line switching signal for progressive scanning; And a sync signal generating circuit for generating a progressive scan synchronizing signal based on a synchronizing signal from a decoder. Then, one field data of the interlaced scanning is directly converted into one frame data of the progressive scanning, and a scanning line not scanned in the interlaced scanning is changed to a scanning line of zero level data of the progressive scanning (zero level scanning line). ) And replace the missing pixel data As shown in the figure, the analog video signal for interlaced scanning can be converted into a digital video signal for progressive scanning without deteriorating the image quality, and a large-capacity memory such as a field memory is not required. The scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an interlace / progressive scan conversion circuit according to the present invention.

FIG. 2 is a circuit diagram of FIG. 1 showing one field data of interlaced scanning as it is for one field of progressive scanning.
FIG. 7A shows a case where the image data is converted into one frame data, and a scan line which is not scanned in the interlaced scan is replaced with a scan line of zero level data (zero level scan line) in the progressive scan and displayed. When the Nth field data of the race scan is converted into the Mth frame data of the progressive scan and displayed,
(B) is an explanatory diagram showing a case where the (N + 1) th field data of the interlaced scanning is converted into the (M + 1) th frame data of the progressive scanning and displayed.

FIG. 3 is an explanatory diagram of a conventional example, showing a case where video data of one scanning line of interlaced scanning is twice converted to video data of two scanning lines of progressive scanning and displayed. FIG.

FIG. 4 is an explanatory diagram of another conventional example, and illustrates 2nd interlaced scanning.
FIG. 7 is an explanatory diagram showing a case where field data of one sheet is combined with one frame data of progressive scanning and displayed.

[Explanation of symbols]

10: decoder, 12: input terminal, 14: line memory, 16: control circuit, 18: synchronization signal generation circuit,
20: Zero level data interpolation circuit, 22: Synchronous signal output terminal, 24: Video signal output terminal, ... Scanning line, (1) to (6) ... Zero level scanning line.

Claims (4)

[Claims] An interlace / progressive scan conversion circuit for converting an analog video signal for interlace scan into a digital video signal for progressive scan,
A decoder for converting the analog video signal for interlaced scanning into a digital video signal and separating a synchronizing signal from the analog video signal for interlaced scanning; and a digital video signal output from the decoder.
A line memory for storing lines, and a control circuit for controlling read / write of a digital video signal in the line memory by setting the frequency of a read clock to twice the frequency of a write clock, and outputting a line switching signal for progressive scanning A zero level for switching between a digital video signal read out from the line memory and a previously generated zero level data line by line based on a line switching signal of the control circuit and outputting as a digital video signal for progressive scanning. An interlace / progressive scan conversion circuit, comprising: a data interpolation circuit; and a synchronization signal generation circuit that generates a synchronization signal for progressive scanning based on a synchronization signal output from the decoder. 2. A decoder converts an analog video signal for interlaced scanning into digital R, G, B signals and separates a synchronizing signal from the analog video signal for interlaced scanning. 2. The interlace / progressive scan conversion circuit according to claim 1, wherein one line of digital R, G, B signals output from said decoder is stored. 3. The interlace / progressive scan conversion circuit according to claim 1, wherein the analog video signal for interlace scanning is an NTSC signal. 4. The interlace / progressive scan conversion circuit according to claim 1, wherein the analog video signal for interlace scan is a MUSE signal.