JPH0687191B2 - Vertical cursor data generator for raster scan display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a raster scan display device capable of displaying a crosshair cursor on a display screen, and more particularly to a vertical cursor data generation device thereof.

[Prior Art] In a raster scan display device, particularly a graphic display device, as shown in FIG. 4, a horizontal cursor is used to specify a desired coordinate point on the display screen 10 or a part of a display figure. Crosshair cursors 18 consisting of 12 and vertical cursors 14 are often used. A block diagram of a relatively low pixel rate pixel data generator including a conventional crosshair cursor generator is shown in FIG. The resolution of a bitmap memory (BMM) 55 having pixel data corresponding to the display screen 10 on a one-to-one basis is, for example, 640.
Assuming x480, BMM55 is 10 via bus 27 and bus 46 respectively.
It is accessed by a bit horizontal (X) counter 22 and a 9-bit vertical (Y) counter 42. The bus 27 is an upper part of the bus 26, and the BMM 55 outputs the same number of pixel data to 56 in parallel every time the X counter 22 receives a predetermined number of pixel clocks. This parallel output data is taken into the shift register (S / R) 60 according to the load signal from the predetermined bit output 23 of the X counter 22. The shift register 60 outputs this pixel data to the output line according to the pixel clock.
Shift output to 61 in series. X counter 22 is reset to 0 at count 639 in this example. On the other hand, Y counter 4
2 receives a horizontal synchronizing pulse (H-sync) at its clock input terminal and changes the address data of the bus 46 for each scanning line of the raster. The Y counter 42 is reset to 0 by a count 479. Thus, the output line 61 of the shift register 60
Pixel data corresponding to the image of the BMM 55 is sequentially output to.

In FIG. 5, the cursor generator is a vertical cursor generation circuit 21 including an X counter 22, an X comparator 28, and a latch circuit 30.
And a vertical cursor generation circuit 41 including a Y counter 42, a Y comparator 48, and a latch circuit 50. The latch circuit 30 and the latch circuit 50 have a processor (CPU:
(Not shown), the X coordinate of the Y cursor 14 and the Y coordinate of the X cursor 12 are loaded via the buses 34 and 35, respectively. The X coordinate data of the latch circuit 30 is compared with the output data of the X counter 22 which advances in every pixel clock by the X comparator 28, and when both data match, that is, the pixel scanning is Y.
When the cursor 14 is reached, the X comparator 28 produces an output on signal line 29. This signal is finally Y on the display screen 10.
One pixel on the cursor 14 is activated (luminance modulation or color modulation). Similarly, the Y coordinate data of the latch circuit 50 is compared with the output data of the Y counter 42, which is advancing for each scanning line, by the Y comparator 48, and when the both data match, that is, the pixel scanning is performed on the X cursor 12. When reached, the Y comparator 48 produces a signal on its output line 49. This signal is the X cursor 12
Energize the pixel continuously for one scan line corresponding to.
Both outputs 29, 49 of the X-comparator 28 and the Y-comparator 48 are combined in a gate 58, such as an OR gate, and the output 59 of this gate 58 is further shifted by a gate 62, such as an ejector (EOR) gate. It is combined with the pixel data from register 60.
The output pixel data of gate 62 drives a raster scan display means (not shown) such as a cathode ray tube. In this way, the crosshair cursor 18 can be displayed on the display screen 10 at an arbitrary position so as to be superimposed on the display image.

However, in a higher pixel rate raster scan display device having a resolution of 1280x1024, for example, the operation speed of the device cannot keep up with the cursor generation method such as the vertical cursor data generation circuit 21 of FIG.

In order to solve this problem, a vertical cursor data generation circuit 65 as shown in FIG. 7 has been conventionally used. In this circuit, the 11-bit X coordinate data of the Y cursor is loaded from the processor to the latch circuit 64, and the upper 8 bits of the output data of the latch circuit 64 are compared with the upper 8 bits of the 11-bit X counter 72 by the comparator 78. It This does not detect whether the pixel scan has reached the X coordinate of the Y cursor 14, but rather divides the display screen into a plurality of vertical blocks 16 as shown in FIG. This means that it has detected whether or not the vertical block 16 to which is belongs has been reached. This eliminates the problem of the operating speed of the comparator 78. Lower 3 of output data of latch circuit 64
The bits are applied to the parallel data input of a down counter 68 via a level converter 63 that converts the signal level from TTL level to ECL level. When the data of the X counter 72 matches the data from the latch circuit 64, the output of the comparator 78 is input to the clock input terminal of the D flip-flop 73 via the level converter 69. Since the D input terminal of the flip-flop 73 is grounded, it outputs a low signal to its Q output terminal. This low output is connected to the D input terminal of the D flip-flop 74, and is flip-floped at the next pixel clock.
74 Q output goes low. The Q output of the flip-flop 74 is applied to the load input terminal LD of the down counter 68 and the clear input terminal CLR of the flip-flop 75, and the down counter 68
The counting operation is enabled and the urea state of the flip-flop 75 is released. While the high Q output is given to the LD input terminal of the down counter 68, the down counter
The lower 3 bits of the X coordinate are loaded into the 68 via the level converter 63 according to the pixel clock. LD
When a low signal is applied to the input terminal, the down counter 68 starts down counting from the next pixel clock and the content becomes 0.
Then, a high signal is output from the borrow output terminal B to the D input terminal of the flip-flop 75. The flip-flop 75 generates a high signal from the Q output terminal to the gate 58 (FIG. 5: ECL circuit) at the next pixel clock. Since this high signal is also applied to the preset input terminal PR of the flip-flop 73, the Q output of the flip-flop 73 becomes high, and the Q output of the flip-flop 74 also returns to high at the next pixel clock, and the down counter 68 has a new output. Load operation is enabled and the flip-flop 75 is cleared. This causes the flip-flop 75 to output a high signal for one pixel, activating one pixel on the Y cursor 14. According to this circuit, the flip-flops 74 and 75 cause a delay of two pixel clocks, so that it is necessary to give a similar delay to the pixel data side of FIG. The number of vertical blocks 16 in FIG. 6 is eight, but in the example of FIG. 7, it is 160. Down counter 68 with "・" on the right shoulder of the block, level converters 63 and 69, and flip-flops 73 and 7
4 and 75 are high-speed ECL circuits. The lower part of the X counter 72 is also composed of an ECL circuit. Since the ECL circuit is more expensive than the TTL circuit, the TTL circuit is generally used for the low speed part. The X cursor data generation circuit is the same as in the case of FIG. 5 except that the number of bits is increased.

[Problems to be Solved by the Invention] When the resolution of the display screen is further increased, for example,
In the case of 2048x1536, 60Hz non-interlace, the pixel rate becomes 240MHz. At this time, in the conventional vertical cursor data generation circuit 65 shown in FIG. 7, there is a problem in the propagation delay time from the pixel clock of the down counter 68 to the B output. That is, while the period of the pixel clock is about 4 nS, the delay time of the down counter 68 is about 4.5 nS, and this value fluctuates due to temperature changes and the like, so the output of the flip-flop 75 corresponds to one pixel clock. Error may occur. Therefore, there arises a problem that the position of the Y cursor 14 is not accurately determined. Further, the circuit is complicated and the phase adjustment with the pixel data side is required.

Therefore, an object of the present invention is to provide a vertical cursor data generator for a raster scan display device capable of supporting a high pixel rate with a simple circuit.

[Means for Solving the Problem] A vertical cursor data generation circuit for a raster scan display device according to the present invention includes an N (integer of 2 or more) bit counter that counts a pixel clock and a horizontal coordinate of a vertical cursor that forms a crosshair cursor. A comparator for comparing the upper n bits of the data (a positive integer less than N) with the upper n bits of the output of the counter to detect a match between the two data, and a lower (N-n) bit of the horizontal coordinate data. Decoder means for decoding and output data of the decoder means are loaded in parallel according to the output of the comparator, and the load data is vertically shifted and output by a pixel clock ^(N- n ⁾ bit shift register. It is the one.

[Operation] In the vertical cursor data generation circuit for raster scan display device of the present invention, the display screen is divided into a plurality of vertical blocks, and the Y-cursor X coordinate upper bit corresponding to the vertical block to which the Y cursor 14 belongs is output to the X counter. It is detected that the pixel scanning has reached the block by comparing with, and the decode output of the Y cursor X coordinate lower-order bit is loaded in parallel to the shift register in accordance with this detection signal, and serial shift output is performed according to the pixel clock. In the present invention, the decode output of the Y-cursor X-coordinate lower bit is loaded in parallel to the shift register and is serially shifted and output according to the pixel clock. Therefore, vertical cursor data suitable for use in a raster scan display device having a high pixel rate is provided. A generator circuit is obtained.

[Embodiment] FIG. 1 is a block diagram of a first embodiment of a vertical cursor data generation circuit for a raster scan display device according to the present invention. The same components as those in FIG. 7 are designated by the same reference numerals.
The resolution of this raster scan display device is 2048x1530 and the pixel rate is 240MHz. In the latch circuit 80 of the vertical cursor data generation circuit 71, only the upper bits (for example, 8 bits) of the 11-bit X coordinate of the Y cursor 14 are loaded. The comparator 78 compares the data of the latch circuit 80 with the same number of upper bits of the 11-bit X counter 72. Instead of detecting whether the pixel scan has reached the X coordinate of the Y cursor 14, the display screen is divided into a plurality of vertical blocks 16 to determine whether the pixel scan has reached the vertical block 16 to which the Y cursor 14 belongs. The detection is similar to that of the circuit shown in FIG. However, if the pixel width of one block 16 is the same, the number of blocks in this embodiment is 256. The latch circuit 90 is blocked by the processor via the bus 94.
Y cursor pattern data representing the position of the Y cursor 14 within 16 is loaded. This Y cursor pattern data is obtained by decoding the lower few bits (3 bits in this example) of the X coordinate of the Y cursor 14. The output data of the latch circuit 90 is applied to the parallel input terminal of the shift register 84 via the level converter 88 that converts the signal level from the TTL level to the ECL level. This data is loaded into the shift register 84 according to the signal applied to the LD input terminal from the comparator 78 via the level converter 79. Shift register
Reference numeral 84 always receives the pixel clock during the pixel scanning and continues the shift operation, and shifts the 0 signal from the grounded serial input terminal when the data from the latch circuit 90 is not loaded. When the pixel scanning reaches the block 16 to which the Y cursor 14 belongs, the load signal is output from the comparator 78 and the data from the latch circuit 90 is loaded into the shift register 84. From the next pixel clock, the 8-pit Y cursor pattern (corresponding to the lower 3 bits of the X coordinate) in the block 16 loaded in the shift register 84 is shifted and superimposed on the pixel data via the gate 58 and the gate 62. . However, both gates are different from ECL in Fig.5.
It must be composed of a circuit. Shift register 84 with "・" on the right shoulder of the block, latch circuit 90, level converter
The circuits of the lower 3 bits of 79 and 88 and the X counter 72 are high-speed ECL circuits as described above. The X cursor data generation circuit 41 is similar to the case of FIG. 5 except that the number of bits is increased. The propagation delay time from the clock input to the shift output of the shift register 84 is about 2.2 nS in the ECL circuit and smaller than the pixel clock frequency 4 nS, and this delay is the shift register for pixel data (see FIG. 5).
(Corresponding to 60) is almost the same as the delay, so there is no need to adjust the phase between the two.

Next, a second embodiment of the present invention will be described with reference to FIG. Also in this embodiment, the Y cursor pattern data is loaded into the shift register 84 as in the first embodiment.
The difference from the first embodiment is that the Y cursor pattern data is generated not by the processor but by the decoder 108. The decode 108 is an 11-bit latch circuit 1
Lower 3 of X coordinate data of Y cursor 14 latched in 04
The bit is received through level converter 106 and its 8-bit decoded output is provided to the parallel input of shift register 84. The truth table of the decoder 108 is as follows.

Truth table input output 000 00000001 001 00000010 010 00000100 011 00001000 100 00010000 101 00100000 110 01000000 111 10000000 The output of the decoder 108 is loaded into the shift register 84 according to the output signal of the comparator given through the level converter 79, Gate 58 in synchronization with the pixel clock (Fig. 5)
Is output to. The decoder 108 does not necessarily have to be an ECL circuit, but the reason why this is an ECL circuit is that if the level converter 106 is provided in the subsequent stage, eight level converters are required, but if it is provided in the previous stage. This is because it only needs three. The actual level translator is a relatively expensive device such as the Motorola MC10124, which contains four level translators on a single chip. Therefore, although three devices are required in the first embodiment, one device may be used in this embodiment, and the required arrangement space and the number of wirings are small. Also, in the first embodiment, the Y cursor
The processor generates a Y-cursor pattern based on 14 X-coordinates, whereas in this embodiment a dedicated decoder 10 is used.
Since the decoding process is performed by 8, the load on the processor can be reduced.

When the vertical cursor data generation circuit of the present invention is applied to a color raster scan display device, the gate shown in FIG.
Instead of 62, a circuit as shown in FIG. 3 is used. The shift registers 115R, 115G, 115B take in the pixel data R, G, B in response to the load signal, and shift-output to the A input terminals of the data selectors 117R, 117G, 117B in accordance with the pixel clock. Each B input terminal of the data selector 117 receives the corresponding output bit of the latch circuit 119 holding the color code from the processor. Data selector 117 is gate 5
The A or B input is selected and output according to the cursor data from 8 (Fig. 5). With this configuration, the output of the latch circuit 119 is selected for the pixels forming the cursor, and the cursor is displayed in the color designated by the color code.

Although the preferred embodiments of the present invention have been described above, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the gist of the present invention. For example, although the crosshair cursor 18 is displayed on the entire display screen 10, it may be displayed only on the intersecting portion. To do this, take the Y cursor as an example.
It suffices to compare the output of the counter with the reference data before and after the intersection so that the load signal is given to the shift register 84 only near the intersection. Also, the number of blocks 16 of the display screen and the number of pixels in one block 16 may be different from those in the embodiment.

As described above, according to the vertical cursor data generation circuit for raster scan display device of the present invention, the Y cursor X coordinate lower bit corresponding to the block to which the Y cursor 14 belongs is decoded, and this data is compared. Since it is loaded in parallel to the shift register according to the output of the above and is serially shifted out according to the pixel clock, a vertical cursor data generation circuit suitable for a raster scan display device having a high pixel rate can be obtained. Also, the circuit configuration becomes relatively simple.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is cursor data for applying the present invention to a color raster scan display device. And a block diagram explaining a method of superimposing pixel data, FIG. 4 is a display screen diagram of a crosshair cursor,
FIG. 5 is a block diagram of a raster scan display pixel data generating circuit including a conventional cursor generator, FIG. 6 is a display screen diagram for explaining a conventional vertical cursor data generating method adopted by the present invention, and FIG. FIG. 7 is a block diagram of a conventional vertical cursor data generation circuit adopting the vertical cursor data generation method of FIG. In the figure, 72 is an N-bit counter, 78 is an n-bit comparator, 84 is a 2 ^(N- n ⁾ -bit shift register, and 108 is a decoder.

Claims (1)

[Claims] 1. An N (integer of 2 or more) bit counter for counting a pixel clock, and upper n (a positive integer less than N) bits of horizontal coordinate data of a vertical cursor forming a crosshair cursor are output from the counter. A comparator for detecting a match between the two data by comparing with the upper n bits, a decoder means for decoding the lower (N-n) bits of the horizontal coordinate data, and an output of the decoder means according to the output of the comparator. A vertical cursor data generator for a raster scan display device, comprising: 2 ^(N- n ⁾ bit shift registers in which data is loaded in parallel and the loaded data is serially shifted and output according to a pixel clock.