JPH0687231B2 - Buffer memory control method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer storage control method in a data processing device, and more particularly to a transfer block determination method for efficiently performing operand access.

(Prior Art) Conventionally, regarding transfer block determination in this type of buffer storage control method, if the block that sent the access request does not exist in the buffer memory, the central processing unit transfers the block from the main memory device to the buffer memory. The method was publicly known. Regarding the fetch of the instruction code, the prefetch method is currently used on the buffer memory.
A method is known in which the block next to the required block is transferred.

(Problems to be Solved by the Invention) In the conventional buffer storage control method described above, a method of transferring a block corresponding to an access request sent from the main storage device to the buffer memory is known, except for the prefetch method. When the data of the area to be handled is handled as an operand, the block before the current block, especially when the start address is near the block boundary,
Or it is more efficient to transfer the next block. However, since the conventional system does not have such a judgment logic, there is a drawback that it is impossible to judge the transfer.

When the prefetch method is used, the prospective transfer of the next block at the block boundary is carried out, but this also only carries out the transfer in the direction of increasing addresses, and has the drawback that it is a simple logic.

An object of the present invention is to extract and hold the continuous fetch direction of operands from an instruction code, and determine the block to be transferred to the buffer memory from the address information in the block and the operand length information based on the held signal. Therefore, it is an object of the present invention to provide a buffer storage control system configured to eliminate the above-mentioned drawbacks and to easily determine a block to be transferred.

(Means for Solving the Problems) The buffer storage control method according to the present invention compares a block number with a main memory, a central processing unit, a buffer storage located between the main memory and the central processing unit. And a block number difference deciding / adjusting means.

The block number comparator is a buffer memory that rewrites the contents of the buffer memory from the main memory by a block transfer method when no data exists inside the buffer memory in response to a memory access request from the central processing unit. It is for comparing the block number output from the device with the block number output from the central processing unit.

The address direction instruction means is for determining the continuous fetch direction of the operand from the instruction code and holding it.

The block number difference determining / adjusting means is for selecting the block which can be most efficiently transferred to the buffer memory device for rewriting the buffer memory device from the output of the address direction indicating device, the address information in the block, and the operand length information. Is.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the buffer storage control system according to the present invention. In FIG. 1, 1 is a main memory device, 2 is a buffer memory device, 3 is a central processing unit, 4 is an address direction indicator, 5 is a block number comparator, 6 is a block number difference determination circuit, and 7 is a block number adjustment. It is a vessel.

In FIG. 1, a buffer storage device 2 is arranged between a main storage device 1 and a central processing unit 3 to construct a hierarchical storage configuration. The block transfer path 8 connects the main storage device 1 and the buffer storage device 2 so that the requested data is stored in the buffer storage device
If it does not exist inside the block, it is rewritten in block units. A data bus 9 is connected between the buffer storage device 2 and the central processing unit 3. Instructions for example the address direction indicator 4 are trying to run, in the long operation of operand length as adding or subtracting, when starting the calculation from 2 ⁰ bit side of the operands are excisional the state of "1", When it is not related to the weight like a transfer instruction, the state of "0" is set.

In other words, when the output of the address direction indicator 4 is "1", the address is sequentially decreased in the decreasing direction, and when the output is "0", the address is sequentially increasing in the increasing direction.
Indicates that the operand is fetched. The block number sent from the buffer storage device 2 onto the signal line 10,
The block number comparator 5 compares the block number requested by the access and sent from the central processing unit 3 to the signal line 112 by the block number comparator 5 to determine whether or not the corresponding block exists in the buffer storage device 2. .

When the operand data requested by the block number comparator 5 does not exist in the buffer storage device 2, the block number difference determination circuit 6 is sent via the signal line 15.
A start signal is output to. In the block number difference determination circuit 6, the address information in the block of the requested operand data on the signal line 12, the operand length on the signal line 13, and the address sent from the address direction indicator 4 to the signal line 14 The most efficient block is selected from the direction indication signal, the difference between the requested block number and the selected block number is created, and the difference is sent out on the signal line 16. The block number adder / subtractor 7 generates a block number to be transferred to the buffer storage device 2 based on the difference described above, and sends it to the signal line 17.

Next, an actual example of the difference determination logic inside the block number difference determination circuit 6 will be described. FIG. 2 is an explanatory diagram showing a data block in which 256 bytes are configured as one block for this purpose.

At present, the operand requested by the central processing unit is the i-th
It is assumed that it exists in the second block and is not transferred to the buffer storage device 2. First, when the address direction indicator 4 is in the state of "0", it is judged whether or not the address information in the block on the signal line 12 is in the word in the shaded area in FIG. 2 (the word of the maximum address in the block). If it is inside the diagonal line, the operand length is taken into consideration to determine whether or not the block boundary is crossed. If the block boundary is crossed, it is determined that it is more efficient to transfer the (i + 1) th block, and the difference "+1" is generated. When the address direction indicator 4 is in the state of "1", it is judged whether or not the address information in the block on the signal line 12 indicates in the word (word of the minimum address in the block) in FIG. . If it is inside the diagonal line, it is more effective to transfer the (i-1) th block if the operand length is taken into consideration to determine whether or not it exceeds the block boundary. It is determined to be the target, and the difference “−1” is generated. In all other cases, "0" is generated as the difference, and the block number adder / subtractor 7 generates the transfer block number.

As described above, according to the present invention, the address direction of the operand can be indicated, and the block to be transferred to the buffer storage device is determined from the address in the block and the operand length. The effect is that the buffer storage device can be used efficiently.

Further, even in the worst case in which the block transfer has to be performed twice consecutively, according to the present invention, the processing can be completed by one block transfer, so that the processing efficiency of the entire system is improved, and particularly the decimal operation is performed. There is an effect that the processing is efficiently performed in the office processing device that handles many string instructions such as.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment for realizing the buffer storage control method according to the present invention. FIG. 2 is an explanatory diagram showing an example of a logic system for determining the difference between block numbers. 1 ... Main storage device, 2 ... Buffer storage device 3 ... Central processing unit 4 ... Address direction indicator 5 ... Block number comparator 6 ... Block number difference determination circuit 7 ... Block number adder / drainer 8 ... … Block transfer path, 9 …… Data bus 10 to 17 …… Signal line

Claims (1)

[Claims] 1. A main storage device, a central processing unit, a buffer storage device placed between the main storage device and the central processing unit, and the buffer for a memory access request from the central processing unit. When there is no data inside the storage device, the block number output from the buffer storage device and the central processing unit are output so that the contents of the buffer storage device can be rewritten by the block transfer method from the main storage device. A block number comparator for comparing with a block number, address direction indicating means for determining and holding a continuous fetch direction of an operand from an instruction code, output of the address direction indicating means, in-block address information, and A block that can be most efficiently transferred from the operand length information to the buffer storage device for rewriting the buffer storage device. Buffer storage control system, characterized by being configured to and a blow poke number difference determination / subtraction means for selecting.