JPH0687251B2 - Logic circuit simulation method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a logic simulation method for a digital logic circuit including logic elements such as AND gates and / or OR gates.

[Background of the Invention]

In order to perform a simulation of a digital logic circuit, usually, a method of converting a logic element such as an AND gate or an OR gate forming the logic circuit into a basic circuit capable of logic simulation and forming it on a memory of a general purpose computer or the like is used. To be In particular, in the logic circuit simulation that faithfully simulates the circuit delay of the logic element, the logic element forming the logic circuit and the basic circuit capable of logic simulation have a one-to-one correspondence. This is shown in FIGS. 1 and 2. That is, 11, 12, and 13 in FIG. 1 are logic elements of the logic circuit, and 21, 22, and 23 in FIG. 2 are basic circuits in which the logic elements 11, 12, and 13 are converted into simulatable forms, respectively. is there. One basic circuit consists of three parts 1, 2, and 3. 1 represents the function of the basic circuit, 2 represents the delay time of the basic circuit, and 3 represents the fan-out destination address to which the output signal value of the basic circuit should be transmitted.

By the way, in recent years, the number of logic elements of digital logic circuits has increased due to the progress of semiconductor technology, and the capacity on the memory of a general-purpose computer required for carrying out the logic circuit simulation, the computer time, and the like have increased dramatically. As a countermeasure against this, conventionally, a method has been adopted in which the number of basic circuits is reduced by paying attention to a functional group in the simulation target logic circuit and expressing it in a macro manner. Examples thereof are shown in FIGS. 3 and 4. In Fig. 3,
Reference numeral 30 denotes an adder, 31 denotes an input signal line to the adder 30, and 32 denotes an output signal line from the adder 30. Generally, one adder has the function of about 5 to 10 logic elements. FIG. 4 shows an example in which the adder 30 is converted into a basic circuit that can be simulated. Here, the basic circuit 40 consists of four parts,
41 represents the function (ADDER) of the basic circuit 40, and 42 to 44 represent the fan-out destination address to which the output signal value of the basic circuit 40 should be transmitted.

According to the method of FIGS. 3 and 4, 5 to 10 basic circuits can be expressed by one basic circuit, and the memory amount can be reduced. However, the delay times between the input signal line 31 and the output signal line 32 are not equal to each other. for that reason,
With this method, it is not possible to accurately simulate the circuit delay of each logic element that constitutes an actual digital logic circuit. So, for example, even if the simulation is normal, the actual delay time may not be reflected correctly,
When the function is lowered to the logic element, there is a problem that a logic defect cannot be found.

[Object of the Invention]

An object of the present invention is to simulate a digital logic circuit composed of basic logic elements such as AND gates or OR gates in consideration of the circuit delay of the logic element.
It is an object of the present invention to provide a logic circuit simulation method that can reduce the amount of memory required for a general-purpose computer or the like as compared with the related art, and further reduce the computer time of the computer.

[Outline of Invention]

In order to achieve the above object, the present invention extracts a partial circuit of only combinational logic composed of logic elements such as AND gates or OR gates included in a digital logic circuit to be subjected to logic simulation, and extracts the partial circuit of the partial circuit. Focusing on input terminals and output terminals, a virtual element having logical equivalence and physical equivalence such as circuit delay is generated, and the virtual element is replaced with the partial circuit to be a target of logic simulation. The number of basic circuit elements is reduced, and the number of times of signal value propagation processing to the fan-out element, which accounts for about 80% of the logic simulation processing time, is reduced to reduce the simulation processing time.

[Embodiment of the Invention] FIG. 5 shows an example of a partial circuit composed only of combinational logic by basic logic elements in a digital logic device. Fifth
In the figure, AND gate 51 receives inputs a and b, and AND gate 5
2 has c and d as inputs, and the delay time is 1 ns in both cases. OR
The gate 53 receives the outputs of the AND gates 51 and 52 and has a delay time of 2 ns. The OR gate 54 receives e and f as inputs, and the delay time is
2 ns. The OR gate 55 receives the outputs of the OR gates 53 and 54, and its delay time is 3 ns.

Focusing on the fact that the AND gates 51 and 52 of the logic circuit (partial circuit) of FIG. 5 have the same delay time, the logic circuit is
It can be replaced as shown. That is, the circuit 61 in FIG. 6 corresponds to the group of AND gates 51, 52 and OR gate 53 in FIG. 5, and the delay time is 3 ns. The OR gates 62 and 63 are the fifth
It is the same as the OR gates 54 and 55 in the figure.

When the logic circuit shown in FIG. 5 is directly converted into a form that can be simulated, basic circuits 71 to 75 that can be simulated are formed on the memory of a general-purpose computer as shown in FIG. On the other hand, if the logic circuit shown in FIG. 5 is converted into that shown in FIG. 6, the simulatable basic circuit formed on the memory of the general-purpose computer becomes as shown in FIG. That is, the basic circuits 81, 82 and 83 of FIG. 8 correspond to the basic circuits 61, 62 and 63 of FIG. 6, respectively, and two basic circuits that can be simulated can be reduced as compared with FIG.

FIG. 9 shows a processing procedure according to the present invention. First, level numbers are assigned in ascending order from the basic circuit (basic logic element) on the input side of the logic circuit to the basic circuit on the output side (step 91). Of the unprocessed basic circuits, the one with the lowest level number is the basic circuit to be processed (step
92). A basic circuit group is formed by the basic circuit to be processed and the basic circuit that is the source (step 9).
3). All the delay times between the input pin and the output pin of the formed basic circuit group are examined, and it is judged whether all the delay times are equal (steps 94 and 95). If the result of determination is that they are all the same, a basic circuit having a function that is logically equal to the basic circuit group is generated, and the basic circuit group is replaced with this basic circuit group (step 96). Here, as for the combinational circuit, since the functions can be expressed in the same format, the function expression part of the generated basic circuit and the function expression part of the basic circuit (basic logic element) such as AND gate and OR gate The amount of memory per basic circuit is the same (see FIG. 8). Next, the delay time of the generated basic circuit is set as the sum of the delay time of the processing target basic circuit and the delay time of the source basic circuit (step 97). The basic circuit that is the sink of the generated basic circuit is the basic circuit to be processed (step 9
8), and the processing after step 93 is repeated. Similarly, these processes are repeated until there are no unprocessed basic circuits (step 99).

By applying the above processing to FIG. 5, a basic circuit that can be simulated is formed in the memory of the computer as shown in FIG.

Note that the number of basic circuits that are sources in step 93 of FIG. 9 may be one. In this case, as shown in FIG. 10, the basic circuit 102 with one input is eliminated, and this and the basic circuit 101 are combined to form a basic circuit 103.

Also, for example, in the logic circuit of FIG.
If the delay time of 2 is 3 ns and the delay times of the basic circuits 61, 62 and 63 are all equal, the logic circuit of FIG. 6 can be further replaced by the basic circuit 110 shown in FIG.

About 80% of the simulation processing time is normally occupied by the signal value propagation processing, and the signal value calculation processing occupies only a small proportion. This complicates the function of the basic circuit,
Even if the output signal value calculation processing time per basic circuit increases, if the number of basic circuits decreases, the signal value propagation processing time decreases, and the simulation processing time also shortens. The present invention aims at this.

〔The invention's effect〕

As described above, according to the present invention, since the number of basic circuits to be simulated in the logic circuit is reduced,
The amount of memory required for simulation of a general-purpose computer or the like is reduced. Further, since the number of basic circuits is reduced and the number of output signal value calculations and the number of signal value propagations after the simulation are performed are reduced, the computer processing time required when the simulation is performed can be shortened.
Furthermore, since the basic circuits are grouped within a range in which the delay time and the logical operation do not change, the actual delay time and the like can be reflected correctly.

[Brief description of drawings]

1 and 2 are diagrams for explaining an example of a conventional logic circuit simulation method, FIGS. 3 and 4 are diagrams for explaining another example of a conventional logic circuit simulation method, and FIG.
11 to 11 are diagrams for explaining the method of the present invention, FIG. 5 is a logic circuit diagram before the number of basic circuits is reduced, and FIG. 6 is a logic circuit after the number of basic circuits of the logic circuit of FIG. 5 is reduced. A circuit diagram, FIG. 7 is a diagram showing an example in which the logic circuit of FIG. 5 is converted into a simulatable basic circuit and expanded on a memory of a computer, and FIG. 8 is also able to similarly simulate the logic circuit of FIG. FIG. 9 is a diagram showing an example converted into a basic circuit, FIG. 9 is a flow chart showing a processing procedure of the present invention, and FIGS. 10 and 11 are diagrams showing other specific examples according to the present invention. 51-55 …… Basic circuit before conversion, 61-63 …… Basic circuit after conversion, 81-83 …… Basic circuit that can be simulated.

Front page continuation (72) Inventor Osamu Tada 1 Horiyamashita, Hinoyama, Hadano, Kanagawa Pref., Kanagawa Plant, Hiritsu Manufacturing Co., Ltd. (72) Yasuo Nagura, 1st, Horiyamashita, Hadano, Hadano, Kanagawa Pref. 56) References Information processing, Vol. 22, No. 8 (1981) PP. 762-769

Claims (1)

[Claims] 1. A basic circuit group is formed by a basic circuit to be processed and a basic circuit which is a source of the basic circuit,
When all the delay times between the input pins and the output pins of the basic circuit group are checked, and when the delay times between the input pins and the output pins are all equal, a virtual basic circuit having a function logically equivalent to the basic circuit group is selected. By generating and replacing the virtual basic circuit with the above basic circuit group and repeating the above process for all the basic circuit groups, the logic circuit is simulated according to the replaced virtual basic circuit. And a logic circuit simulation method.