JPH0687497B2 - Memory integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a memory integrated circuit device having a unit memory cell of a circuit composed of a flip-flop circuit composed of two npn type transistors and a load composed of a pnp type transistor. Is.

[Conventional technology]

Conventionally, in a memory integrated circuit element that includes a unit memory cell including a flip-flop circuit composed of two npn-type transistors, (1) a load resistor and a parallel load of a BC (PN junction) diode are used as a load element of the memory cell. (2) Load resistance and Schottky barrier diode (SB
D) Parallel load (3) Three pnp transistor loads are used.

(1) Load resistance and BC diode parallel load (Fig. 3)
At the time of address access, the forward potential of the BC (PN coupling) diode is as large as about 0.8V, and the npn-type transistor that constitutes the flip-flop circuit is driven into saturation. Therefore, a technique for performing gold diffusion as a hole killer is introduced. However, it is becoming an old technology because it is difficult to realize shallow junction and high integration.

(2) Load resistance and Schottky barrier diode (SB
The parallel load of (D) (Fig. 4) has a small forward potential of SBD at the time of address access, which is as small as 0.45V. Therefore, the npn-type transistor that configures the flip-flop circuit is not driven into saturation. Is rapidly written (inversion of the memory cell). Since it does not diffuse gold, it is also suitable for shallow junctions and is a powerful loading method for realizing high-speed, highly integrated memory cells.

However, as high integration progresses, the power consumption at the time of holding the memory (holding current flows through the load resistance) cannot be ignored, and the resistance of the load resistance becomes high (several hundred KΩ to 1 MΩ).
Is becoming essential and has become a major constraint on the process. In addition, the introduction of SBDs inevitably complicates the process, which is a major problem in terms of yield and cost.

Against this background, the (3) pnp transistor load (Fig. 5) is drawing attention in the field of memory integrated circuit devices aiming at high speed, high integration, and low power consumption.

[Problems to be solved by the invention]

In the memory cell equipped with a pnp-type transistor load, which has been drawing attention in the field of memory integrated circuit devices aiming for high-speed / high-integration and low power consumption, the current amplification factor (β) of the pnp-type transistor and the memory There is a close correlation between device characteristics.

That is, as shown in FIG. 5, when the current amplification factor (β) of the pnp-type transistor is large, a flip-flop circuit is constituted of the read / write current ( _ID ) of the memory cell.
Current flowing into the base region of an npn-type transistor (β /
β + 1 _ID ) becomes large, and as a result, the npn-type transistor is driven into the saturation region, the change of the npn-type transistor from the ON state to the OFF state is delayed at the time of writing the memory cell, and the write pulse of the memory element characteristics, in particular, the write pulse. Width (T _WP )
The inconvenience of increasing In order to eliminate such inconvenience, if the base width of the pnp type transistor is increased, the current amplification factor (β) can be inevitably reduced. However, if the base width is easily expanded, the memory cell pattern and the chip area are increased, which is incompatible with the trend toward higher speed and higher integration.

An object of the present invention is to match the direction of high speed / high integration and low power consumption without expanding the base width of a pnp type transistor which is a load of a memory cell, and to provide a pnp which has an optimum current amplification factor for memory cell operation. An object of the present invention is to provide a memory integrated circuit device including a memory cell having a type transistor.

[Means for solving problems]

The memory integrated circuit device of the present invention comprises a flip-flop circuit in which the n-type collector and the p-type base of two npn-type bipolar transistors are mutually separated, and the n-type collector region and the p-type base region of the npn-type bipolar transistor. Pnp with base region and collector region respectively
In a memory integrated circuit element composed of unit memory cells composed of a load composed of a bipolar transistor,
The n-type base region sandwiched between the p-type emitter region and the p-type collector region of the load pnp-type transistor is parallel to the p-type emitter region and the p-type collector region, and from the surface in the direction orthogonal to the element insulating region. The insulator is provided so as to dig into a certain depth, and a gap is provided in the insulator, and the current amplification factor of the pnp transistor is set to an optimum value by the width of the gap. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are a sectional view and a plan view of a memory cell portion according to an embodiment of the present invention.

First, as shown in FIG. 1A, a p-type silicon substrate 1
After providing the high-concentration n-type silicon layer 2 thereon, the n-type silicon epitaxial layer 3 is grown. Next, after a silicon oxide film 4 for element isolation is provided, an npn type transistor which constitutes a unit memory cell and a pnp type transistor according to the present invention are formed in an island surrounded by the silicon oxide film 4.

That is, the npn transistor base 5, read / write emitter 6, information holding emitter 7, collector 3 and pnp
-Type transistor emitter 8, collector 5, and emitter,
It is made of a silicon oxide film 9 provided between the collectors. The silicon oxide film 9 is provided in a region sandwiched between the emitter 8 and the collector 5 of the pnp type transistor, and the silicon oxide film 9 may be in contact with the emitter 8 and the collector 5 or may be present in the middle.

FIG. 1 (b) is a plan view of a memory cell having the pnp-type transistor of the embodiment shown in FIG. 1 (a) as a load. npn-type transistor bases 101, 201 and collectors 101,
A flip-flop circuit is formed by connecting 201 and collectors 103 and 203 to each other. The read / write emitters 104 and 204 are digit lines 1
It is connected to 05,205. In addition, information holding emitters 102, 20
2 is the word bottom line 1 of the second layer after being connected by common wiring
Connected to 06. pnp transistor emitter 10
7,207 are connected to the common word top line 108, and a memory cell having a pnp-type transistor as a load is formed. Silicon oxide films 109, 110, 209, 210 are selectively formed in the base region of the load pnp transistor by the ordinary photolithography technique and thermal oxidation method. The silicon oxide films 109, 110 and 209, 210 are provided with gaps 110, 211, respectively, and the current amplification factor of the load pnp transistor of the memory cell is set to an optimum value.

Incidentally, FIG. 1 (a) is a sectional view taken along the line AA 'in FIG. 1 (b).

FIG. 2 is a plan view of another embodiment of the present invention.

In this embodiment, the oxide films 309, 310 and 409, 410 provided in the base region of the load pnp type transistor of the memory cell are A
The gaps 311 and 411 provided in the oxide film that overlap in the −A ′ axis direction and the BB ′ axis direction increase the effective base length (width) of the load pnp transistor, making it easier to realize the optimum current amplification factor (β). to enable.

The effect of the present invention will be described with reference to FIG. 5 again. For example, when the read / write current ( _ID ) at the time of accessing the memory cell is 700 μA, β of the pnp transistor is 5
Is the current flowing into the base of the npn-type transistor. Is And the transistor is driven sufficiently into the saturation region. If β is 0.1, Since the npn-type transistor is driven in the active region,
When the memory cell is inverted, the npn-type transistor quickly becomes O
Change from N state to OFF state. In the case of a pnp-type transistor that can be obtained by the usual introduction of impurities, if the base width is 3 μm,
A value of 3 to 5 is obtained as the current amplification factor. To reduce this to about 0.1, a base width of 10-15 μm is required,
For example, in the case of a 16K-bit RAM, it is composed of 128 rows × 128 columns, so the size of the memory cell section is (15μm-3μ
m) × 128 = 1536 μm = 1.5 mm increase.

However, when the pnp-type transistor according to the present invention is adopted, even if the base width is 3 μm, the current amplification factor (β) can be reduced to 0.1 and the write pulse width of the memory cell can be increased without increasing the chip area. It is possible to reduce the size of the memory device and thus speed up the memory device.

〔The invention's effect〕

As described above, according to the present invention, the n-type base region sandwiched between the p-type emitter region and the p-type collector region of the pnp-type transistor, which is the load of the memory cell, is parallel to the p-type emitter region and the p-type collector region, In addition, by providing an insulator in a direction perpendicular to the element insulation region so as to penetrate to a certain depth from the surface, and setting the current amplification factor of the pnp-type transistor to the maximum value by the width of the gap, the pnp-type transistor The current amplification factor (β) can be reduced without expanding the base width of the memory cell, the base current of the npn-type transistor forming the memory cell can be reduced, and the write (reversal) operation of the memory cell can be performed quickly. .

[Brief description of drawings]

1 (a) and 1 (b) are a sectional view and a plan view of a memory cell portion according to an embodiment of the present invention, and FIG. 2 is a plan view of a memory cell portion according to another embodiment of the present invention, and FIG. Is a circuit diagram of a flip-flop type memory cell having a load resistance and a parallel load of a BC (PN) diode, which is an example of the related art, and FIG.
FIG. 5 is a circuit diagram of a flip-flop memory cell having a load resistance and an SBD parallel load as an example of FIG. 5, and FIG. 5 is a circuit diagram of a flip-flop memory cell having a load of a pnp transistor as a third example of the related art. is there. 1 ... p-type silicon substrate, 2 ... high-concentration n-type silicon layer (buried layer), 3 ... n-type silicon epitaxial layer, 4
...... Silicon oxide film, 5 …… Base (npn type), 6 ……
Read / write emitter (npn type), 7 ... Information holding emitter (npn type), 8 ... Collector (npn type),
9 ... Silicon oxide film selectively provided so as to penetrate into the base region of the pnp transistor, 101, 201 ... Base (npn type), 102, 202 ... Information holding emitter (npn
Type), 103,203 …… collector (npn type), 104,204 …… read / write emitter (npn type), 105,205 …… digit line, 106 …… word bottom line, 107,207 …… emitter (pnp type), 108 …… Word top line (pnp type), 10
9,209 …… Silicon oxide film selectively provided to bite into the base region (pnp type), 111,211 …… Gap between silicon oxide films, 309,310,409,410 …… Selective to bite into the base region (pnp type) Provided silicon oxide film, 311,
411: A gap between silicon oxide films.

Claims (1)

[Claims] 1. The n of two npn type bipolar transistors.
A flip-flop circuit in which a p-type collector and a p-type base are mutually stacked, and a load composed of a pnp-type bipolar transistor having an n-type collector region and a p-type base region of the npn-type bipolar transistor as a base region and a collector region, respectively. In a memory integrated circuit element including a unit memory cell configured by, the p-type emitter region and the p-type emitter region are provided in an n-type base region sandwiched between the p-type emitter region and the p-type collector region of the load pnp-type transistor.
The pnp transistor has a current that is parallel to the type collector region and orthogonal to the element insulating region, and is provided so as to invade the insulator to a certain depth from the surface. A memory integrated circuit device characterized in that the amplification factor is set to an optimum value depending on the width of the gap.