JPH0689573A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to reduce power consumption during standby operation of a DRAM. [Structure] An internal power supply Vint obtained by stepping down an external power supply Vcc by an internal power supply regulator 13 is supplied to a memory cell 4, a back bias Vw is supplied to a back gate of a cell transistor constituting the memory cell 4, and the cell transistor is a P channel. It is composed of a MOS transistor 21 and a capacitor 23, and a back bias Vw having a potential higher than the internal power supply Vint is supplied to the P-channel MOS transistor 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a dynamic RAM.
(Hereinafter referred to as DRAM).

A portable electronic device such as a laptop personal computer can use a battery as a power source. Therefore, it is required to reduce the power consumption of the DRAM used in such a portable electronic device.

[0003]

2. Description of the Related Art FIG. 10 shows the structure of a conventional DRAM.
That is, the address signals A0 to A9 are input to the column decoder 2 and the row decoder 3 via the address buffer 1, and the memory cells in the memory cells 4 are selected based on the output signals of the column decoder 2 and the row decoder 3.

The cell transistors forming the memory cell 4 are N-channel MOS transistors. At the time of writing operation, for example, control signals RAS, C
Both AS bars become L level. Its control signal RAS
Clock generator 5, based on bar, CAS bar
Based on the signal output to the write clock generator 7 via 6 and the write control signal WE bar, the write clock generator 7 operates the data input buffer 8.

The data input buffer 8 outputs the write data Din to the sense amplifier and the I / O gate 9, and the write data Din is written in the memory cell selected via the sense amplifier and the I / O gate 9.

Further, for example, during a read operation in which the control signal CAS bar becomes H level, the write clock generator 7 and the data input buffer 8 are inactivated based on the write control signal WE bar.

The cell information read from the selected memory cell is output as an output signal Dout via the sense amplifier, the I / O gate 9 and the data output buffer 10.

In the standby state waiting for the write operation or the read operation, the output signal of the clock generator 5 based on the control signal RAS bar and the control signal CAS.
The mode control 11 operates based on the bar.

The refresh address counter 12 is operated by the operation of the mode control 11 and the address signal for the refresh operation is output to the predecoder in the address buffer 1.

Then, based on the refresh address signal output from the address buffer 1 to the column decoder 2 and the row decoder 3 and the clock signal output from the clock generator 6, it is stored in a memory cell in the memory cell 4. The cell information is refreshed in sequence.

The clock signal output from the clock generator 5 is also output to the internal power supply regulator 13. The internal power supply regulator 13 is provided in order to extend the life of the memory cell 4 and the elements constituting the peripheral circuit and stabilize the operation thereof. The internal power supply regulator 13 lowers the power supply Vcc supplied from the outside and makes it a constant voltage, and the internal power supply Vint. Is generated and supplied to each of the circuits.

The substrate bias generator 14 supplies a back bias to the cell transistors forming the memory cell 4. The substrate bias generator 1
Reference numeral 4 includes a ring oscillator that oscillates a predetermined frequency by connecting an odd number of inverter circuits in a ring shape, and a pumping circuit that outputs a predetermined bias voltage based on the oscillation frequency of the ring oscillator.

Such a substrate bias generator 14
If 0 V is supplied as the low-potential-side power supply Vss of the memory cell 4, a potential of 0 V or less is supplied to the back gate of each cell transistor as the back bias.

By supplying the optimum bias voltage, it is possible to prevent an increase in the diffusion layer capacitance of each cell transistor and an accompanying increase in the bit line capacitance.

If the bias voltage is too high,
In the diffusion layer on the side of the charge storage node of the cell transistor, the depletion layer region is expanded to the region where the lattice defect generated at the time of ion implantation exists, thereby increasing the junction leak current and shortening the refresh operation cycle. I won't.

However, by supplying the optimum bias voltage from the substrate bias generator 14 as described above, the occurrence of the above problems can be prevented.

[0017]

DRAM as described above
The power consumption during the standby operation is due to the power consumed by the ring oscillator in the substrate bias generator 14, the power consumed in the reset potential generation circuit that generates an intermediate potential for resetting the bit line potential, and the junction leak current. Power consumption.

Among them, the power consumption of the ring oscillator accounts for 50% or more of the total power consumption. Therefore, in the conventional DRAM, the oscillation frequency of the ring oscillator is lowered to reduce the power consumption during the standby operation. There is.

However, the lower the oscillation frequency of the ring oscillator is, the smaller the difference between the bias voltage output from the substrate bias generator 14 and the power supply Vss becomes. Therefore, the oscillation frequency of the ring oscillator is ensured while securing the necessary bias voltage. Keeping it low is not easy.

Therefore, there is a problem that the power consumption during the standby operation cannot be sufficiently reduced. An object of the present invention is to reduce power consumption during a standby operation of DRAM.

[0021]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the internal power supply Vint obtained by stepping down the external power supply Vcc by the internal power supply regulator 13 is supplied to the memory cell 4, the cell transistor back bias Vw forming the memory cell 4 is supplied, and the cell transistor is the P-channel MOS transistor 21. Capacitor 23
And the P-channel MOS transistor 21.
A back bias Vw having a potential higher than the internal power supply Vint is supplied to the back gate of the above.

Further, as shown in FIG. 2, an external power source Vcc is supplied as the back bias Vw. Also, FIG.
As the back bias Vw, as shown in FIG.
A potential as high as the threshold value of the OS transistor Tr9 is supplied.

[0023]

Since the cell transistor is composed of the P-channel MOS transistor 21, the back bias supplied to the transistor 21 may be a potential higher than the internal power supply Vint.

Therefore, the back bias potential can be easily generated based on the external power supply Vcc without the need for the ring oscillator.

[0025]

FIG. 9 is a block diagram of a DRAM showing first and second embodiments embodying the present invention. The same components as those in the conventional example will be described with the same reference numerals.

The cell transistor forming the memory cell 4 of the DRAM shown in FIG. 9 is formed of a P channel MOS transistor 21. In the first embodiment, the power supply Vcc is supplied as a back bias to the cell transistors constituting the memory cell 4, and in the second embodiment, the power supply Vcc and the power supply Vss supplied from the outside and the internal power supply Vint. Based on this, the well potential Vw generated by the well potential generation circuit 15 is supplied as a back bias.

That is, in the first embodiment, as shown in FIG. 2, the power supply Vcc supplied from the outside is supplied to the internal power supply regulator 13, and the internal power supply Vint generated by the internal power supply regulator 13 is supplied to the memory cell 4. Peripheral circuit 16
Is supplied to.

Then, the memory cell 4 is driven based on the peripheral circuit 16, and the maximum amplitude of the bit line becomes the potential difference between the internal power source Vint and the power source Vss. An example of the circuit configuration of the internal power supply regulator 13 will be described with reference to FIG. 4. The drain of the N-channel MOS transistor Tr1 is connected to the power supply Vcc via the resistor R1.
The gate of r1 is connected to the drain.

The source of the transistor Tr1 is connected to the drain of the N-channel MOS transistor Tr2, the gate of the transistor Tr2 is connected to its drain, and the source is connected to the power supply Vss.

Therefore, the transistors Tr1 and Tr2 and the resistor R1 form a reference voltage generating circuit. The transistors Tr1 and Tr2 are always turned on, and the reference voltage Vre output from the drain of the transistor Tr1.
As shown in FIG. 5, the power source Vcc has f
If the sum of the thresholds of 1 and Tr2 is exceeded, the constant voltage is based on the sum of the thresholds.

The drain of the transistor Tr1 is connected to the gate of the N-channel MOS transistor Tr3, and the source of the transistor Tr3 is connected to the drain of the N-channel MOS transistor Tr4. The source of the transistor Tr4 is connected to the power supply Vss.

The drain of the transistor Tr3 is connected to the drain of the P-channel MOS transistor Tr5, and the source of the transistor Tr5 is connected to the power supply Vcc. The gate of the transistor Tr5 is a P channel MOS
It is connected to the gate of the transistor Tr6 and the gate of the transistor Tr4, and the source of the transistor Tr6 is connected to the power supply Vcc.

The drain of the transistor Tr6 is connected to the drain of the N-channel MOS transistor Tr7, and the source of the transistor Tr7 is connected to the drain of the transistor Tr4.

The drain of the transistor Tr5 is connected to the gate of the P-channel MOS transistor Tr8, and the source of the transistor Tr8 is connected to the power supply Vcc.
The drain of the transistor Tr8 is connected to the power source Vss via the resistors R2 and R3, and the internal power source Vint is output from the drain.

The resistors R2 and R3 are connected to the gate of the transistor Tr7, and the transistors Tr3 to Tr7 form a current mirror circuit. Therefore, the current mirror circuit of the internal power supply regulator 13 is driven by the reference voltage Vref, and the voltage based on the internal power supply Vint which is the output voltage is input to the current mirror circuit as a negative feedback signal, and the internal power supply Vint is the reference voltage. Vre
It is further stabilized than f.

That is, the Vref is the transistor Tr3.
Is input to the transistor Tr3, the transistor Tr3 is turned on and the transistor Tr8 is turned on. Then, the transistor Tr7
Is turned on to turn on the transistors Tr5 and Tr6, and the transistor Tr4 is turned on to stabilize in this state.

When the internal power supply Vint tries to change based on the change of the reference voltage Vref, the transistor T
The negative feedback signal input to the gate of r7 operates to suppress the fluctuation of the internal power supply Vint.

Therefore, the internal power supply regulator 13 boosts the reference voltage Vref as shown in FIG. 3 based on the constant voltage reference voltage Vref shown in FIG. 5, and outputs the internal power supply Vint which is further made into a constant voltage. .

FIG. 6 shows the structure of a P-channel MOS transistor forming the cell transistor of the memory cell 4. That is, the N-type well 18 is formed in the P-type substrate 17, and a large number of P-type diffusion regions 19 are formed in the N-type well 18. A word line 20 forming a gate electrode is formed between the P type diffusion regions 19, and the word line 20 is formed.
A P-channel MOS transistor 21 is formed by the P-type diffusion regions 19 on both sides of the above.

A bit line 22 is connected to one of the P-type diffusion regions 19 forming the P-channel MOS transistor 21, and a cell capacitor 23 is connected to the other. Therefore, the P-channel MOS transistor 21 and the cell capacitor 23 constitute one memory cell, and one N-type well 18 constitutes many memory cells to constitute one cell block. It is composed of a plurality of cell blocks.

An N-type diffusion region 24 is formed at the end of the N-type well 18 in which the large number of P-channel MOS transistors 21 are formed. Is being supplied.

Therefore, the power source Vcc is supplied as the back bias of the P-channel MOS transistor 21 to the N-type well 18 constituting each cell block,
An increase in the diffusion layer capacitance of each P-channel MOS transistor 21 forming the cell transistor and a concomitant increase in the bit line capacitance are prevented.

In the DRAM constructed as described above, the cell transistor forming the memory cell is formed of the P-channel MOS transistor 21, and the P-channel M of the P-channel MOS transistor 21 is formed.
Power supply Vcc is used as back bias for the OS transistor 21.
Is being supplied.

As a result, the substrate bias generator for generating the back bias voltage supplied to the cell transistor is not necessary. Therefore, the ring oscillator, which was necessary to configure the substrate bias generator 14 in the conventional example, can be omitted in the present example, so that the power consumption during the standby operation of this DRAM can be reduced.

Since the P-channel MOS transistor is used as the cell transistor in this embodiment, the word line is set to the L level (0V) in the cell selected state, and the word line is set to the internal power source Vint in the other non-selected states. And

Further, the selected word line may be at L level (0 V or less). In this case, the negative voltage generation circuit 24 is required as shown in FIG. 9, and a circuit almost equivalent to the conventional substrate bias generator is required, but word line selection is only during the input period of the control signal RAS bar. The negative voltage generation circuit may be operated only during the input period of the control signal RAS bar.

Therefore, it is not necessary to move the substrate bias generator during standby as in the conventional case, so that power consumption is reduced. Further, as shown in FIG. 9, in the second embodiment, the power supply Vcc and the power supply Vss supplied from the outside,
Well potential generation circuit 1 based on the internal power supply Vint
The well potential Vw generated in 5 is supplied to the memory cell 4 as a back bias.

In the well potential generating circuit 15, as shown in FIG. 7, the power source Vcc is supplied to the source of the P channel MOS transistor Tr9 via the resistor R4. The internal power supply regulator 1 is connected to the gate of the transistor Tr9.
Internal power supply Vint is input from 3 and drain is power supply Vss
It is connected to the. Then, the source potential of the transistor Tr9 is supplied to the memory cell 4 as a well potential Vw, and the well potential Vw is also supplied to the back gate of the transistor Tr9.

The well potential generation circuit 15 configured as described above outputs to the memory cell 4 the well potential Vw at a level higher than the internal power supply Vint. That is, as shown in FIG.
When int is output, the well potential Vw output from the well potential generation circuit 15 to the memory cell 4 is the internal power supply Vint.
The potential is maintained higher by the threshold value Vthp of the transistor Tr9.

Therefore, the well potential Vw having a higher level than the internal power supply Vint supplied to the memory cell 4 is supplied, and the same effect as the first embodiment can be obtained.

[0051]

As described above in detail, the present invention is a DRA.
It has an excellent effect of reducing the power consumption during standby operation of M.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is an input / output characteristic diagram of an internal power supply regulator.

FIG. 4 is a circuit diagram showing an example of an internal power supply regulator.

FIG. 5 is an input / output characteristic diagram of a reference voltage generation circuit.

FIG. 6 is a sectional view showing a memory cell according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

FIG. 8 is an input / output characteristic diagram of a well potential generation circuit of the second embodiment.

FIG. 9 is a block diagram showing a DRAM of the present invention.

FIG. 10 is a block diagram showing a conventional DRAM.

[Explanation of symbols]

 4 Memory cell 13 Internal power supply regulator 21 P-channel MOS transistor 23 Capacitor Vcc External power supply Vint Internal power supply Vw Back bias C Control signal

Claims (3)

[Claims] 1. An internal power supply (Vint) obtained by stepping down an external power supply (Vcc) by an internal power supply regulator (13) is supplied to a memory cell (4), and a back bias is applied to a cell transistor constituting the memory cell (4). A dynamic RAM supplying (Vw), wherein the cell transistor is composed of a P-channel MOS transistor (21) and a capacitor (23), and the back gate of the P-channel MOS transistor (21) has the internal power supply ( A semiconductor memory device characterized in that a back bias (Vw) having a higher potential than Vint) is supplied. 2. The semiconductor memory device according to claim 1, wherein an external power supply (Vcc) is supplied as the back bias (Vw). 3. The back bias (Vw) is supplied from the well potential generating circuit (15) by a potential higher than the internal power supply (Vint) by the threshold value of the P-channel MOS transistor (Tr9). The semiconductor memory device according to claim 1.