JPH0690156A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable acceleration and low energy consumption. CONSTITUTION:A common emitter voltage VE of an ECL current switch 1 is inputted to the base of a discharging transistor Q4 at an output bypass part 3 of an emitter follower circuit 2 in the next step. At the time of dropping an output voltage VO from 'H' to 'L', a discharging current iD is increased and at the time of increasing from 'L' to 'H', the current iD is decreased. Thus, no DC bias circuit exists at an output bias part, and energy consumption is reduced. Further, capacity added to a collector node N2 is reduced, and switching delay is not generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having an ECL current switch.

[0002]

2. Description of the Related Art As shown in FIG. 6, a conventional semiconductor integrated circuit includes an input bipolar transistor Q1 which receives an input voltage VI as a base and a bipolar transistor Q2 which receives a reference reference voltage VR as a base. One emitter is connected to a constant current source IC via a common emitter node NE, and each collector has resistors R1 and R2.
It has an ECL current switch 1 which is connected to a VC power supply via.

Further, the collector of the charging bipolar transistor Q3 which inputs the collector voltage VC1 to its base is connected to the power supply voltage VC which is the highest voltage, and the emitter is connected to the ground potential point GND which is the lowest potential via the resistor R5. , An emitter follower circuit 2b for outputting an output voltage VO1 from an output terminal TO to which this emitter is connected.

Next, the operation of the circuit shown in FIG. 6 will be described.
When the input voltage VI has a higher potential than the reference voltage VR, that is, VI> VR, the input transistor Q1 of the ECL current switch 1 is turned on, and the constant current IC flows into the collector of the transistor Q1. The voltage VC1 becomes "L" level, and the collector voltage VC2 at the node N2 becomes "H" level. Also, VI <V
In the case of R, the collector voltages VC1 and VC2 have opposite levels.

The collector voltage VC1 is input to the base of the transistor Q3 of the emitter follower circuit 2b, and the output voltage VO1 lowered by the base-emitter forward voltage Vf of about 0.8 V is output from the output terminal TO.

When the output voltage VO1 changes from "L" to "H" level, it passes through the transistor Q3 and the terminal T
When the charge is charged between O and GND and changes from "H" to "L", the discharge current IR is passed through the discharge resistor R5 to GND.
Flows.

Recently, as shown in FIG. 7, the output voltage VO
A constant current I that constantly flows the discharge current IR when the value of 1 drops.
There is also proposed an output bypass circuit in which an emitter pull-down circuit is provided instead of R to selectively increase the discharge current only during the time when the output voltage VO1 drops to speed up the output change.

The ECL current switch 1 and the charging bipolar transistor Q3 of the emitter follower circuit 2e are the same as in the conventional example of FIG. 6, but the output bypass section 3 for discharging is used.
b, the constant voltage VB at the connection point of the two series-connected diodes D and the resistor R4 inserted between the power source and the GND is input to the base, and the emitter is connected to the GND via the parallel circuit of the discharge resistor R5 and the capacitor C. It also has a discharging bipolar transistor Q4.

In the steady state, the output terminal TO is connected and a constant current is drawn from the collector of the discharge transistor Q4, but when the output voltage VO1 is lowered, the collector voltage VC1 of the current switch 1 drops and the voltage VC2 rises. In order to do this, the variation of this voltage VC2 is calculated by coupling capacitor C
It is transmitted to the base of the discharge transistor Q4 via C.

At this time, the transistor Q4 has a base-emitter voltage V due to the capacitor C connected to the emitter.
The discharge current iC is increased because BE increases and turns on strongly transiently.
Will increase. For these, I Triple E Journal of Solid State Circuits (IEEE JOURNAL OF SOLID-ST
ATE CIRCUITS) Vol. 24, No. 5,
OCTOBER, 1989. It is described in.

[0011]

In this conventional semiconductor integrated circuit, the constant current value of the emitter follower has to be increased in order to increase the speed, especially the discharge operation at the time of output drop, and the consumption due to this increase. It was not possible to prevent the increase in power.

In another circuit of the conventional example, it is possible to reduce the current except when the output drops, but the collector voltage of the current switch in the high potential region is used to control the emitter follower current. Therefore, a DC bias voltage circuit that superimposes an AC component is required, which has a complicated circuit configuration.

Further, if the input capacitance of the output bypass section added to the collector node becomes large, the signal response becomes dull when the collector output voltage is used for inputting another signal, and therefore the path response of this path is reduced. There is a problem that the delay time increases.

[0014]

In the semiconductor integrated circuit of the present invention, the emitters of a plurality of bipolar transistors whose bases are connected to an input voltage terminal are connected to a common emitter node which is connected to a constant current source. The collector is connected to the power source through the resistor and outputs the collector output voltage, and the collector output voltage is input to the base, the emitter is connected to the output terminal, and the output bypass unit is connected. In a semiconductor integrated circuit including an emitter follower circuit having a charging bipolar transistor connected to a ground potential point via a base, the output bypass unit has a base connected to the common emitter node and a collector connected to the output terminal. ,
It has a bypass transistor whose emitter is connected to the ground potential point via a capacitor, and a discharge N-channel MOS transistor whose gate inputs the other of the collector voltage and whose drain and source are connected in parallel to both ends of the capacitor. Is configured.

Further, in the semiconductor integrated circuit of the present invention, the emitters of the plurality of bipolar transistors whose bases are connected to the input voltage terminal are connected to the common emitter node which is connected to the constant current source, and the collectors are resistive. And an ECL current switch connected to the power supply through the PCL to output a collector output voltage, and one of the collector output voltages is input to the P gate, and the N gate is connected to the common emitter node to output a common drain voltage. First
CMOS inverter, and the other of the collector voltage is P
A second drain having a common drain voltage input to the gate and the common drain voltage input to the N gate, and the common drain connected to the output voltage terminal;
And a level conversion circuit having a CMOS inverter.

[0016]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. The semiconductor integrated circuit of this embodiment has the same ECL current switch 1 as that of the conventional example shown in FIGS.

The emitter follower circuit 2 omits the diode D, the resistor R4, and the coupling capacitor CC of the output bypass section 3b of FIG. 7, connects the base to the common emitter node NE, and connects the discharge resistor R5 connected to both ends of the capacitor C. Instead, it has an output bypass section 3 provided with a discharging N-channel MOS transistor MN1 whose gate is connected to a collector node N2.

Next, the operation of the circuit of FIG. 1 will be described with reference to the waveform chart of FIG. When the input voltage VI rises from “L” to “H” from the time point t0, the input voltage VI is compared with the reference voltage VR set to the intermediate value, and the input transistor Q1 of the ECL current switch 1 is turned from off to on,
2 goes from on to off.

Therefore, the collector resistance R due to the collector current
The voltage drops of 1 and R2 also change, the collector voltage VC2 changes from "L" to "H", and the voltage VC1 changes from "H" to "L". This amplitude is constant current IC and collector resistance R
It is determined by the values of 1 and R2.

The "H" level clamp of the charging transistor Q3 drops due to the potential drop of the collector voltage VC1, and the output voltage VO is caused by the charge discharge current iD of the output bypass section 3.
To "L" level.

The potential of the common emitter NE of the ECL current switch 1 is raised by the input transistor Q1 from the time t1 when VI> VR.

Since the emitter of the discharge transistor Q4 has the capacitor C, the base-emitter voltage VBE instantaneously increases, the transistor Q4 strongly turns on, and a large current iD is drawn from the output terminal TO.

A constant current thereafter flows at a constant current with an impedance determined by the MOS transistor MN1 inserted between the emitter of the transistor Q4 and GND.

When the input voltage VI drops from "H" to "L", since the input transistor Q1 is turned off and the transistor Q2 is turned on at the threshold value of the reference voltage VR, the collector voltage VC1 rises and the charging voltage is increased. A large charging current flows to the output terminal TO by the bipolar transistor Q3 to raise the voltage V0.

During the pulling-up time t3 to t4, the discharging current, that is, the current iD flowing in the output bypass section is small, and the charging current from the transistor Q3 is efficiently used for charging the output to shorten the delay time.

Common emitter voltage V of the current switch 1
Since E drops as the input voltage VI drops, the base-emitter voltage VBE of the charging transistor Q3 decreases, the transistor Q3 momentarily turns off, and the current iD of the output bypass section 3 is cut.

At the same time, the collector voltage VC2, which is the gate voltage of the transistor MN1 between the emitter and GND, also drops at this time, so that the current in the steady state can also be reduced. Here, the capacitance added to the collector node N2 is MO
Since there is only the gate capacitance of the S transistor MN1 and it is extremely small, there is no switch delay.

FIG. 2 (b) shows the time variation of the emitter follower current of this embodiment and the conventional example.
It can be seen that the current peak of No. 2 and the current decrease at the output increasing time points t3 to t4 are effective at the start of the output change because the discharge current iD of the present embodiment is fast.

This is because the discharge current iD is controlled by directly utilizing the common emitter voltage of the current switch 1. Therefore, the collector voltage VC2 is shifted to a lower voltage as in the conventional example shown in FIG. The response speed is faster than when using it later.

Further, since the base bias circuit for the voltage shift of FIG. 7 is unnecessary, the circuit structure is simplified and the chip use area on the semiconductor integrated circuit can be reduced.

FIG. 3 is a circuit diagram of the second embodiment of the present invention. In this example, a resistor RE is inserted between the common emitter node NE of the current switch 1a and the constant current source IC, the common emitter voltage is shifted to the lower side by this resistance value, and the emitter follower circuit 2 is caused by this voltage VEL.
Control the bias current of a.

N channel M is provided between the output terminals TO and GND.
By providing only the OS transistor MN2 and inputting the emitter voltage VEL to its gate, the transistor MN2 is strongly turned on to allow a large discharge current iD to flow when the output voltage VO is “L”, and the output is “H”. Transistor M
N2 is weakly turned on to reduce the current amount iD. This change in current can be performed at a high speed almost at the same time as the change in output, so that it is possible to reduce the current during transition.

This embodiment does not have the instantaneous discharge current increase at the output falling times t1 to t2 unlike the above-mentioned second embodiment and the conventional example shown in FIG. 7, but has the circuit configuration of the conventional example of FIG. Despite such simplification, almost the same circuit area can be used on the chip to achieve high speed and low current consumption, which is highly effective in applications such as large-scale semiconductor integrated circuits.

FIG. 4 is a circuit diagram of a third embodiment of the present invention, in which the input voltage VI of a low amplitude signal such as ECL level is C
This is a case where the output voltage VO of a large amplitude signal such as a MOS level is upconverted.

In the embodiment of the present invention, as shown in FIG. 4, the collector nodes N1 and N2 of the current switch 1 are respectively the base of the charging bipolar transistor Q3 operable by the signal voltage in the high voltage region and the N-channel MOS transistor MN1. Has been entered into the gate.

Since the common emitter NE of the current switch 1 has an operating point in a lower voltage region than the intermediate voltage, it is connected to the gate of the P-channel MOS transistor MP1. These transistors Q3, MP1, and MN1 are connected in series between VC and GND in order, and the CMOS transistor C
The common drain of M1 was used as the output terminal TO.

When the input voltage VI is "L", VC1 = V
Since C and VE are at "L" level, the transistors Q5 and
MP1 is strongly turned on, increasing the output voltage VO. VC
2 is "L" to reduce the bypass capability of MN1.

When the input voltage VI is "H", VC2 = VC, MN1 is strongly turned on, and the output voltage VO is lowered. The emitter voltage VE becomes "H", and the MN1 lowers the bypass ability.

Although the MOS transistor MP1 has a lower response capability than other bipolar or N-channel MOS transistors, the common emitter voltage VE has a collector voltage VC.
1, the response is faster than VC2, so high speed can be secured.
Further, since the CMOS transistor CM1 has an on-current capability ratio of one digit or more at "H" and "L", the amplitude of the output voltage VO can be set large.

In this example, since the transistor cannot be turned on and off completely, the "H" and "L" levels of the output voltage VO are (VC-about 1V), + about 0.5V. Full V
In order to obtain output amplitudes up to C and GND, it is necessary to completely turn on / off the transistors in the CMOS configuration.

A circuit diagram of another embodiment thus improved is shown in FIG. In this example, one of the collector resistors R1 and R2 of the current switch 1b is connected to the common offset resistor R
3 to the power supply VC.

VC2 and emitter voltage VE are input to the gate inputs of the CMOS inverter CM2 composed of the MOS transistors MP2 and MN2, and the common drain thereof is connected to the gate node NG to output the gate voltage VG.

Then, the MOS transistors MP1 and MN1
The collector voltage VC1 and the gate voltage VG are input to the gate of the CMOS inverter CM1 including the CMOS inverter CM1 and the complete CM from the common drain D connected to the output terminal TO.
The OS level output voltage VD is output.

Here, by matching the offset voltage determined by the resistor R3 with the threshold voltage of the P-channel MOS transistors NP1 and NP2, the transistor M
P1 and MP2 can be completely turned on and off.

At the same time, the common-emitter voltage VE, which is in phase with the collector voltage VC2 and operates at high speed, changes the impedance of the transistor MN2 at high speed, so that the gate voltage VG operates in antiphase with the input voltage VI. Since "L" of the gate voltage VG drops to GND, the transistor N1 is completely turned off, and an output waveform of "H" voltage = VC and "H" voltage = GND is obtained in the same phase as the input voltage VI.

[0046]

As described above, according to the present invention, the discharge current amount of the emitter follower current is controlled by using the common emitter voltage of the ECL current switch by the bipolar transistor. Therefore, the delay of the emitter follower output voltage is delayed by a simple circuit. We were able to effectively reduce the time and power consumption.

Further, since this common emitter voltage is used as the control signal of the ECL-CMOS level conversion circuit in the next stage of the current switch, there is an effect that high speed operation can be realized with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

2 (a) and 2 (b) are waveform diagrams of respective signals and an emitter follower current waveform diagram for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of an example of a conventional semiconductor integrated circuit.

FIG. 7 is a circuit diagram of another example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 to 1b ECL current switch circuit 2 to 2b emitter follower circuit 3.3a output bypass section 4, 4a level conversion circuit C capacitor IC constant current source iD discharge current MN1, MN2 N channel MOS transistor MP1, MP2 P channel MOS transistor N1, N2 Collector node NE Common emitter node NG Gate node Q1, Q2 Input bipolar transistor Q3 Charging bipolar transistor Q4 Discharging bipolar transistor R1, R2 Collector resistor R3 Offset resistor TI input terminal TO output terminal VC1, VC2 Collector voltage VE Common emitter voltage VO Output voltage VR reference voltage

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 17/66 C 9184-5J

Claims (2)

[Claims] 1. An emitter of each of a plurality of bipolar transistors whose bases are connected to an input voltage terminal is connected to a common emitter node which is connected to a constant current source, and a collector is connected to a power supply via a resistor. And an ECL current switch that outputs the collector output voltage,
A semiconductor integrated circuit including: an emitter follower circuit having a charging bipolar transistor having one of the collector output voltages input to a base, an emitter connected to an output terminal, and an output bypass unit connected to a ground potential point. , The output bypass unit has a base connected to the common emitter node, a collector connected to the output terminal, an emitter connected to the ground potential point via a capacitor, and a gate connected to the collector voltage. Discharge N-channel MO with the other input and the drain and source connected in parallel across the capacitor
A semiconductor integrated circuit having an S transistor. 2. An emitter of each of a plurality of bipolar transistors whose bases are connected to an input voltage terminal is connected to a common emitter node which is connected to a constant current source, and a collector is connected to a power supply via a resistor. Together with an ECL current switch for outputting a collector output voltage, and one of the collector output voltage is input to the P gate and N
A first CMOS inverter having a gate connected to the common emitter node to output a common drain voltage; the other of the collector voltages is input to a P gate, the common drain voltage is input to an N gate, and the common drain is an output voltage. And a level conversion circuit having a second CMOS inverter connected to a terminal.