JPH069029B2 - Digital signal processing processor - Google Patents

Description

The present invention relates to a digital signal processor (hereinafter, DS).
(Referred to as P).

(Prior Art) A DSP is a device that performs a predetermined digital operation on a signal to be processed that has been converted from an analog signal to a digital signal. The advantages of digital signal processing include higher precision, easier nonlinear processing, multiplexing processing, adaptive control, etc., improved stability against temperature changes and aging changes, and simplified manufacturing and inspection processes. It can be realized.

Conventionally, as a technique in such a field, for example, there is one described in the following documents.

Reference 1; JP-A-56-101266. Reference 2; "MICROSYSTEM COMPONENTS HANDBOOK", 1 (195
4) Intel Corporation (US) P.4-52 to 4-75 The DSP described in Reference 1 is a read-only memory for storing programs, a data memory for storing data, a shift circuit, an adder / subtractor, and an accumulator. It is equipped with registers and the like. A fixed-point format is adopted as an internal operation data format, and a parallel type multiplication circuit is incorporated in order to strengthen the operation capability of the product-sum operation necessary for the digital signal processing operation.

Further, Document 2 describes a technique of a numerical arithmetic processor 80287 (manufactured by Intel Corporation) which adopts a floating point format.

(Problems to be Solved by the Invention) However, the conventional DSP has the following problems (1) and (2).

(1) In the DSP of Document 1, when the time-varying operation of the coefficient is required for adaptive control or the like, the read-only memory for the coefficient cannot update the coefficient at any time, so the memory cannot be used. Therefore, the number of steps of the program is increased, and the storage area of the data memory is wasted.

Furthermore, since this type of DSP uses the fixed-point format as the internal arithmetic data format, it is necessary to perform an operation such as converting the processed data into the [+1, -1] section, and the decimal point position of the data. There was a problem that they had to be constantly managed.

For example, in the operation of the non-recursive digital filter, in order to add a large number of multiplication results, the decimal point position is shifted to the right by N bits from the current position in consideration of overflow, etc., and then returned to the left by N bits again after the operation. I was doing an extra operation. This shift processing is performed because the fixed-point arithmetic format has a narrow dynamic range. Further, there is a problem that many correction operations for accumulating errors and deterioration of accuracy are required.

(2) In order to widen the dynamic range, reference 2
Floating point format is adopted in the DSP of the above, but as described on page 4-58 of the same document 2, addition 14
It requires processing times of μs, multiplication 19 μs (single precision), and 27 μs (double precision). Therefore, when digitally processing signals in the voice band 0 to 4 kHz, 8 kHz
Since sampling is adopted, only a few instructions can be executed within the time of 125 μs, and the arithmetic operation capability is not yet sufficient for performing digital signal processing in real time (real time). Therefore, it is conceivable to increase the circuit scale to improve the arithmetic operation capability, but in the case of a one-chip integrated circuit, there is a new problem that it becomes difficult.

The present invention has the problems that the above-mentioned prior art has a problem that it does not have a high speed suitable for executing digital signal processing in real time, and that if it has a high speed, integration on a single chip is possible. It is an object of the present invention to solve a difficult point and to provide a DSP which can be easily integrated on one chip and has a high processing speed.

(Means for Solving Problems) In order to solve the above problems, the first invention controls a read first memory for storing a program and an address of the first memory in a DSP. A first address control unit, a second memory which is controlled by the program and can write and read data, and a second address control unit which controls an address of the second memory,
A memory write register which takes in one of the data of the second memory and the data of the internal data bus as an input and outputs the data to the second memory and the internal data bus; A memory read register that holds one of the data in the memory and the data in the internal data bus is provided.

Furthermore, a multiplication circuit that multiplies the contents of the memory reading register as a multiplier and a multiplicand, a multiplication register that holds the output data of the multiplication circuit, an accumulation register that accumulates the operation result data, and the memory reading. An arithmetic logic operation circuit that takes in the contents of two registers designated by the program among the input registers, the multiplication registers, and the accumulation registers as input data and performs arithmetic logic operation on those input data, It is provided.

In the second invention, the first read-out storing the program is provided.
Memory, a first address control unit for controlling an address of the first memory, two-sided second and third memories controlled by the program and capable of writing and reading data, and the second and third memories. A second address control unit for controlling an address of the third memory, and one of the data of the second and third memories and the data of the internal data bus is taken as an input, and the data is taken as the second data. , A third memory and a memory write register for outputting to the internal data bus, and 2 read from the second and third memories.
A first memory read register that holds one of the two data, and a second memory read register that holds one of the third memory data and the internal data bus data. Is prepared.

Further, a multiplication circuit that multiplies the contents of the first and second memory read registers as a multiplier and a multiplicand and outputs the result as double length data, and first and second single lengths that respectively hold the double length data. A register, first and second accumulation registers for accumulating single-length data representing a calculation result, the first and second memory reading registers, the first and second single-length registers, and An arithmetic logic operation circuit that takes in the contents of two registers designated by the program as input data among the first and second accumulation registers and performs an arithmetic logic operation on those input data is provided. Has been.

(Operation) According to the first and second inventions, since the DSP is configured as described above, the memory write register, the memory read register, and the input data selection means on the ALU input side are:
It has a function of selecting data input to each component and changing signal processing inside the DSP by a program stored in the first memory. Therefore, various types of adaptive signal processing can be supported, and integration on one chip is facilitated.

Further, the memory writing register, the memory reading register, and the input data selecting means on the ALU input side have the function of optimizing the data processing procedure and reducing the number of steps required for the data processing. Therefore, if conventional
Although only one process can be performed per clock cycle, data is temporarily stored in these write register and memory read register and used in the process of the next step to execute a plurality of processes in parallel. It has a function. Moreover, the memory write register and the memory read register are arranged such that the number of processing steps handled by these registers is substantially uniform. Therefore, in the processing of the memory, the multiplication circuit, the ALU, etc., when the processing shifts to the next step (for example, memory → multiplication circuit, multiplication circuit → ALU, etc.), the next step processing which is processed in parallel is completed. Aim to reduce unnecessary waiting time. As a result, the processing speed of the DSP can be increased. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of a main part of a DSP (digital signal processor) showing an embodiment of the present invention.

This DSP has an internal data bus 1 controlled by an internal data bus controller (not shown), and a control unit, a storage unit, a calculation unit and an input / output unit are connected to this internal data bus 1.

The control unit and the storage unit include a first memory (for example, ROM) 10 for reading that stores a program, a first address control unit 11 that controls an address of the ROM 10, and an external control memory for the address control unit 11. It has an external data bus terminal 13 connected via a data bus 12 and an external address bus terminal 15 connected to the address control section 11 via an external control memory address bus 14. Further, the control unit and the storage unit have second and third memories (for example, RAM) 2 capable of writing and reading data.
0,21 second for controlling the address of the RAM 20,21
Address control unit 22, memory writing register 23,
First and second memory read registers 24, 25 and signal selecting selectors 26, 27, 28 are provided.

The ROM 10 is a memory that sends and receives signals to and from the address control unit 11, reads out a program command at an address designated by the address control unit 11, and outputs the program command to the internal data bus 1 or the like. The address control unit 11 is a circuit that sends and receives data to and from the internal data bus 1 and controls the address of the ROM 10. The external data bus terminal 13 and the external address bus terminal 15 connected to the address control unit 11 are for connecting an external control memory (for example, an external ROM storing a program), and the read address of the external ROM is used. It has a function of outputting and inputting the read result as data. These bus 1
2, 14 and terminals 13 and 15 are used for the internal ROM 10 when the internal ROM 10 is not used or when debugging a program.
It is used when 10 cannot be used.

The RAMs 20 and 21 write the data in the memory write register 23 to an address designated by the address control unit 22 and read the written data to select the selectors 27 and 2.
It is a circuit to give to 8. The selector 26 connected to the input side of the memory write register 23 is connected to the internal data bus 1
It is a circuit that selects one of the above data or the read data of the RAMs 20 and 21 and supplies it to the memory write register 23. The memory write register 23 temporarily holds the output data of the selector 26 and stores it in the RAM 2
0, 21 and a circuit applied to the internal data bus 1. The selector 27 is one of the read data of the RAM 20 or 21.
The selector 28 is a circuit for selecting one of the read data of the RAM 21 and the data on the internal data bus 1 and supplying it to the memory reading register 25.
The memory read registers 24 and 25 are connected to the selectors 2 respectively.
This is a circuit for temporarily holding the output data of 7, 28 and outputting the data in the floating point format to the arithmetic unit.

The arithmetic unit includes a parallel type multiplication circuit 30 and first and second single-length registers 3 which are multiplication registers for holding a multiplication result.
1, 32, first and second accumulation registers (accumulators) 33 and 34, selectors 35 and 36, and an arithmetic logic operation circuit (hereinafter referred to as ALU) 37.

The multiplication circuit 30 inputs the output data in the floating-point format in the memory read registers 24 and 25, multiplies the two inputs as a multiplier and a multiplicand, and outputs the multiplication result as first double-length data in normalized floating-point format. , A circuit for giving to the second single length registers 31, 32. The first and second single-length registers 31 and 32 each temporarily hold the output data of the multiplication circuit 30, and among them, the first single-length register 3
Reference numeral 1 designates retained data as an internal data bus 1 and a selector 35.
The second single-length register 32 stores the held data in the selector 3
5 is a circuit to give to each. The first and second accumulation registers 33 and 34 are circuits for accumulating operation results, outputting the accumulation results as floating-point format data, and giving the same to the selector 36. The selector 35 includes the memory read registers 24 and 25 and the single length registers 31 and 3.
A circuit for selecting one of the four output data in the floating point format in 2 and supplying it to the ALU 37 as the first input data, the selector 36 is the memory read register 2
5 and one of the three output data in the floating point format in the accumulation registers 33 and 34 and select it from the ALU.
37 is a circuit which is given to 37 as the second input data. AL
A U37 is a circuit for performing an operation on the first and second input data, outputting the operation result as data in a normalized floating point format, and giving it to the accumulation registers 33 and 34 and the internal data bus 1.

The input / output unit is a circuit that is controlled by the control unit to input / output data, and includes an input register 40 for inputting external data to the internal data bus 1 and an output register for outputting data on the internal data bus 1 to the outside. 41, the input / output register 4
0 and 41 connected to the internal data bus 42 via the external data bus 42, external memory address registers 44 and 45 connected to the internal data bus 1, and external data memory addresses to the address registers 44 and 45. An external address bus terminal 47 connected via a bus 46 and general-purpose input / output flags 48, 49 connected to the internal data bus 1 are provided.

Of the two address registers 44 and 45, one address register 44 functions as a destination (destination) register and the other address register 45 functions as a source (source) address register, and an external memory (for example, When a RAM) is used, it has a function of designating an address for reading and writing the external RAM. Therefore, the external data bus terminal 47 connected to the address register 44 is connected to the internal RAMs 20 and 21.
An external RAM is connected when the memory capacity is insufficient. Further, the input / output flags 48, 49 have a function of controlling the transfer of data to / from a circuit external to the DSP during the repeated operation of the arithmetic processing.
The usage of 49 is determined by the communication control procedure with the external circuit.

The operation when performing the second-order cyclic digital filter operation as shown in FIGS. 2 and 3 using the DSP configured as described above will be described.

(A) Description of FIG. 2 and FIG. 3 As a method of designing a digital filter, a method of converting a design value of an analog filter into a digital filter is used, and a filter specification in an analog area is f ₀ = 1 KHz of a bandpass characteristic. , Q = 5, A = 0 dB (1) However, a known matching Z transformation is performed on ω ₀ = 2Πf ₀ . Then, the general formula of the Z region is However, Z = e ^jWT T; can be represented by a sampling period (= 125 μs), and its coefficient value is a ₀ = 0.1343065 a ₁ = -0.1343065 b ₁ = -1.312528 b ₂ = 0.854636 (4) Become.

FIG. 2 shows a filter configuration diagram of the Z region corresponding to the equation (3).

The filter of FIG. 2 has an input terminal 100 for inputting an input signal X (Z) and an output terminal 10 for outputting an output signal Y (Z).
1, a terminal 102 for inputting a coefficient −b ₁ , a terminal 103 for inputting a coefficient −b ₂ , a terminal 104 for inputting a coefficient a ₀ , a terminal 105 for inputting a coefficient a _1, and a unit delay processing time Z ^{−1 of} one clock Delay circuits 106 and 107, and a multiplier 1
08,109,110,111 and adders 112,1
It is composed of 13.

In this type of filter, the input signal X (Z) is processed by the adder 112 corresponding to the calculation of the denominator of Expression (3), and the adder 113 corresponds to the calculation of the numerator of Expression (3). Output signal Y from the output terminal 101.
Get (Z).

The arithmetic expression when the filter operation of FIG. 2 is processed by the DSP is W (Z) = X (Z) -b ₁ Z ^-1 W (Z) -b using the filter internal state signal W (Z). ₂ Z ^-2 W (Z) ・ ・ ・ (5) Y (Z) ＝ a ₀ W (Z) + a ₁ Z ^-1 W (Z) ・ ・ ・ (6) Therefore, the filter coefficient a _{0 of the} equation (4),
a ₁ , b ₁ , b ₂ whose absolute value exceeds ₁ (b ₁ )
Therefore, when the arithmetic operation is performed in the fixed-point data format, the coefficient b ₁ is divided, the equation (5) is transformed into the following equation (7), and the arithmetic operation is performed.

W (Z) ＝ X (Z) ＋ (-b ₁ +1) Z ^-1 W (Z) -Z ^-1 W (Z) -b ₂ Z ^-2 W (Z) ・ ・ ・ (7) This ( FIG. 3 is a filter configuration diagram showing the processing contents of equation 7). Compared to the one shown in FIG. 2, the one shown in FIG. 3 has an input terminal 114 for inputting a coefficient −1 and a multiplier 115, and has a four-input adder 116 instead of the three-input adder 112. Since it is provided, the multiplication processing and the addition processing are each increased once, and the processing is increased by only two steps as a whole.

Therefore, in the following, the processing contents of FIG. 2, that is, (5),
The equation (6) is converted into the DS of FIG. 1 by using the floating point data format.
The operation realized by P will be described.

(B) Processing operation of FIG. 2 First, based on the program stored in the ROM 10 of FIG. 1, the address control unit 11 reads the filter coefficients a ₀ , a ₁ , -b ₁ , -b ₂ in the ROM 10. After determining the memory address value in the address control unit 22, the RAM2
It writes the filter coefficient _{-b 1, -b 2, a 0} , a 1 using each to the address value of the first register 23. For example, as shown in the memory map of FIG. 4, the filter coefficients −b ₁ , −b ₂ , a ₀ , a ₁ are written in the addresses 128, 129, 130, 131 of the RAM 21, respectively. Similarly, for example, addresses 0, 1 and 2 of the RAM 20 are used as input / output temporary storage areas of the delay circuits 106 and 107 in FIG. 2, respectively, and (5) and (6) are assigned to the addresses 0, 1 and 2, respectively. Data value W (Z), Z ⁻¹ W in the formula
^Write (Z), Z ⁻² W (Z).

Hereinafter, the operations of the first step (1) to the ninth step (9) are executed.

(1) First step Since the input data X (Z) of the input register 40 is usually fixed point data, the input data X (Z) is registered in the register 2 so that it becomes the floating point normalized data.
5, and sets the normalization constant (scaling constant) specified by the program of the ROM 10 in the register 24, and then the two data in the registers 24 and 25 are set in the ALU3.
It is converted into normalized floating point data in 7 and set in the register 33.

(2) Second Step The filter coefficient −b ₂ in the RAM 21 is read out and set in the register 25, and the output Z ⁻² W (Z) of the delay circuit 107 stored in the RAM ₂₀ is read out and the register 2 is read out.
Set to 4.

(3) Data in the third step register 24, 25 -b ₂ , Z ^-2 W (Z)
Is multiplied by the multiplication circuit 30 and the multiplication result −b ₂ × Z ⁻²
W (Z) is set in the single length register 31, and each RA
The next filter coefficient -b _{1 in} M21, 20 and the delay circuit 1
The output Z ⁻¹ W (Z) of 06 is read and set in each register 25, 24.

(4) Fourth Step The following four items (4) (i) to (iv) are executed in parallel.

(4) (i) The data -b ₁ in each register 25, 24 and Z ^-1 W (Z) are multiplied by the multiplication circuit 30, and the multiplication result -b ₁ × Z ^-1 W (Z) is a single length. Store in register 31.

(4) (ii) The multiplication result −b ₂ × Z ⁻² W (Z) held in the single length register 31 is read out and input to the ALU 37 via the selector 35, and the data X (Z in the register 33 is read. ) Is input to the ALU 37 via the selector 36, and the ALU 37 performs a subtraction process of X (Z) -b ₂ × Z ⁻² W (Z) and sets the subtraction result in the register 33.

(4) (iii) Filter coefficient a in each RAM 21, 20
₁ and the output Z ⁻¹ W (Z) of the delay circuit 106 are read and set in the registers 25 and 24.

(4) (iv) The data Z ⁻¹ W (Z) in the register 24 is transferred to the register 23 via the selector 36, and the RAM 2
The address control unit 22 is program-controlled so that the address of 0 becomes 2, and the writing process is performed at the address 2. By this writing process, the delay process of the delay circuit 107 is performed, and the data of Z ⁻² W (Z) is updated.

(5) Fifth Step The following three items (5) (i) to (iii) are executed in parallel.

(5) (i) The data X (Z) −b ₂ × Z ⁻² W (Z) stored in the register 33 is read and input to the ALU 37, and the data −b held in the single length register 31 is read. ₁ × Z ⁻¹ W (Z) is input to the ALU 37, the right side of the expression (5) is subtracted by the ALU 37, and the subtraction result is stored in the internal data bus 1
Also, it is stored in the register 25 via the selector 28.

(5) (ii) Multiplication a ₁ × Z ⁻¹ W (Z) of the data a ₁ , Z ⁻¹ W (Z) held in the registers 25, 24
Is performed by the multiplication circuit 30, and the multiplication result is stored in the single length register 3
Store in 1.

(5) (iii) The filter coefficient a ₀ is read from the RAM 21 and set in the register 24.

(6) Sixth Step The processes of the following two items (6) (i) and (ii) are executed in parallel.

(6) (i) Data a held in the registers 25 and 24
_The multiplication circuit 30 performs multiplication a ₀ × W (Z) of ₀ , W (Z), and sets the multiplication result in the single length register 31.

(6) (ii) The data a ₀ × W in the single length register 31
(Z) is passed through the ALU 37 and set in the register 34.

(7) Seventh Step The data a ₀ × W (Z) in the single length register 31 is read and input to the ALU 37, and the data a ₁ × W ⁻¹ W (Z) in the register 34 is written to the ALU 37. It is input, and the addition processing of the right side of the equation (6) is performed in the ALU 37, and the addition result is set in the register 33.

(8) Since the addition result of the expression (6) in the eighth step register 33 is floating point type data, format conversion is performed to fixed point data suitable for use by an external D / A converter or the like. To do this, the exponent offset value for conversion is stored in ROM1.
0 to register 2 through internal data bus 1
Set to 5.

(9) The operation result of the seventh step held in the ninth step register 33,
The data of the eighth step held in the register 25 is set to A
It is input to the LU 37, the floating point data is converted by the ALU 37 to fixed decimal point data, and the conversion result is set in the output register 41 through the internal data bus 1.

In this 9th step, 2
This means that the calculation of the next cyclic digital filter has been completed. Thereafter, similarly, the next sample data is input to the input register 40 from the external data bus terminal 43, and the above-mentioned first to ninth steps are performed on the input data,
The operation of setting the processing result in the output register 41 is repeated. Such repetitive operation is
It is controlled by the data with the external circuit transmitted / received via the input / output flags 48 and 49.

(C) Other circuit operation in FIG. 1 The operation of the single length register 32 not used in the above (B) is as follows. In the multiplication circuit 30, the mantissa part of the input data has a single length, but the mantissa part of the output data has a double length. Therefore, the upper part of the output data is stored in the first single-length register 31, and the lower part is stored. It is stored in the second single length register 32. Therefore, in the floating point data, the upper single mantissa part and the exponent part of the multiplication result are usually set in the first single length register 31 and used, and the second single length register 32 performs the double length operation on the fixed point data. Used in case.

(D) Advantages of this embodiment As described in the fourth step, the RAM 20, 2
Reading of 1 to 2 data, multiplication processing, RAM2
Simultaneous processing of 4 items of writing to 0 and arithmetic logic operation processing can be performed. Therefore, it is possible to realize an efficient DSP with extremely high parallelism of hardware for the processing of multiplication, addition, and delay, which are the basics of digital signal processing operations, and because the redundancy of the circuit configuration is extremely low, it is possible to use one chip. Can be easily integrated.

Moreover, by adopting a pipeline register, it is possible to adopt a configuration in which a floating-point operation process is executed in one instruction of 100 ns. Therefore, for example, the processing of 125 μs / 100 ns = 1250 steps can be performed on the audio signal of 8 KHZ sampling for each sampling period, and the computing ability for real-time digital signal processing is significantly improved.

Further, since the memory write register 23, the memory read registers 24 and 25, and the input data selection means (selectors 35 and 36) on the input side of the ALU 37 are provided, the data input to each component of the DSP is selected. It becomes possible, and it becomes D by the program stored in ROM10.
The signal processing inside the SP can be changed. As a result, the DSP of this embodiment can be applied to various types of adaptive signal processing and can be easily integrated on one chip.

Various types of adaptive signal processing include, for example, the following.

(A) Both the data stored in the first memory read register 24 and the data stored in the second memory read register 25 do not pass through the multiplication circuit 30,
By directly inputting to the ALU 37, calculation processing such as absolute value calculation that does not require multiplication becomes possible.

(B) The data stored in the RAM 21 is input to the first and second memory reading registers 24 and 25, respectively,
By inputting the contents into the multiplication circuit 30, respectively, the number of steps required in the prior art can be reduced, and the square calculation can be easily executed.

(C) The RAM 20 and the RAM 21 can be connected in series to double the memory capacity available for the filtering process.

The present invention is not limited to the illustrated embodiment, and various modifications can be made.

(Effect of the Invention) As described in detail above, according to the first and second inventions, since the memory write register, the memory read register, and the input data selection means on the ALU input side are provided, the DSP is provided. The data input to each of the components can be selected, and the signal processing in the DSP can be changed by the program stored in the first memory.
As a result, the DSP of the present invention can be applied to various types of adaptive signal processing and can be easily integrated on one chip.

Furthermore, since the memory write register, the memory read register, and the input data selection means on the ALU input side are provided, the data processing procedure can be optimized and the number of steps required for the data processing can be reduced. . In the past, only one process could be performed per clock cycle, but by temporarily storing data in the memory write register or memory read register and using it in the process of the next step, a plurality of The processes can be executed in parallel. In addition, the memory write register and the memory read register are arranged so that the number of processing steps handled by the registers is substantially uniform, so that the memory, the multiplication circuit, and the AL are arranged.
In processing such as U, when shifting to the processing of the next stage (for example, memory → multiplication circuit, multiplication circuit → ALU, etc.), there is a wasteful waiting time until the processing of the next stage which is processed in parallel is completed. Can be reduced. Therefore, the processing speed of the DSP can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of the essential parts of a DSP (digital signal processor) showing an embodiment of the present invention, FIGS. 2 and 3 are filter block diagrams, and FIG. 4 is the memory map of FIG. is there. 1 ... Internal data bus, 10 ... ROM, 11 ... Address control unit, 20,21 ... RAM, 22 ... Address control unit, 23 ... Memory writing register, 24,25
...... Memory read register, 30 …… Multiplier circuit, 3
1, 32 ... Single length register, 33, 34 ... Accumulation register, 37 ... ALU.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Nomura 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) Reference JP-A-59-47837 (JP, A) JP-A-SHO 60-182815 (JP, A)

Claims (2)

[Claims] 1. A first memory for reading that stores a program, a first address control unit that controls an address of the first memory, and a second memory that is capable of writing and reading data controlled by the program. Memory, a second address control unit for controlling the address of the second memory, and one of the data of the second memory and the data of the internal data bus is taken as an input, and the data is fetched as A memory write register for outputting to a second memory and the internal data bus; a memory read register for holding one of the data of the second memory and the data of the internal data bus; and the memory read. A multiplication circuit for multiplying the contents of the register for multiplication as a multiplier and a multiplicand, a multiplication register for holding output data of the multiplication circuit, An accumulation register for accumulating the data of the arithmetic result, and the contents of two registers designated by the program among the memory read register, the multiplication register and the accumulation register are taken as input data, A digital signal processor, comprising: an arithmetic logic operation circuit that performs an arithmetic logic operation on the input data. 2. A first memory for reading which stores a program, a first address control section which controls an address of the first memory, and two surfaces which are controlled by the program and can write and read data. Second and third memories, a second address control unit that controls addresses of the second and third memories, and one of the data of the second and third memories and the data of the internal data bus. Of the two data read from the second and third memories, a memory write register that takes in one data as an input and outputs the data to the second and third memories and the internal data bus And a second memory read register that holds either one of the data in the third memory and the data in the internal data bus. A register, a multiplication circuit that multiplies the contents of the first and second memory read registers as a multiplier and a multiplicand, and outputs the result as double-length data; first and second single units that respectively hold the double-length data. The first register that accumulates the long register and the single length data that represents the operation result
A second accumulation register; the first and second memory reading registers;
Arithmetic for fetching as input data the contents of two registers designated by the program, of the second single-length register and the first and second accumulation registers, and performing arithmetic logic operation of those input data A digital signal processor, comprising: a logical operation circuit.