JPH069207B2 - Lateral transistor - Google Patents

Description

The present invention relates to a lateral PNP transistor incorporated in an IC, and more particularly to a lateral PNP transistor suitable for use in an IC for equipment using a low power supply voltage.

(B) Conventional Technology Conventionally, as a lateral transistor incorporated in a semiconductor integrated circuit, for example, there is one described in Japanese Patent Application Laid-Open No. 59-159566.

That is, as shown in FIGS. 5A and 5B, a P-type semiconductor substrate (1)
The N-type epitaxial layer (2) formed above, the N ⁺ -type buried layer (3) provided on the surface of the substrate (1), and the epitaxial layer (2) surrounding the buried layer (3). Penetrating P ⁺ type isolation region (4)
And an island region (5) separated into islands by the separation region (4),
P-type emitter regions spaced apart on the surface of the island region (5)
(6), P type collector region (7) and N ⁺ type base contact region (8), and oxide film (9) covering the epitaxial layer (2)
And an electrode (10) which makes ohmic contact with the emitter region (6), the collector region (7) and the base contact region (8) through the electrode holes of the oxide film (9). The island region (5) is the base, the emitter region (6) and the collector region
The surface of the island region (5) between (7) and (7) becomes a substantial base that becomes active as a transistor.

In such a transistor, since the collector region (7) is formed so as to surround the periphery of the emitter region (6), the minority carriers (holes) injected from the emitter region (6) are excellent in catching efficiency and active. It can operate at high h _FE in the region.

(C) Problems to be Solved by the Invention However, since the conventional lateral PNP transistor has a poor rise characteristic of the collector current I _C , the collector-emitter voltage V _{CE of the} transistor is about 0.7 V or less and the base
There is a drawback that the saturation voltage V _CE (sat) is large in a low voltage region where the collector junction is forward biased. for that reason,
For example, when used in an IC circuit in which a 1.5V or 3.0V battery is used as a power supply voltage, the circuit is forced to operate in the low voltage region and the saturation voltage V _CE (sat) at that time is high. There is a drawback that the voltage reduction characteristics deteriorate.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and a P-type emitter region (16) and a collector region are formed on the surface of the island region (15) serving as a base.
In a lateral PNP transistor having (17) spaced apart from each other, the junction lengths of the base-emitter junction and the base-collector junction, which are active as transistors, are set to be substantially equal to each other, and the emitter region (16) and the collector region (17) are Is characterized in that an N ⁺ type guard ring region (18) is provided in contact with these regions so as to collectively enclose them.

(E) Action When the PNP transistor operates, holes are injected from the emitter to the base and back holes from the collector to the base at the same time in the transistor.
The difference in the injection amount of both holes becomes the collector current.

Here, when a sufficient potential difference is applied between the collector and the emitter and the base-collector junction is reverse biased, the reverse injection amount of holes from the collector to the base is extremely smaller than the injection amount of holes from the emitter to the base. Because it is a little
A large collector current I _C can flow. Also, in this state, the amount of back-injection of electrons from the base to the collector is extremely small, so the base current is small and the transistor is high.
Can operate in h _FE state.

However, if the potential difference between the collector and the emitter is not sufficient and the potential of the collector rises relatively and the base-collector junction becomes forward biased, the amount of holes injected from the emitter to the base is increased from the collector to the base. Since the reverse injection amount of holes increases rapidly, the flow I _C is drastically reduced at the collector.

In the conventional lateral PNP transistor of FIG. 5, the emitter region (6) is surrounded by the collector region (7), so that the minority carriers (holes) injected from the emitter region (6) are excellent in catching efficiency. If the base-collector junction is sufficiently reverse-biased, it shows high h _FE , but in the situation where the base-collector junction is forward-biased as described above, the efficiency of hole injection from the emitter to the base is higher than the efficiency of hole injection from the collector to the base. since towards opposite the hole injection efficiency will win to, poor rising characteristic of I _C, V _CE in this area (sat)
Will become large.

On the other hand, in the lateral PNP transistor of the present invention, the base-emitter junction and the base-collector junction have the substantially equal junction lengths, so that the base-collector junction is maintained while maintaining a certain high h _FE in the active region. In the region where the forward bias is applied, the efficiency of hole injection from the emitter to the base and the efficiency of hole injection from the collector to the base are approximately equal, and therefore the collector current flows from the emitter to the collector to a region where V _CE is considerably lower than before.
Since I _C can flow, the saturation voltage V _CE (sat) at that time
Can be made quite small.

(F) Example Hereinafter, the present invention will be described in detail with reference to the drawings.

1A and 1B are a plan view and a cross-sectional view taken along the line AA of a lateral PNP transistor according to the present invention.

As shown in FIGS. 1A and 1B, an N-type epitaxial layer (12) formed by stacking on a P-type semiconductor substrate (11) and a substrate (1
1) The N ⁺ type buried layer (13) buried on the surface and the P ⁺ type isolation region (14) penetrating the epitaxial layer (12) so as to surround this buried layer (13) The island region (15) separated into islands by the region (14), the P-type emitter region (16) formed on the surface of the island region (15), and the emitter region (16) facing each other and separated from each other. Formed P-type collector region (17) and emitter region (1
6) and an N ⁺ guard ring region (18) formed so as to surround the collector region (17), an oxide film (19) covering the surface of the epitaxial layer (12), and a contact opened in this oxide film (19) It is composed of an electrode (20) that makes ohmic contact with each region through a hole, and a collector region (17) is formed as an emitter region (16) in the same shape and size to form a base-emitter junction that is active as a transistor. The junction length of the base-collector junction is made substantially equal. The guard ring region (18) is shared as a contact for the base island region (15), and is formed in a ring shape to prevent leakage current from the emitter region (16) and the collector region (17) to the isolation region (14). Has been formed. At this time, the high concentration carding region (18) comes into contact with each region to deteriorate the breakdown voltage, but there is no problem if it is used at a low power supply voltage as in the present invention. Further, in this embodiment, in order to almost completely prevent the leakage current to the isolation region (14), the guard ring region (18) is formed as a diffusion region reaching from the surface of the island region (15) to the buried layer (13). However, the collector contact region (8) of FIG. 5A is shallower than this.
It may be formed in the same diffusion region as.

The Laral PNP transistor formed in this way is
Since the junction length of the base-collector junction with respect to the base-emitter junction is shorter than that of the conventional one, the efficiency of reverse injection of holes from the collector to the base when the base-collector junction is forward biased is small. Therefore, even if the same forward bias is applied, the present invention has a smaller reverse injection amount of holes from the collector to the base with respect to the injection amount of holes from the emitter to the base. _{More C} can be made to flow, and the saturation voltage V _CE (sat) can be relatively lowered. Method of shortening the bonding length of the collector-base junction with respect to the emitter-base junction to promote this step is also considered, but are not preferred because the h _FE of the active region becomes impossible to take.

2A and 2B show the transistor characteristics of the invention of FIG. 1 and the conventional one of FIG. 5, respectively. As is clear from the figure, since the present invention has an excellent I _C rising characteristic, V _CE = 50 [m when the conventional one is Ib = 1 [μA].
_However , in the present invention, when Ib = 1 [μA] and V _CE = 35 [mV], h _FE = 10 is already reached.
Over. In the completely saturated region where V _CE is extremely lowered, the reverse injection of holes from the collector to the base is superior, and the leakage current due to the parasitic PNP transistor with the substrate (11) cannot be ignored, so the apparent emitter Current flows in the opposite direction from the collector to the collector.

Now, consider the case where a lateral PNP transistor is used as a switch as shown in FIG. In FIG. 3, (21) is a switching transistor, (22) is a predetermined circuit connected to the collector of the switching transistor (21),
The collector current of the switching transistor (21) flows according to the input signal applied to the input terminal (23), and the output terminal (2
It is configured to drive a predetermined circuit (22) connected to 4). Assuming that the collector current I _C of the switching transistor (21) needs to be 10 μA to operate the predetermined circuit (22) and the power supply voltage V _CC has dropped to 1.0 V in FIG. From FIG. 2B, when the base current Ib = 1 μA, the conventional lateral PNP transistor has a saturation voltage of V _CE = 50 mV, whereas the lateral PNP transistor of the present invention has a saturation voltage of V _CE = 35 mV under the same condition. It will not remain. The output voltage of the output terminal (24)
Since only the remaining voltage obtained by subtracting V _CE from V _CC is applied, the output voltage is 0.950 V in the conventional case and 0.965 V in the case of the present invention. V _BE for one transistor is required to construct a given circuit (22) 0.6V, and if the remaining voltages 0.350V and 0.365V are used as the collector-emitter voltage of other transistors, the output It is clear that if the output voltage of the terminal (24) is as high as possible, the voltage reduction characteristic of the predetermined circuit (22) can be improved. It is possible to use an NPN transistor as the switching transistor (21), but since the output voltage of the output terminal (24) is regulated by the base-emitter voltage V _BE and the base potential cannot be set higher than the power supply voltage V _CC , Since it cannot be set sufficiently high and it is more advantageous to use a PNP transistor as shown in FIG. 3, this switch circuit is frequently used in equipment using a low power supply voltage.

4A and 4B are a sectional view and a plan view, respectively, for explaining a second embodiment of the present invention. One conductivity type semiconductor substrate is shown.
(11) The reverse conductivity type epitaxial layer (12) formed by stacking on the surface, the N ⁺ type buried layer (13) buried by being buried in the surface of the substrate (11), and the buried layer (13 ), A P ⁺ -type isolation region (14) penetrating the epitaxial layer (12) and an isolation region (1
4) an island region (15) formed in an island shape, a P-type emitter region (16) and a collector region (17) arranged alternately on the surface of the island region (15) at a distance from each other, and these emitter regions (16) and the collector region (17) are collectively surrounded by a guard ring region (18), an oxide film (19) and an electrode (20), and an emitter region (16) is arranged at both ends. It is set up. The emitter region (16) and the collector region (17) are formed to have the same shape and the same size, and their separation distance (base width) is also the same. In the lateral PNP transistor formed in this way, although the junction lengths of the base-emitter junction and the base-collector junction, which are active as transistors, are approximately equal, the emitter region (16) is arranged at both ends, so that the guard ring region (18) is Hole injection from the emitter to the base that cannot be prevented acts, and it is equivalent to increasing the base-emitter junction length as a result. Therefore, the saturation voltage in the lower voltage region becomes smaller than that of the lateral PNP transistor of FIG. In addition, since the same result can be obtained by increasing the size of the emitter region (16), it is possible to increase the maximum collector current IC max with space advantage. However, when the number of the emitter regions (16) is two and the number of the collector regions (17) is one, the ratio of the substantial base-emitter junction to the base-collector junction becomes excessively large, and therefore h _FE cannot be obtained, and the first
Since the characteristics deteriorate slightly compared to those in the figure, it is not so preferable if the reduction voltage characteristics are emphasized.

(G) Effect of the Invention As described above, according to the present invention, the ratio of reverse injection of holes from the collector to the base with respect to injection of holes from the emitter to the base is substantially equal, so that the collector-emitter ratio is 0.6 to Excellent collector current rise characteristics in the low voltage region where the base-collector junction becomes forward bias at 0.7 V or less, and thus high in such region as well.
It has an advantage of exhibiting h _FE and providing a lateral PNP transistor having a low saturation voltage V _CE (sat). Therefore, 1.5V
A lateral PNP transistor suitable for use in an IC circuit using (1.0 V compensation) or a 3 V battery as a power supply voltage can be provided, and the voltage reduction characteristics of the circuit can be significantly improved. In addition, according to the second embodiment of the present invention, it is possible to provide a lateral PNP transistor having better characteristics than the first embodiment. And the lateral PNP of the present invention
The transistor does not require any additional steps,
It also has the advantage that it can be implemented immediately.

[Brief description of drawings]

1A and 1B are a plan view and a sectional view taken along the line AA of a lateral PNP transistor according to a first embodiment of the present invention, and FIGS. 2A and 2B are those of the present invention and a conventional one, respectively. FIG. 3 is a characteristic diagram showing the transistor characteristics of the above, FIG.
A circuit diagram showing a switch circuit using an NP transistor,
4A and 4B are a plan view and a cross-sectional view taken along the line BB, respectively, showing a second embodiment of the present invention, and FIGS. 5A and 5B are plan views showing a conventional lateral PNP transistor, respectively. It is a CC line sectional view. (11) is a P-type semiconductor substrate, (16) is a P-type emitter region,
(17) is a P-type collector region, (18) is an N ⁺ -type guard ring region, and (21) is a switching transistor.

Claims (2)

[Claims] 1. An emitter region of one conductivity type formed on the surface of an island region of one opposite conductivity type serving as a base, and a collector region of one conductivity type formed so as to be opposed to the emitter region. A guard ring having a higher impurity concentration than the base of opposite conductivity type, which is a base extraction region formed so as to surround the emitter region and the collector region collectively and in contact with each region, and the emitter region and the collector region. An emitter electrode and a collector electrode electrically connected to the guard ring, and a base electrode electrically connected to the guard ring, and the lengths of the base-emitter junction and the base-collector junction facing each other that are not in contact with the guard ring. Lateral transistor, which is characterized by making the thicknesses substantially equal. 2. The emitter region and the collector region are spaced apart from each other and alternately arranged on the surface of the island region, and the emitter regions are arranged at both ends of the island region. Lateral transistor according to.