JPH069351B2 - Digital signal synchronization circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a digital signal synchronizing circuit for extracting a clock signal synchronized with a digital signal input.

[Prior art]

A block diagram of a conventional digital signal synchronizing circuit is shown in FIG. In the figure, 1 is a fixed frequency oscillator, 2 is a delay circuit, 3 is a decoder, 4 is a selector, 5 is a phase comparator, 6
The control pulse generator 7 is an up / down counter. This conventional circuit has a fixed frequency oscillator 1 in the circuit and can be synchronized within the frequency stability range of the oscillator 1 even when the input signal is stopped. Here, the delay circuit 2 phase-divides the output of the oscillator 1 into 2M signals and produces 2M signals having a phase difference of Δ = 2π / 2M. The decoder 3 selects one of the 2M signals designated by the counter 7 and outputs the output signal S via the selector 4.
get out The phase comparator 5 compares the phases of the input signal Sin and the output signal Sout, and when detecting a phase difference of Δ / 2 or more, outputs a phase delay (or phase advance) signal. When the control pulse generator 6 continuously detects the phase delay (or phase skip) signal m times, the control pulse generator 6 changes the counter 7 by 1 to reduce the phase difference and outputs the output signal Sout via the decoder 3 and the selector 4. Phase correction is performed and the input signal Si
The output signal Sout is synchronized with n.

In this method, there are two problems that the delay amount of the delay circuit 2 is required exactly for the phase 2π, the accuracy of 2π and the hardware scale of the delay circuit for 2π are large.

[Object of the Invention]

It is an object of the present invention to provide a digital signal synchronizing circuit which eliminates the above-mentioned drawbacks of the prior art, increases the margin for variations in the delay amount accuracy of the delay circuit, and reduces the hardware scale of the circuit.

[Outline of Invention]

In the present invention, the frequency of the oscillator is N times the input signal, the required delay amount of the delay circuit is 1 / N of the conventional one, and a circuit for detecting the phase difference between the phase reference signal of the delay circuit and the output clock signal is added. The selector is adapted to select the phase signal corresponding to the central position of the delay circuit when the circuit detects a predetermined phase difference.

Example of Invention

The present invention will be described in detail below with reference to an embodiment circuit shown in FIG. In the figure, 11 is the frequency f of the input signal Sin.
An oscillator that outputs a frequency fo ′ (fo′≈N · fin) that is N times in, a delay circuit 12 that outputs a phase reference signal from a central position while having a delay amount of 4π / N + (α is an element of the delay circuit Margin to absorb variations), 13 is a selector that includes a decoder function, 14 is a phase comparator, 15 is a control pulse generator that includes an up / down counter, 16 and 17 are 1 / N frequency dividers, and 18 is 2π / N. It is a phase comparator for detection.

Next, the operation will be described.

Oscillator 11 having frequency fo ′ which is N times the input signal frequency fin
Is output to the delay circuit 12, and the output selected by the selector 13 from the outputs is divided by 1 / N by the 1 / N frequency divider 16 to be the synchronous clock output Sout. This clock output Sout and the input signal Sin are compared in phase by the phase comparator 14 to obtain a phase delay (or phase advance) signal. When the control pulse generator 15 detects the output signal continuously m times, the control pulse generator 15 generates a control pulse so that the selection position of the selector 13 moves by one delay element in the direction of reducing the phase difference between the two signals. To do. In addition, the phase reference signal is extracted separately from the center position of the delay circuit 12 (this is the phase origin),
This phase reference signal is frequency-divided by the 1 / N frequency divider 17 and the phase of the synchronous clock output Sout is compared by the phase comparator 18, and if a phase difference of | 2π / N is detected, a reset pulse is sent to the selector 13. Is output and the signal is reset to select the signal of the selector 13 phase origin. Here, the phase origin is set at the center of the delay circuit 12 even if the constant error between the frequency fo'of the oscillator 11 and the frequency fin of the input signal Sin is "+" or "-" can be processed by the same procedure. This is because

〔The invention's effect〕

For the configuration of the circuit system of the present invention, the delay circuit requires a minimum delay amount of 2π / N on both sides of the phase origin, and a total delay amount of 4π / N. Since the delay amount of 1 is given, since the phase α is provided as a margin for variations in the delay accuracy, the margin can be increased. Also, by setting N to 4 or more,
The required delay is obviously less than 2π (when N = 4, That is, the scale of the delay circuit is reduced, and the hardware scale can be reduced as a whole even if the increase in other components is included.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional digital signal synchronizing circuit,
FIG. 2 is a circuit diagram of an embodiment of a digital signal synchronizing circuit according to the present invention. 11: Oscillator 12: Delay circuit 13: Selector 14: Phase comparator 15: Control pulse generator 16,17: 1 / N frequency divider 18: 2π / N detection phase comparator

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Fujio Amamiya 1-2356 Takeshi, Yokosuka City, Kanagawa Prefecture Yokosuka Telecommunications Research Institute, Nippon Telegraph and Telephone Public Corporation (72) Naoki Matsuo 1-2356, Takeshi City, Yokosuka, Kanagawa Prefecture Nippon Telegraph and Telephone Corporation Telephone Public Corporation Yokosuka Electro-Communication Research Laboratory (56) References JP-A-51-134538 (JP, A)

Claims (1)

[Claims] 1. An output of an oscillator is supplied to a selector through a delay circuit, and based on a comparison output obtained by comparing an input signal to a synchronizing circuit and an output signal selected by the selector in a phase comparison circuit, In a digital signal synchronizing circuit for controlling the selection position of the selector, the frequency of the oscillator is set to N times the frequency of the input signal (N is an integer), and the delay circuit is phased from its central position. The reference signal is taken out and its delay amount is 4π / N + margin phase α, and the phase comparator circuit divides the input signal and the selector output by 1 / N frequency by the first 1 / N frequency divider. In addition to phase comparison, a second phase comparison is made between the output of the first 1 / N frequency divider and the signal obtained by frequency-dividing the phase reference signal of the delay circuit by the second 1 / N frequency divider. The circuit compares the phases, and the second phase comparison circuit detects a predetermined phase difference. A digital signal synchronizing circuit, characterized in that the selector is reset so as to select a phase signal corresponding to the central position of the delay circuit at the time.