JPH069397B2 - Time switch - Google Patents

Description

TECHNICAL FIELD The present invention relates to a time switch used in a broadband time division switch.

[Conventional technology]

Conventionally, as a time switch for performing phase conversion of a call signal on a highway, those described in Akiyama, Goto, Shimazaki, "Digital Telephone Exchange" (Industrial Books), pages 25 to 28 are known. FIG. 2 is a block diagram showing the structure of a time switch according to the prior art. This time switch comprises a counter 201 and a demultiplexer 202 whose signal input is connected to the input highway 208 and whose control input is connected to the output of the counter 201.
And the first to fourth inputs are the first to fourth of the demultiplexer 202.
Channel memory cell array 206 connected to the fourth output
And the first to fourth signal inputs are the communication path memory cell array 20.
A multiplexer 204 connected to the first to fourth outputs of 6, the output of which is connected to the output highway 209; the demultiplexer 203 whose signal input is connected to the control information terminal 210 and whose control input is connected to the address terminal 211; A control memory cell array 207 whose first to fourth inputs are connected to first to fourth outputs of the demultiplexer 203, and first to fourth signal inputs are first to fourth outputs of the control memory cell array 207. In addition, the control input is connected to the output of the counter 201, and the output is composed of the multiplexer 205 connected to the control input of the multiplexer 204.

In FIG. 2, the case where the call signal A multiplexed in the time slot 0 on the input highway 208 is output to the time slot 2 on the output highway 209 will be described.
First, the demultiplexer 202 counters the call signal A multiplexed in the time slot 0 on the input highway 208.
The address of the channel memory cell array 206 is output by the output of 1.
Write to 0. On the other hand, the demultiplexer 203 outputs "0" to the address # 2 of the control memory cell array 207 by the control system (not shown) outputting "0" to the control information terminal 210 and "2" to the address terminal 211. Write. Here, when the output of the counter 201 is 2, that is, when the time slot number on the output highway 209 is 2, the multiplexer 205 outputs “0” written in the address # 2 of the control memory cell array 207. In addition, the multiplexer
204 outputs the call signal A written in the address # 0 of the call path memory cell array 206 to the highway 209 by the output “0” of the multiplexer 205.

[Problems to be solved by the invention]

In the prior art time switch shown in FIG.
When trying to increase the number of lines accommodated, I / O highway 20
It is necessary to increase the multiplicity of 8,209, increase the capacity of the communication path memory cell array 206 and the control memory cell array 207, and increase the operation speed. For example, the signal speed is 140Mbps
When handling wideband signals such as
The memory must read and write call signals at a speed of 2.24Gbps just by multiplexing. However, it is difficult to realize such a memory that operates at high speed, and there is a problem that a large capacity time switch cannot be configured.

An object of the present invention is to provide a time switch that solves such problems.

[Means for solving problems]

A time switch according to a first aspect of the present invention includes a plurality of input highways, a plurality of output highways, and a memory including a plurality of regions respectively assigned to the input highways, each of which receives the input according to a first control signal. A plurality of means for writing a call signal on a highway to an area of the memory allocated to the input highway; and a plurality of means for writing the call signal from a desired address of the entire area of the memory according to a second control signal, respectively. It is characterized by having a plurality of means for reading to.

A time switch according to a second aspect of the present invention includes a plurality of input highways, a plurality of output highways, and a memory including a plurality of regions respectively assigned to the output highways, each of which receives the input according to a first control signal. A plurality of means for writing call signals on the highway to desired addresses in all areas of the memory; and the output highway from areas assigned to the output highways of the memory for the call signals in accordance with respective second control signals. It is characterized by having a plurality of means for reading to.

[Action]

In the time switch according to the present invention, by having a plurality of input and output highways, and by having a plurality of means for writing a call signal on the input highway to the area assigned to the input highway of the memory, a call on each highway is made. By writing signals to different memory cells at the same time, and by having a plurality of means for reading from a desired address in the entire area of the memory to the output highway, a call signal is simultaneously output from a plurality of memory cells to a plurality of output highways. . As a result, the number of lines accommodated in the time switch can be increased according to the number of input / output highways without increasing the operation speed of the memory. Further, even when the memory is composed of a plurality of areas respectively assigned to a plurality of output highways, the number of lines accommodated in the time switch can be increased according to the number of input / output highways without increasing the operation speed of the memory. You can

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. First
According to the drawing, the embodiment of the present invention shows that the counter 101, the signal input is the control information terminal 131, and the control input is the address terminal 132.
, A control memory cell array 110 having first to fourth inputs connected to first to fourth outputs of the demultiplexer 135, and first to fourth signal inputs to the control memory 110. A multiplexer 105 whose control input is connected to the output of the counter 101,
A demultiplexer 136 whose signal input is connected to the control information terminal 133 and whose control input is connected to the address terminal 134;
Of the control memory cell array 112 whose inputs are connected to the first to fourth outputs of the demultiplexer 136, and the first to fourth signal inputs to the first to fourth outputs of the control memory cell array 112. A multiplexer 108 connected to the output of the counter 101 and a demultiplexer 103 whose signal input is connected to the highway 121 and whose control input is connected to the output of the counter 101.
And the signal input to the highway 122 and the control input to the counter 1
Demultiplexer 104 connected to the output of 01,
The fourth input is the first to fourth outputs of the demultiplexer 103, and the fifth to eighth inputs are the first to fourth outputs of the demultiplexer 104.
Channel memory cell array 111 connected to the fourth output
, A signal input is connected to the first to eighth outputs of the channel memory cell array 111, a control input is connected to the output of the multiplexer 105, an output is connected to the highway 123, and a signal input is the channel memory cell array. The first to eighth outputs of 111 comprise a multiplexer 107 having a control input connected to the output of the multiplexer 108 and an output connected to the highway 124.

In FIG. 1, a case will be described in which speech signals A and B multiplexed in time slot 0 on input highways 121 and 122 are output to time slot 2 on output highway 124 and time slot 1 on output highway 123, respectively. . The call signal A multiplexed in the time slot 0 of the input highway 121 is stored in the address # 0 of the call path memory cell array 111 by the output of the counter 101.
On the other hand, in the demultiplexer 136, the control system (not shown) outputs "0" to the control information terminal 133 and "2" to the address terminal 134, so that the control memory cell array 11
Write "0" to address # 2 of 2. Here, when the output of the counter 101 is 2, that is, when the time slot number on the output highway 124 is 2, the multiplexer 108 outputs “0” written in the address # 2 of the control memory cell array 112. Further, the multiplexer 107 outputs the call signal A written in the address # 0 of the call path memory 111 to the highway 12 by the output “0” of the multiplexer 108.
Output to 4. Similarly, the call signal B multiplexed in the time slot 0 on the input highway 122 is output to the time slot 1 on the output highway 123.

As described above, in the embodiment of the present invention, the input highway
By providing the demultiplexers 103 and 104 for the respective 121 and 122, the call signals on the input highways 121 and 122 are simultaneously written to different addresses of the call path memory cell array 111, and the multiplexers 106 and 107 are provided for the output highways 123 and 124, respectively. The call signals A and B written in 111 can be read on the output highways 124 and 123, respectively. As a result, a time switch having twice the number of accommodated lines can be constructed by using a memory having the same operating speed as the time switch shown in FIG.

In the present embodiment, it is described that the channel memory including the plurality of areas respectively assigned to the input highways is used and the sequential writing and the designated reading are performed, but the channel memory including the plurality of areas respectively assigned to the output highways is described. Similarly, the time switch can be similarly configured by performing designated writing and sequential reading using.

〔The invention's effect〕

As described above, according to the present invention, it is possible to increase the number of lines accommodated in the time switch without increasing the operation speed of the memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a time switch according to the prior art. 111,206 …… Channel memory cell array 110,112,207 …… Control memory cell array 103,104,135, 136,202,203 …… Demultiplexer 105 to 108,204,205 …… Multiplexer 101,201 …… Counter

Claims (2)

[Claims] 1. A call having a plurality of input highways, a plurality of output highways, and a memory having a plurality of areas respectively assigned to the input highways, each of which is on the input highway in response to a first control signal. A plurality of means for writing a signal to an area of the memory allocated to the input highway; and a plurality of means for reading the call signal from a desired address of the entire area of the memory to the output highway in response to a second control signal, respectively. A time switch having means. 2. A call on the input highway having a plurality of input highways, a plurality of output highways, and a memory composed of a plurality of areas assigned to the output highways, respectively, according to a first control signal. A plurality of means for writing signals to desired addresses in all areas of the memory; and a plurality of means for reading the call signal from the area assigned to the output highway of the memory to the output highway in response to a second control signal, respectively. A time switch having means.