JPH03145352A - Satellite exchange - Google Patents

Abstract

PURPOSE:To make the circuit scale small by applying time division multiplex to plural low speed data, giving the multiplexed data to one series of information data memory circuit to write the data. CONSTITUTION:A signal multiplex circuit 9 is provided, which applies time division multiplex to low speed input data 1-3 and a high speed data is generated by applying time division multiplex to the input data 1-3 and the high speed data is formed to be a speed data nearly the same as the high speed data 4. Then one series of information data memory circuit 7 is used for the high speed data. Plural low speed data 1-3 are multiplexed into a high speed data in this way and the data is written by using one series of information data memory circuit 7 for the high speed data, then no waste of memory area in each information data memory circuit 7 is caused and the scale of the information data memory circuit 7 is made small.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to satellite switches that require memory during exchanges such as data rate exchanges and channel exchanges.

[Conventional technology]

A conventional satellite exchange is shown in the block diagram of FIG.

In the figure, a plurality of columns of input data 1, 2, 3, 4 are written into all the information data memory circuits 7 in the same row, and then read out according to random read address data. Since the read data is time-division multiplexed, each output data 6 is generated by distributing signals to each output port in the signal division circuits 8, 8', 8''.

The information data memory circuits 7 all have the same circuit configuration, the number of rows is equal to the number of input data, and the number of columns is proportional to the number of output data. Therefore, as the number of input data increases or the number of output data increases, the circuit size increases proportionally.

[Problem to be solved by the invention]

By the way, FIG. 4 shows an example of the memory map of the information data memory circuit 7 in FIG. 3. Figure (a) is a memory map when the input data transmission rate is maximum and the number of channels included in the information data is I, and Figure (b) is the memory map when the input data transmission rate is medium and the number of channels included in the information data is I. The memory map when the number of channels included in the data is i, and FIG. 2C shows the memory map when the input data transmission speed is the minimum and the number of channels included in the information data is 1.

As shown in these figures, the number of data stored in the information data memory circuit 7 is equal to the number of channels included in each input data.
Even when high-speed data is input to the information data memory circuit 7, there is a memory area that is not used on the low-speed data side.

Therefore, if the information data memory circuit 7 is configured to correspond to the number of high-speed data, there is a problem in that the memory area is wasted on the low-speed data side, and the overall circuit size increases.

An object of the present invention is to provide a satellite exchange that enables required data conversion without increasing the circuit scale.

[Failure to solve the problem]

The satellite exchange of the present invention is provided with a signal multiplexing circuit that time-division multiplexes a plurality of low-speed input data, and has a configuration in which a row of information data memory circuits is connected to this multiplexed signal.

[Effect]

In the S configuration, a plurality of low-speed data can be multiplexed into high-speed data, and data is written by connecting one column of information data memory circuits to this high-speed data, so each information data memory circuit There is no wastage of memory area in the memory area, and the scale of the information data memory circuit can be reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a functional block diagram of an embodiment of the present invention. In the figure, numerals 12, 3.4 are human data, and here an example is shown in which human data 1, 2.3 are low-speed data signals, and input data 4 is a high-speed data signal. Also, an information data memory circuit 7 and a signal division circuit 8.8', 8
” remains the same as before.

Furthermore, this device is equipped with a signal multiplexing circuit 9 that time-division multiplexes the low-speed input data 1, 2.3, and time-division multiplexes the m pieces (in this case, 3) of input data 1, 2.3. By doing this, high-speed data 5 is generated, and as a result, this high-speed data 5 is converted into high-speed data 4,1! - Constructed as approximately the same speed data. In this example, the memory map for the high-speed data 5 multiplexed by the signal multiplexing circuit 9 is created by dividing an area for each input data as shown in FIG. One column of information data memory circuits 7 is connected to this high-speed data 5.

According to this configuration, the input data 1, 2, .
3 is a time-division multiplexed one-column information data memory circuit 7;
will be written to. This writing corresponds to writing the input data 4 with a fast transmission speed into the information data memory circuit 7, and thereby each The wasted area in the information data memory circuit 7 is reduced. Therefore, by writing three columns of human input data into one column of information data memory circuits 7, it is possible to reduce the number of information data memory circuits 7, and the circuit scale can be reduced.

Note that depending on the speed relationship between data with a low transmission rate and data with a high transmission rate, two or four or more pieces of input data may be multiplexed in the signal multiplexing circuit.

〔Effect of the invention〕

As explained above, the present invention time-division multiplexes a plurality of low-speed data, and connects one row of information data memory circuits to the multiplexed data to write data into each information data memory. This has the effect of eliminating wasted memory area in the circuit, significantly reducing the number of information data memory circuits, and realizing miniaturization of the circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a satellite exchange according to the present invention, FIG. 2 is a memory map of the information data memory circuit in FIG. 1, FIG. 3 is a block diagram of a conventional satellite exchange, and FIGS. (C) is a memory map of the information data memory circuit in FIG. 3, respectively. ? , 2.3... Low speed input data, 4... High speed input data, 5... Multiplexed high speed data, 6... Output data, 7... Information data memory circuit, 8'8''...Signal division circuit. Fig. 2 (a) Fig. 4 (b) (C) Fig. 6 Hokadenik Fig. 3

Claims (1)

[Claims] 1. In a satellite exchange that writes multiple input data with different transmission speeds into an information data memory circuit and sequentially reads the data from the information data memory circuit to obtain output data, multiple input data with low transmission speeds are A satellite exchange characterized in that a signal multiplexing circuit for dividing and multiplexing is provided, and a row of information data memory circuits is connected to the multiplexed signals.