JPH0696111A - Memory control system - Google Patents

Abstract

(57) [Summary] [Purpose] The execution of store instructions whose addresses increase and decrease at regular intervals is executed by a request pipe with a small amount of hardware to improve the throughput of store instructions. [Structure] The vector processing device 2 includes a plurality of request pipes 2 for issuing memory requests to the main storage device 1.
0A0 to 20B1 are provided. Request pipe 20A
0 to 20A1 are store instructions whose addresses increase / decrease at regular intervals, and request pipes 20B0 to 20B0 process the store instructions whose increase / decrease value is equal to or less than 1/2 of the block size of the buffer memory 30 in the scalar processor 3. 20B1 is
Process all store instructions. The instruction control unit 21 uses the store instruction whose request address increases and decreases at regular intervals and the other store instructions to request the request pipe 2
Use 0A0 to 20B1 properly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control system and a vector processing device in a computer system, and more particularly to a storage control system suitable for use in a computer system such as a vector processing device in which a request pipe group is used for each instruction. Regarding

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a computer system having a storage control method according to the prior art, and FIG. 4 is a diagram for explaining thinning-out of a management table (FAA) reference request. The related art will be described with reference to FIG. 3 and 4, 1 is a main memory (MS), 2 is a vector processor (VP), 3 is a scalar processor (S).
P), 20A0, 20A1, 20B0 and 20B1 are request pipes, 21 is an instruction control unit, 22 is an instruction issuing unit, 23 is a vector register (VR), 24B0, 2
4B1 is a management table (FAA), and 30 is a buffer storage.

The computer system according to the prior art shown in FIG. 3 comprises a main storage unit (hereinafter referred to as MS) 1 and load-only request pipes 20A0 and 20A1 for processing two memory requests in element parallel. Request pipe group, requests for both load and store
A vector processing device (hereinafter, referred to as VP) 2 including a request pipe group formed by pipes 20B1 and 20B1;
A scalar processing device (hereinafter, referred to as SP) 3 including a buffer storage (hereinafter, simply referred to as BS) 30 is configured.

First, the processing of a store instruction in the VP2 in the illustrated prior art will be described.

The store instruction includes an instruction for increasing / decreasing a request address at regular intervals and a list vector instruction.

Now, from the instruction issuing unit 22 to the instruction control unit 21
On the other hand, when an instruction is issued together with the instruction code 250, the instruction control unit 21 decodes the code 250 and detects that it is a store instruction, and issues a request 260B to the request pipes 20B0 to 20B1. To do. This request has a vector length of the instruction to be executed divided by the number of parallel elements of the request pipe, and in this example, 20B0 to 20B as the request pipe.
Since the two elements of 1 are provided, the vector length of the instruction to be executed is divided by 2 and is issued, and the request for the final element is added with information indicating that it is the final element request.

Request pipes 20B0-20B1
Is synchronized with the issuance of an instruction from the instruction issuing unit 22 to the instruction control unit 21, and the start address 252 and the vector increment address 251 or the vector register (hereinafter referred to as VR).
The index data 270B is received from the command controller 21 and the vector increment address 251 and the index data 270 are received by the request 260B from the instruction control unit 21.
One of B is selected, and the address is sequentially calculated by the selected value and the head address. Then, the request pipes 20B0 to 20B1 receive the store data 271B from the VR 23 and receive the flip-flop (hereinafter, referred to as F
Address F through 202B-204B
0B, request 281B, store data 282B to M
Send to S1.

The decimation control circuit 206B compares the vector increment address 251 with the management unit of the BS 30 (hereinafter referred to as block size), and if the vector increment address is equal to or larger than the block size value, or if the request is In case of list vector access, management table (hereinafter referred to as FAA) 24B0 to 24B1
Issue a reference request 284B0, 284B1 for each request with the address 285B0, 285B1 of each request. If the vector increment address 251 is equal to or smaller than 1/2 of the block size, the FAA reference request of two consecutive requests enters the same block of the BS 30, so that the thinning circuit 206B makes one request 284B0 among the requests that operate simultaneously. Only about address 28
5B0 and other FAA reference requests are thinned out and sent. Request 28 only when the request is the final element
4B1 and address 285B1 are also transmitted.

As a conventional technique relating to such a thinning-out method of request reference request, for example, Japanese Patent Laid-Open No. 1-18
The technology proposed as No. 0669 is known.

The data at the memory addresses 285B0 and 285B1 stored as described above is stored in BS3 in SP3.
Whether the address is fetched into 0 or not is the FAA of that address.
Detected by referencing 24B0-24B1 and if the data is captured by BS30, F
AA24B0, 24B1 are BS invalidation signals 29B0,
By sending 29B1 to BS30 and canceling the contents in BS30, the matching of contents in BS30-MS1 is guaranteed.

Next, referring to FIG. 4, in the case where the vector increment address is larger than 1/2 of the block size of BS30 and when it is equal to or smaller than 1/2 of the block size F
The thinning of the AA reference request will be described.

The vector increment address 251 is a block
If it is larger than 1/2 of the size, the access address is added with the vector increment address 251 in synchronization with the request 260B, as shown in FIG.
00, 285B10, 285B01, 285B11, 2
85B02, 285B12. In this case, the addresses 285B00 to 285B02 are the request pipe 20B0 and the addresses 285B10 to 285.
B12 is processed by the request pipe 20B1.

Addresses 285B00 to 285B02, 2
BS invalidation signals 29B00 to 29B02, 29B10 to 29B1 to BS30 by 85B10 to 285B12.
2 is sent out. BS invalidation signals 29B00, 29B1
0, block 300 of BS 30, block 301 by BS invalidation signal 29B01, block 302 by BS invalidation signal 29B11, BS invalidation signal 2
The blocks 303 are invalidated by 9B02 and 29B12, respectively, and the matching of the contents of the BS 30 and the MS 1 is guaranteed.

When the vector increment address is less than 1/2 of the block size, as shown in FIG. 4B, the address is incremented by the vector increment address 251 in synchronization with the request 260B, 285B03, 285B13,
285B04, 285B14, 285B05, 285B
15, 285B06, 285B16, 285B07, 2
85B17, 285B08, 285B18. In this case, the addresses 285B03 to 285B08
Is request pipe 20B0 at address 258B
13 to 258B18 are processed by the request pipe 20B1.

Address 285B03 and address 285B
Since 13 is for the same block 305, only 29B03 is transmitted as the BS invalidation signal, and 29B13 is not transmitted. Similarly, only the request pipe 20B0 side BS invalidation signal 29B04-
If 29B07 is sent, request pipe 20B1
The blocks 305 to 308 can be invalidated without sending the BS invalidation signals 29B14 to 29B17 from the side. However, when the request is the final element, there is a case where only the request pipe 20B1 side is provided. Therefore, the BS invalidation signal 29B18 is transmitted to invalidate the block 309, and the matching of the contents of the BS 30-MS1 is guaranteed.

[0016]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Prepare FAA for the number of parallel request pipe elements,
Store requests do not become a bottleneck for FAA reference. However, the above-mentioned conventional technique is based on this FAA.
Since the amount of hardware in the
One of the pipes is dedicated to loading and the other is used for loading / storing, and the instruction control unit 21 in the VP2 discriminates between the load instruction and the store instruction.
Request pipe group by 0, 20A1 and 20B
0 and 20B1 are used as the request pipe group.

As described above, in the above-mentioned conventional technique, one of the two request pipes is dedicated to loading,
There is a problem that the throughput of store instructions is reduced due to the lack of request instruction request pipes.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to enable execution of a store instruction whose request address increases or decreases at regular intervals by a request pipe composed of a small amount of metal. , And to provide a storage control method capable of improving the throughput of store instructions.

[0019]

Generally, a program in a vector processing device uses many instructions in which a request address increases or decreases at regular intervals.

According to the present invention, the object is to utilize the characteristics of the program and enable a load-only request pipe to process a store instruction whose request address increases or decreases at regular intervals. That is, by using all the request pipes for both load and store, and also in the VP, there is provided an instruction control unit for discriminating between an instruction whose request address increases and decreases at a constant interval and other instructions regarding the store instruction. Achieved by

[0021]

[Function] Loads all request pipes in VP /
It is also used as a store, and the instruction control unit in the VP requests
Since it is possible to distinguish between the store instruction whose address increases and decreases at regular intervals and other store instructions and use these request pipes properly, it is possible to improve the throughput of the store instruction.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a storage control system according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a computer system to which the present invention is applied, and FIG. 2 is a block diagram showing a configuration of an instruction control unit according to an embodiment of the present invention. 1 and 2, reference numeral 24A is a management table (FAA), 210 is an instruction decoder, 211 is a request generation circuit, 2112 is a request pipe assign circuit, and other reference numerals are the same as those in FIG.

As shown in FIG. 1, one embodiment of a computer system to which the present invention is applied is composed of MS1, VP2 and SP3, which is almost the same as the case of the prior art shown in FIG. One embodiment of the present invention is largely different in that the request pipes 20A0 and 20A1 are used exclusively for loading but also for loading / storing, so that the FAA 24A is newly provided.

In this embodiment of the present invention, VP2 is
An instruction issuing unit 22 that issues an instruction, an instruction control unit 21 that issues a request, and a VR that holds vector data
23, the load instruction and the request address are increased / decreased at regular intervals, and the absolute value of the increase / decrease value of the address is 1 / element parallel number of the block size of BS30. Pipe 20A0-20A
1, request pipes 20B0 to 20B1 capable of processing all load / store instructions, and BS30
The FAA 24A, 24B0, 24B1 for registering the address of the data stored in the main storage device 1 is configured.

Then, the request pipes 20A0-2
0A1 and request pipes 20B0 to 20B1 are provided by the number of faces in parallel for each element (two faces in the example of FIG. 1), and the FAA 24A can thin reference, so one face, FAA 24B0 to 24B1 Considering the case where the reference cannot be thinned, the number of faces for the element parallel (Fig. 1
In this example, two surfaces are provided.

In this embodiment of the present invention, it is assumed that the VP2 is activated and the instruction issuing unit 22 issues a load instruction. In this case, the instruction issuing unit 22 uses the instruction code 250.
To the request pipe, and the command control unit 21 sends the request 260A or 260B to the request pipe.

Request pipes 20A0-20A1
When the request 260A is sent from the instruction control unit 21, the index data 2 from the VR 23 depends on whether the instruction type is list vector load or not.
70A or one of the vector increment addresses 251 from the instruction issuing unit 22 is selected by the selector 200A, and the address adder 201A together with the head address 252 is selected.
To enter.

The address adder 201A sequentially calculates addresses by this, and sends the address 280A to the MS1 together with the request 281A from the FFs 202A and 203A. After that, request pipe 20A0
The 20A1 receives the fetch data 283A fetched from the MS1 by the request 281A, and the FF 20
It is sent to the VR 23 as fetch data 272A via 5A.

In the above, the request pipes 20A0 to 20A0
Although the load operation of 20A1 has been described, the request pipes 20B0 to 20B1 operate similarly.

Next, the operation relating to the store instruction, which is a feature of the present invention, will be described.

In this case, the request address increases / decreases at regular intervals, and the increase / decrease value of the address is BS30.
Store instructions of 1/2 or less of the block size and other instructions are processed separately.

In order to carry out the processing relating to the store instruction, the instruction control section 21 has the instruction decoder 210 as shown in FIG.
And the address comparison circuit 2 in the request generation circuit 211
110 and AND circuits 2111, 2113A to 2113
B and a request pipe assign circuit 2112.

Now, it is assumed that the request address is increased / decreased at regular intervals and a store instruction is issued in which the absolute value of the increase / decrease value of the address is 1/2 or less of the block size of BS30.

When the VP2 is activated, the instruction issuing unit 22
Sends the instruction code 250 and the vector increment address 251 to the instruction control unit 21. The instruction control unit 21 inputs the instruction code 250 to the instruction decoder 210 and decodes it. As a result, the instruction decoder 210 outputs the store instruction signal 212A and the store instruction signal 212B at regular intervals.

On the other hand, the vector increment address 251 is input to the address comparison circuit 2110 and the absolute value of this address increment value indicates the signal 2 indicating the block size of the BS 30.
Compared to 114. In the case of this example, the absolute value of the address increment value is equal to or smaller than 1/2 of the block size of the BS 30, so the address comparison circuit 2110 outputs the thinning-out permission signal 2115. This thinning permission signal 2115
And a constant interval store instruction signal 2 from the instruction decoder 210
12A is ANDed with an AND circuit 2111 and output as a request generation permission signal 2116.

Request pipe assign circuit 211
2 is the request pipe 20A0-2 regardless of the instruction
0A1 and request pipes 20B0 to 20B1 can be used.

Request pipe assign circuit 211
2 outputs the request pipe A selection signal 2117A, the request generation permission signal 2116 and the request pipe A selection signal 2117A are ANDed.
The logical product is taken by the circuit 2113A and the request 26
It is generated in 0A and is transmitted by the vector length to be processed / element parallel number. When the request is the final element, the order of the final element request is added and transmitted.

Request pipe assign circuit 211
When the request pipe B selection signal 2117B is signaled from 2, the request pipe B selection signal 211
7B and the store command signal 212B from the decoder 210 are logically ANDed by the AND circuit 2113B to generate the request signal 260B, and the request signal 260B is transmitted by the vector length to be processed / the number of parallel elements. When the request is the final element, the order of the final element request is added and transmitted.

In the above, the selection signal from the request pipe assign circuit 2112 causes the AND 211
When 3A sends the request 260A, the request pipes 20A0 to 20A1 have the vector increment address 25 from the instruction issuing unit 22 in the selector 200A.
Select 1. The address adder 201A uses the vector increment address 251 and the head address 252 to
The address is sequentially calculated, and the address 280A is sent to the MS together with the request 281A via the FFs 202A and 203A.
Send to 1.

Request pipes 20A0-20
A1 receives the store data 271A from the VR 23,
Similarly, the store data 282A is sent to the MS 1 via the FF 204A.

The above-mentioned request 260A is also input to the thinning circuit 206A, and the thinning circuit 206A outputs FAA.
The reference request signal 284A and the FAA reference address 285A are sent to the FAA 24A. The thinning circuit 206A is
Request signal 260A and vector increment address 25 only for requests with the last element order added
1 and the FAA reference request signal 284A and the request.
Calculate the FAA reference address 285A for the last element request of the pipe 20A1 and re-calculate the FAA 24A
Send to. At this time, no request is sent to MS1.

Request pipes 20B0-20B1
Operates similarly to the above when the request signal 260B is sent from the request pipe assign circuit 2112. In this case, the thinning-out circuit 206B detects that the reference of the table by the FAA reference request signal can be thinned out as in the conventional case, and the FAA 24B0 only has the FA
The A reference request 284B0 is transmitted. The request signal 260B and the vector increment address 251 are input to the thinning circuit 206B only for the request to which the order of the final element is added, and the thinning circuit 206B outputs F to F.
AA reference request signal 284B1 and FAA reference address 28
5B1 is sent to FAA 24B1.

Whether or not the data of the memory addresses 285A, 285B0, 285B1 stored as described above is fetched by the BS 30 in SP3 can be detected by referring to the FAA 24A, 24B0, 24B1 of these addresses. Yes, if the data is BS3
FAA 24A, 24B0, 2 if captured in 0
4B1 is a BS invalidation signal 29A, 29B0, 29B1.
Is transmitted, the contents in BS30 are canceled and the contents of BS30 and MS1 are guaranteed to match.

In the case of a store instruction other than the case described above, when the VP2 is activated, the instruction issuing section 22 sends the instruction code 250 and the vector increment address 251 to the instruction control section 21. The instruction control unit 21 inputs the instruction code 250 to the instruction decoder 210 and decodes it. The instruction decoder 210 stores the store instruction signal 2 at a constant interval when the request address is an instruction increasing or decreasing at a constant interval.
12A and a store command signal 212B are output, and only a store command signal 212B is output in the case of a list vector command.

However, the request generation circuit 2 shown in FIG.
11 is an instruction for increasing / decreasing the request address at regular intervals, and if the increase / decrease value is equal to or larger than the block size, the address comparison circuit 2100 causes the thinning permission signal 21.
If it is a list vector store instruction, the instruction decoder 210 does not output the constant interval store instruction signal 212A, so that it does not output the request generation permission signal 2116 and the request pipe assign circuit 2112. Request pipe A selection signal 2117A
Even if is output, only the request signal 260B can be transmitted.

Request pipes 20B0, 20B1
When the request 260B is sent from the instruction control unit 21, the selector 200B causes V to change depending on the type of instruction.
One of the index data 270B from R23 or the vector increment address 251 from the instruction issuing unit 22 is selected, and the address adder 201B is caused to select the selected index data or vector increment address 251.
Then, the head address 252 is used to sequentially calculate the address, and as a result, the address 280B is sent to the MS 1 together with the request 281B via the FFs 202B and 203B.

Request pipes 20B0, 20B1
Similarly receives the store data 271B from the VR 23 and sends the store data 282B to the MS via the FF 204B.
1 to the FAA 24B0 and 284B1 and FAA reference request signals 284B0 and 284B1 on the two sides of FAA 24B0 and 24B1.
The A reference addresses 285B0 and 285B1 are transmitted.

The data at the memory addresses 285B0 and 285B1 stored as described above is stored in the BS30 in the SP3.
Whether or not it has been taken into
It can be detected by referring to A24B0, 24B1, and if the data is captured in BS30, FAA24B0, 24B1 will detect BS invalidation signal 2
By sending 9B0 and 29B1, the contents in BS30 are canceled and the contents of BS30 and MS1 are guaranteed to match.

According to the above-described embodiment of the present invention, the request pipes 20A0 and 20A1
Pipe group and request pipes 20B0, 20B
Since all the request pipe groups of 1 are used for both load and store, the throughput of store instructions can be improved.

According to the above-described embodiment of the present invention, the request address of one of the two request pipe groups is increased / decreased at regular intervals, and the absolute value of the increase / decrease value of the address is set. Is less than 1/2 of the block size of BS30, and generally, when the number of parallel elements of the request pipe is n, the absolute value of the increase / decrease value of the address is less than 1 / n of the block size of BS30. Request pipes 20A0 to 20A because they are dedicated to store instructions
Regarding No. 1, the FAA 24A for registering the address in the main memory of the data stored in the BS 30 can be made to have only one surface to reduce the amount of hardware.

[0052]

As described above, according to the present invention, it is possible to execute a store instruction in which a request address increases or decreases at regular intervals by a request pipe composed of a small amount of hardware, and a store instruction is executed. The throughput can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a computer system to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of an instruction control unit according to an exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a computer system having a storage control method according to a conventional technique.

FIG. 3 is a diagram illustrating thinning-out of a management table (FAA) reference request.

[Explanation of symbols]

1 Main Storage Device (MS) 2 Vector Processing Device (VP) 3 Scalar Processing Device (SP) 21 Instruction Control Unit 22 Instruction Issuing Unit 23 Vector Register (VR) 30 Buffer Storage (BS) 210 Instruction Decoder 211 Request Generation Circuit 2110 Address comparison circuit 2112 Request pipe assign circuit 20A0, 20A1, 20B0, 20B1 Request pipe 206A, 206B Thinning circuit 24A, 24B0-24B1 Management table (FAA)

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[Procedure amendment]

[Submission date] October 14, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a computer system to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of an instruction control unit according to an exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a computer system having a storage control method according to a conventional technique.

FIG. 4 is a diagram illustrating thinning-out of a management table (FAA) reference request.

[Explanation of Codes] 1 main memory (MS) 2 vector processor (VP) 3 scalar processor (SP) 21 instruction control unit 22 instruction issuing unit 23 vector register (VR) 30 buffer storage (BS) 210 instruction decoder 211 Request generation circuit 2110 Address comparison circuit 2112 Request pipe assign circuit 20A0, 20A1, 20B0, 20B1 Request pipe 206A, 206B Thinning circuit 24A, 24B0-24B1 Management table (FAA)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadaaki Isobe 1 Horiyamashita, Hinoyama, Hadano, Kanagawa Pref., Kanagawa Plant, Hiritsu Seisakusho Co., Ltd. Hitachi Central Research Laboratory (72) Inventor Shigeko Yazawa 1 Horiyamashita, Hadano City, Kanagawa Prefecture

Claims (3)

[Claims] 1. A main storage device composed of a plurality of independently accessible storage units, and a request pipe group in which a plurality of request pipes for issuing a memory request to the main storage device operate elementally in parallel. In a computer system including a vector processing device having a plurality of groups, an instruction control unit for identifying whether the request address of a store instruction is increased or decreased at regular intervals or another instruction is provided in the vector processing device. A storage control method, comprising: selectively using the request pipe group based on the identification result. 2. The instruction control unit divides the block size of a buffer storage provided in a scalar processing device by the absolute value of a request address that increases or decreases at regular intervals by the number of request pipes operating in parallel with the element. The storage control method according to claim 1, wherein it is identified whether or not the value is less than or equal to a predetermined value. 3. One of the plurality of request pipe groups is an instruction whose request address is increased or decreased at regular intervals, and the absolute value of the increase or decrease value is a block of buffer storage provided in the scalar processor. 3. The storage control method according to claim 2, wherein an instruction having a size equal to or smaller than a value obtained by dividing the size by the number of request pipes operating in parallel is processed.