JPH0696215A - Image processing device - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a small-sized image processing device that performs high-speed processing from the imaging of a subject to the difference calculation processing between frame images necessary for feature extraction and the like. A photodiode group and a storage section are provided, each including a light receiving region having a photodiode group for imaging, and a storage section having a storage bit group for storing data corresponding to each pixel signal generated in these photodiodes. The difference bit data corresponding to the pixel array is output from the EXOR gate only by scanning the memory bits of the same scanning signal with the same scanning signal and scanning the photodiode group and the memory bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which optically picks up a subject and extracts features of the subject.

[0002]

2. Description of the Related Art In recent years, optical information processing technology has been actively developed. For example, in factory automation, the first image data of one frame image obtained by capturing a moving image of an assembly part or product conveyed by a belt conveyor of a manufacturing line with a solid-state image capturing device and capturing one frame period before. And the second image data of one frame image obtained at the present time are compared, and when these image data do not match, it is determined that the component or product has been conveyed to a predetermined position on the belt conveyor. It is known that the manufacturing process is rationalized by extracting the difference between the first and second image data as a feature of a component or a product and applying it to the determination of the type of the component or the like. ing. Also, OCR for facsimiles and computer systems
In the image reading apparatus such as the above, it is applied to character recognition, information compression, reduction of reading errors, and the like. Furthermore, a moving image of the conveyed banknote is captured by a solid-state imaging device, and the feature data of the banknote are extracted and determined by comparing the image data of the past and present one frame image, and only the true banknote is automatically recorded. It is applied to bill reading devices that count. These are just examples, and there is a tendency to develop more and more by taking advantage of the optical information processing technology.

The structure of a conventional general circuit to which such an optical information processing technique is applied will be described with reference to FIG. 6. For example, for example, the light receiving region 1 of a MOS type two-dimensional solid-state image pickup device.
A horizontal shift register 1x for horizontally scanning these pixel groups while the pixel groups consisting of photodiode groups arranged and formed in a matrix form an image of a subject.
The pixel signals of each pixel are read out in time series by the dot-sequential scanning read-out by the vertical scanning register 1y for vertical scanning and the read-out pixel signal is A
The / D converter 2 converts the data into digital pixel data, and the random access memory (RAM) 3 stores the data sequentially in a memory area addressed by the microprocessor (MPU) 4. Since the operation timings of the horizontal shift register 1x and the vertical scanning register 1y and the addressing timing of the MPU 4 are synchronized with the reference clock signal output from the timing generator 5, the RAM 3
The pixel data stored in 1) corresponds to the pixel array of the light receiving region 1 in a one-to-one relationship. Then, N pieces of pixel data corresponding to the first one-frame image are stored in the storage areas (areas indicated by A in the drawing) of the addresses # 0 to # N-1 of the RAM 3, and N corresponding to the next one-frame image. This pixel data is assigned to the addresses #N to # of RAM3.
By storing in a 2N-1 storage area (area indicated by B in the figure), pixel data of two frame images, which are shifted by one frame cycle from each other, are stored. Next, the MPU 4 reads out the pixel data from the respective storage areas A and B of the RAM 3 without destroying the array, and obtains the difference between the pixel data in a mutually corresponding relationship to obtain a difference data group corresponding to the pixel array. Based on these difference data groups, signal processing such as feature extraction and recognition of the subject, determination of the presence of the subject, and the like is performed.

[0004]

However, the conventional image processing apparatus as shown in FIG. 6 has the following problems. That is, since the difference calculation for performing the feature extraction as described above is realized by the program processing of the MPU 4, there is a problem that the load of the computer program is heavy and the processing speed becomes slow. Further, since such program processing is largely responsible, the signal processing for feature extraction and recognition cannot be started unless the pixel data group corresponding to the two frame images is once stored in the RAM 3. Also in this respect, there is a problem that the processing speed becomes slow. Further, since the pixel data once stored in the RAM 3 is read out by the address designation based on the program control of the MPU 4, it is impossible to simultaneously read out the respective pixel data in the storage areas A and B.
That is, after reading the pixel data of the address # 0 of the storage area A, the pixel data of the address #N of the storage area B is read and the difference operation is performed, and then the pixel data of the address # 1 of the storage area A is read. After that, the pixel data of address # N + 1 in the storage area B is read out and the difference calculation is performed. Thereafter, similarly, the pixel data of the storage areas A and B are alternately read out to obtain the difference for all the pixel data. The pixel data must be obtained, and reading of pixel data from the RAM 3, which is a prerequisite for signal processing, has also been a factor that causes a delay in signal processing.

Further, there is a problem that a large-sized RAM for storing data of two frame images is required, which causes an increase in size of the apparatus.

The present invention has been made in view of the above problems to be solved by the prior art, and performs high-speed processing from the image pickup of a subject to the difference calculation processing between frame images necessary for feature extraction and the like. Another object of the present invention is to provide an image processing device that realizes downsizing of the entire device.

[0007]

In order to achieve such an object, the present invention provides a photodiode group corresponding to a pixel group arranged one-dimensionally, and an intervening element between each photodiode and a signal read line. Switching elements group,
By outputting a scanning signal for selectively controlling conduction / non-conduction of each switching element, a horizontal scanning circuit for transferring the pixel signal generated in the photodiode to the signal readout line via the switching element in the conductive state, A storage unit that has the same number of storage bits as the photodiode group and that writes or reads data to or from the storage bits designated by the scanning signal output by the horizontal scanning circuit, and is connected to the end of the signal read line, An output amplifier that converts the pixel signal of the signal readout line into a voltage pixel signal, and the pixel signal of the voltage output from the output amplifier is compared with a predetermined threshold voltage to convert into binary data for each pixel. The comparator and the binarized data output from the comparator are transferred to the storage unit based on the switching control signal or The switching means for transferring and writing the binarized data in the storage unit at the time of transfer and reading the data at the time of non-transfer, and the binarized data output from the comparator and the data output from the storage unit are exclusive. It has a configuration including an EXOR gate for performing an OR operation.

Further, a photodiode group corresponding to a pixel group two-dimensionally arranged in a matrix in the horizontal and vertical directions and a vertical signal read line provided corresponding to the photodiode group arranged in the vertical direction. A first switching element group interposed between the group and a vertical signal read line corresponding to each photodiode, and a second switching element group interposed between the end of each vertical signal read line and the horizontal signal read line. Pixels generated in the photodiode by outputting a vertical scanning signal for selectively controlling conduction / non-conduction for each of the switching element group and the switching elements arranged in the horizontal direction of the first switching element group. A vertical scanning circuit that transfers a signal to the vertical signal read line through the switching element in the conductive state, and a switch of the second switching element group. A horizontal scanning circuit for transferring the pixel signal of the vertical signal read line to the horizontal signal read line through the conductive switching element by outputting a horizontal scanning signal for selectively controlling conduction / non-conduction for each scanning element. A storage unit having the same number of storage bits as the photodiode group, for writing or reading data to or from the storage bits designated by the scanning signals output from the vertical scanning circuit and the horizontal scanning circuit; An output amplifier connected to the end of the signal output line for converting the pixel signal of the horizontal signal readout line into a pixel signal of a voltage, and comparing the pixel signal of the voltage output from the output amplifier with a predetermined threshold voltage. A comparator for converting into binary data for each pixel and binary data output from the comparator based on the switching control signal. Transfer or non-transmission to the parts causes written into the storage unit of binary data in transit,
The switching means for reading data during non-transfer and the EXOR gate for performing an exclusive OR operation on the binarized data output from the comparator and the data output from the storage section are provided.

[0009]

According to the present invention having such a configuration, the photodiode group in the light receiving region and the storage bit in the storage section are scanned by the same scanning signal, so that means for addressing each bit in the storage section. Can be omitted, and simplification of the device can be realized.
In addition, since the difference data corresponding to the pixel array is output from the EXOR gate only by scanning the photodiode group and the storage bit, not by the conventional program control by the MPU, the processing speed is improved. or,
By controlling the switching means in accordance with the switching control signal, the data once held in the storage bit can be read and processed any number of times, so that the application range to the signal processing technique is wide.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, an embodiment in which a MOS type one-dimensional line sensor is applied will be described with reference to FIG. The light receiving area 10, and the photodiode PD ₁ -PD _n of a large number n, each corresponding to a pixel (pixel), MOS as a switching element
FET M _{1 to} M _n are formed, and MOSFET
_One node of each of M _{1 to} M _n is connected to a predetermined photodiode PD _{1 to} PD _n , the other node is commonly connected to a signal output line L _o , and each gate is further provided with a horizontal scanning circuit. Eleven scanning signals h _{1 to} h _n are supplied. The horizontal scanning circuit 11 is composed of a shift register that sequentially outputs scanning signals h _{1 to} h _n of logic “H” by shifting the start pulse signal ST in synchronization with the synchronization clock signal φ having a predetermined frequency. ing. Then, by MOSFET M ₁ ~M _n is turned in order in synchronization with the scanning signal h ₁ to h _n became logical "1", each pixel generated in the photodiodes PD ₁ -PD _n The signal δ is transferred in time series to the signal read line L _o .

The signal read line L _o is connected to an output amplifier which is formed by connecting a capacitive element C and a MOSFET 13 in parallel between the input and output contacts of the amplifier 12, and the output contact of the output amplifier is inverted by the comparator 14. It is connected to the input contact, and a predetermined threshold voltage V _ref is applied to the non-inverting input contact. The MOSFET 13 becomes conductive by the reset signal RS which becomes a logic “H” at a predetermined timing in synchronization with the horizontal scanning circuit 11 outputting each scanning signal h _{1 to} h _n , and the charge accumulation and discharge in the capacitive element C are performed. It is supposed to be done. The output contact of the comparator 14 is E
It is connected to one input contact of the XOR gate 15 and is also connected to the data transfer line L _b via the MOSFET q ₁ , and further is connected to the inverter 16 and the MOSFET q _2.
It is connected to the data transfer line L _a via. MO
The SFETs q ₁ and q ₂ become conductive when the switching control signal EB, which will be described later, becomes a logic “H”. Data transfer line L
_a and L _b are a memory unit 20 and a sense amplifier 17 which will be described later.
Is connected to the sense amplifier 17
Of the EXOR gate 15 is connected to the other input contact of the EXOR gate 15. The output contact of the EXOR gate 15 is connected to the data input contact of the D-type flip-flop 18, and the output data Q of the EXOR gate 15 is synchronized with the falling edge of the latch input signal CLK applied from the OR gate 19 to the clock input contact. 'Is latched and the latched data Q is output. The OR gate 19 generates the latch input signal CLK based on the logical sum of the scanning signals h _{1 to} h _n of the horizontal scanning circuit 11.

The memory section 20 has a storage capacity of n bits, and to describe the first storage bit as a representative, a pair of inverters G _1a and G ₁ having input and output contacts connected in a crossed manner. _1b , a MOSFET q _1a interposed between the input contact of one inverter G _1a and the data transfer line L _a , and a MOSFET q _1b interposed between the input contact of the other inverter G _1b and the data transfer line L _b. The scanning signal h ₁ is applied to the gates of the MOSFETs q _1a and q _1b via a signal line H ₁ extending from the horizontal scanning circuit 11. The other memory bits are also composed of SRAMs having the same structure, and each memory bit similarly has the remaining signal line H ₂ extending from the horizontal scanning circuit 11.
Scanning signals h _{2 to} h _n are applied via ~ H _n . Therefore, each storage bit of the memory unit 20 is associated with the arrangement of the photodiodes PD _{1 to} PD _n and the MOSFETs M _{1 to} M _{n in} the light receiving region 10 in a one-to-one relationship, and the scanning signals h _{1 to} h are associated with each other. _n also functions as an addressing signal for writing and reading these storage bits.

The operation of this embodiment will be described below with reference to the timing chart of FIG. In FIG. 2, the cycle T
_H is the photodiodes PD _{1 to} PD _n of the light receiving region 10.
The period T _CM is a period for reading out all the pixel signals generated in 1) in time series, and is a period for performing feature extraction of the subject. First, the photodiodes PD _{1 to} PD _n are exposed, the subject is imaged, and then the processing of the read cycle T _H is started, and the scanning signal h ₁ of each of the horizontal scanning circuits 11 is started.
~ H _n is sequentially set to logic "H" in synchronization with MOSF
The ET M _{1 to} M _n are sequentially turned on, and each pixel signal δ is transferred to the output amplifier via the signal read line L _o . The output amplifier impedance-converts a pixel signal e having a voltage proportional to the charge amount of each pixel signal δ and outputs the pixel signal e. Here, since the capacitive element C repeats charging and discharging in synchronization with the reset signal RS, the photodiode P
A time-series pixel signal e corresponding to each pixel signal δ of D _{1 to} PD _n is output. A comparator 14 compares these pixel signals e with a threshold voltage V _ref, and if e> V _ref, a logic “L”, and if e ≦ V _ref , a logic “H”.
The digitized data E is output. In the cycle T _H , the switching control signal EB becomes the logic “H” and the MOSFETs q ₁ and q ₂ are both in a conductive state, so that the binarized data E is on the data transfer line L _b and on the other hand, the data transfer line L the inverted data is transferred to _a. Further, in synchronization with the scanning signals h _{1 to} h _n , the SRAM of each storage bit of the memory unit 20 latches and stores the binarized data E.

As described above, in the period T _H , each pixel signal δ generated in the photodiodes PD _{1 to} PD _n is
Is converted into binary data E and stored in each storage bit of the memory unit 20. Each photodiode PD _{1 to} P
Since D _n is ready for exposure again immediately after transferring each pixel signal δ to the signal readout line L _o in synchronization with each scanning signal h _{1 to} h _n , all the photodiodes PD are PD.
The exposure time of _{1 to} PD _n is approximately equal to the cycle T _H.

Next, in the cycle T _CM , the switching control signal EB becomes logic "L", so that the MOSFETs q ₁ , q
₂ becomes non-conductive. The MOSFET is synchronized with the scanning signals h _{1 to} h _n from the horizontal scanning circuit 11.
The pixel signals δ generated in the photodiodes PD _{1 to} PD _n are generated by the M _{1 to} M _n being sequentially turned on.
Is read and further converted into binary data e via the output amplifier and the comparator 14. On the other hand, in synchronization with the scanning signal h ₁ to h _n data held in the storage bits of the memory unit 20 is transferred sequentially the data transfer line L _a, the L _b,
It is output by the sense amplifier 17. Therefore, E
The XOR gate 15 is sequentially provided with the photodiodes PD ₁
Synchronization with the binary data E corresponding supplied to -PD _n also becomes possible to hold data W is supplied from each of the bits stored in the memory unit 20, the logic when a relationship of E ≠ W The data to be "H", and the data Q'to be logic "L" when E = W are held in the D-type flip-flop 18 in synchronization with the latch signal LCK, and the latched data Q is sequentially Is output.

Here, since the latch data Q is the result of the exclusive OR by the EXOR gate 15, the period T _H
Is the difference data for each pixel in the same array of the past binarized data held in the memory unit 20 and the current binarized data read in the cycle T _CM , and is the feature data for each pixel of the subject. Becomes Therefore, according to this embodiment, the difference data can be obtained in synchronization with the reading of the pixel signal without performing the difference calculation based on the program control of the microprocessor or the like as in the related art, so that the processing speed is significantly improved. Will be done. Further, the light receiving area 1
0 scanning and addressing of the memory unit 20 are performed by scanning signals h ₁ to
with the improvement of the wiring density since the simultaneously performed by h _n is achieved, addressing programmatic control of the application of the conventional RAM improves the processing speed becomes unnecessary. In this embodiment, since the circuit shown in FIG. 1 is integrally formed in the same semiconductor chip, a small image processing device is realized with the improvement of the wiring density and the omission of various circuits for addressing. I was able to do it. Further, since the pixel signal δ is integrated by the output amplifier and the impedance is converted into the voltage pixel signal e, an image processing apparatus having a good noise resistance characteristic can be applied.

Next, another embodiment will be described with reference to FIGS.
To do. First, the configuration will be described with reference to FIG. In addition, in FIG.
The same or corresponding parts as in FIG.
There is. This is a matrix of vertical and horizontal directions.
Dimensionally arranged photodiode PD₁₁~ PD_mnPick
Cell group, each photodiode PD₁₁~ PD_mnTo
MOSFET m provided in association₁₁~ M_mnOne side
Node of each photodiode PD₁₁~ PD_mnContact
Connected to the other node with the other node vertically aligned.
Vertical signal read line V provided corresponding to the ion group₁~
V_nEach is commonly connected. Furthermore, along the horizontal direction
The vertical scanning circuit 21 is provided for each gate of the MOSFETs arranged in a line.
Vertical scanning signal v output from₁~ V_mIs applied
Has been done. Further, each of the vertical signal read lines V₁~ V
_nEach end of MOSFET M₁~ M_nDrain So
Horizontal signal read line L_oConnected to each M
OSFET M₁~ M_nThe gate of the horizontal scanning circuit 2
The horizontal scanning signal h output from 2₁~ H_nMark
It is wired to be added. The horizontal scanning circuit 21
Is the start pulse signal S_HThe clock signal of a predetermined frequency
No. φ_HThe horizontal scanning is performed by shifting in synchronization with
Signal h₁~ H_nConsists of a shift register that outputs
Then, the vertical scanning circuit 22 outputs the start pulse signal S_VTo
Clock signal φ of specified frequency_VShift operation in synchronization with
Vertical scanning signal v₁~ V_mOutput
And a horizontal scanning circuit 22.
Is the horizontal scanning signal h₁~ H_nEach time you output
The vertical scanning circuit 21 is operated so that the shift operation is performed once.
Clock signal φ_HAnd φ_VFrequency is set.
Horizontal signal read line L_oIs, for example, the input / output contact of the amplifier 12.
The capacitor C and the MOSFET 13 are connected in parallel between
Connected to the output amplifier of
The point is connected to the inverting input contact of the comparator 14 and its non-inverting
The input contact has a predetermined threshold voltage V_refIs being applied.
In the MOSFET 13, the horizontal scanning circuit 22 is a horizontal scan circuit.
Signal h₁~ H_nThe specified timing synchronized with the output of
The reset signal RS that becomes a logic "H"
The capacitor C is turned on and the capacitor C is allowed to accumulate and discharge.
It has become so. The output contact of the comparator 14 is EXO
It is connected to one input contact of the R gate 15 and
OSFET q₁Data transfer line L via_bConnect to
Furthermore, the inverter 16 and the MOSFET q₂Through
Data transfer line L_aConnected to. In addition, MOSFET
q₁, Q₂Indicates that the switching control signal EB, which will be described later, is a logical "H".
Becomes conductive. Data transfer line L _a, L
_bConnects the memory unit and the sense amplifier 17 described later.
Output wire of the sense amplifier 17
Is connected to the other input contact of the EXOR gate 15.
It EX at the data input contact of the D-type flip-flop 18
The output contact of the OR gate 15 is connected, and the OR gate 19 is connected.
Input signal CL applied to the clock input contact from
In synchronization with the falling edge of K, the EXOR gate 15
Latch the output data Q'and output the latched data Q
To do. The OR gate 19 scans from the horizontal scanning circuit 22.
Signal h₁~ H_nLatch input signal based on the logical sum of
Generate CLK.

In the memory portion, m × n S elements arranged corresponding to the photodiodes PD _{11 to} PD _mn in the light receiving area.
A storage bit consisting of RAM is formed. That is, to describe the first memory bit as a representative, a pair of inverters G _11a and G _11b whose input and output contacts are connected in a crossed manner.
And a MOSFET q _11a interposed between the input contact of one inverter G _11a and the data transfer line L _1a , and a MOSFET q _11b interposed between the input contact of the other inverter G _11b and the data transfer line L _1b. The scanning signal h ₁ is applied to the gates of the MOSFETs q _11a and q _11b via a signal line H ₁ extending from the horizontal scanning circuit 22. The remaining n-1 bits formed in the horizontal direction have the same SR.
It is composed of AM. The horizontal scanning signals h _{2 to} h _n output from the horizontal scanning circuit 22 are sequentially applied to these n−1 storage bits, and at the same time, they are connected to the data transfer lines L _1a and _1b , and the data transfer line L _1a is connected to the data transfer line L _a via a MOSFET N _1a which becomes conductive / non-conductive in synchronization with the vertical scanning signal v ₁ from the vertical scanning circuit 21, and the data transfer line L _1b is connected to the vertical scanning circuit 21. Is connected to the data transfer line L _b via a MOSFET N _1b which becomes conductive / non-conductive in synchronization with the vertical scanning signal v ₁ from

The n storage bits arranged and formed in the second column in the vertical direction have the same structure as the SRAM in the first column and are connected to the data transfer lines L _2a and L _2b , and Horizontal scanning signal h ₁ from the horizontal scanning circuit 22
Controlled by ~ h _n . Furthermore, the data transfer line L
_2a is a vertical scanning signal v from the vertical scanning circuit 21.
_The data transfer line L _2b is connected to the data transfer line L _a through the MOSFET N _2a that becomes conductive / non-conductive in synchronization with
Is a vertical scanning signal v ₂ from the vertical scanning circuit 21.
It is connected to the data transfer line L _b through a MOSFET N _2b which becomes conductive / non-conductive in synchronization with the.

Hereinafter, the memory bits arranged and formed in the remaining columns in the vertical direction are also the SRAMs in the first and second columns.
N storage bits arranged and formed in the last column are connected to the data transfer lines L _ma and L _mb , and the horizontal scanning signals h ₁ to h ₁ -from the horizontal scanning circuit 22. Controlled by h _n , the data transfer line L _ma is turned on / off in synchronization with the vertical scanning signal v _m from the vertical scanning circuit 21.
_The MOSFET N _mb is connected to the data transfer line L _a via _ma , and the data transfer line L _mb becomes conductive / non-conductive in synchronization with the vertical scanning signal v _m from the vertical scanning circuit 21.
It is connected to the data transfer line L _b via.

Thus, m formed in the light receiving region
Corresponding to the × n photodiodes PD _{11 to} PD _mn ,
M × n storage bits formed of SRAM are formed in the storage unit.

Next, the operation of this embodiment will be described with reference to FIGS.
The timing chart will be described. In addition, FIG.
M × n photodiodes PD _{11 to} PD _{mn in the} light receiving region
Represents a reading period for one frame image in which the pixel signals generated in the above are sequentially read and stored in the storage bits of the storage unit, and the cycle T _H is each pixel signal of n photodiodes arranged in each horizontal direction. 5 is a horizontal scanning period in which the pixel signals for the next one frame are read from the photodiodes PD _{11 to} PD _{mn in} the light receiving area, and at the same time, are stored in the storage bits of the storage unit. A period during which the stored data of the preceding one-frame image is read and the feature of the subject is extracted is shown.

[0023] First, in FIG. 4, a period T vertical scanning signal the vertical scanning circuit 21 for each _H v ₁ to v _m will invert the logic "H", the horizontal scanning circuit 22 is horizontal in the period of the respective T _H Scanning signals h _{1 to} h _n are logically “H”
The operation of reversing to is repeated. Further, the switching control signal EB is always held at logic "H".

Therefore, in the first period T _H , the MOSFET M is synchronized with the horizontal scanning signals h _{1 to} h _{n.
When 1 to} M _n are sequentially turned on, the pixel signals δ generated in the photodiodes PD _{11 to} PD _1n in the first column in the vertical direction are sequentially transferred to the output amplifier, and the voltage of each pixel is changed. The pixel signal e is converted and supplied to the comparator 14. The comparator 14 outputs the binary data E of logic "L" when e> V _ref , and outputs the binary data E of logic "H" when _{e≤V ref} . Here, the switching control signal EB is logic "H", and the MOSFETs q ₁ and q ₂
Are turned on, the binarized data E is transferred to the data transfer line L _b, and the inverted data of the binarized data E is transferred to the data transfer line L _a . Furthermore, MOSFET
Since N _1a and N _1b are turned on by the vertical scanning signal v ₁ of logic “H”, the data transfer lines L _1a and L _1a ,
These binarized data are transferred to the storage bit in the first column of the storage unit via L _1b . Then, the horizontal scanning circuit 22
The horizontal scanning signals h _{1 to} h _n sequentially become logical “H”, whereby the binarized data E is stored as pixel data in the storage bit in the first column.

In the next period T _H , only the vertical scanning signal v ₂ becomes the logic “H” and the horizontal scanning signals h _{1 to} h _n become the logic “H” in sequence,
Second-row photodiodes PD _{21 to} PD in the light-receiving region
Each pixel signal δ generated in _2n is sequentially read, and at the same time, the binarized data E corresponding to the pixel signal δ is stored in the storage bit of the second column in the storage unit.

Then, each pixel signal δ generated in the photodiodes of the remaining columns is similarly read out, and at the same time, these pixel signals δ are stored in the storage bits of the corresponding column.
The binary data E corresponding to is stored, and the binary data E corresponding to each pixel signal δ read from the photodiodes PD _{m1 to} PD _mn in the final column is stored in the storage bit of the final column in the storage unit. Remembered.

Next, in FIG. 5, the switching control signal EB becomes logic "L", so that the MOSFETs q ₁ , q
₂ is made both non-conductive, and the horizontal scanning circuit 22 a vertical scanning circuit 21 outputs a horizontal scanning signal h ₁ to h _n and the vertical scanning signal v ₁ to v _m in the same timing as FIG. Therefore, the binarized data E corresponding to the pixel signals of the photodiodes that are in a mutually corresponding relationship and the respective held data W of the memory bits are simultaneously read out and EX
The exclusive OR data Q ′ supplied to the OR gate 15
Is a D-type flip-flop 1 in synchronization with the latch signal CLK.
8 and latched data Q is output. Then, m × n photodiodes PD _{11 to} PD
_With respect to each pixel signal from _mn and the held data from m × n storage bits, the exclusive OR processing is performed for each pixel, so that the difference data for one frame image is output from the D-type flip-flop 18. Will be done.

As described above, according to this embodiment, the difference data can be obtained in synchronization with the reading of the pixel signal without performing the difference calculation based on the program control of the microprocessor or the like as in the conventional case. Is greatly improved. Further, in this embodiment, the light receiving area, the storage section, the horizontal scanning circuit and the vertical scanning circuit shown in FIG. 3, and the signal processing section for arithmetically processing signals output from these and outputting differential data are the same. Since it is formed integrally with the semiconductor chip,
With the improvement of wiring density, it has become possible to provide a small-sized image processing device.

By alternately repeating the processing shown in FIG. 4 and the processing shown in FIG. 5, it is possible to sequentially obtain the differential data for one frame from the image data for two frames. However, this is an example of the operation, and by appropriately controlling the logic of the switching control signal EB, the MOSF
By controlling the conducting / non-conducting states of ET q ₁ and q ₂ , other processing becomes possible. For example, if the process shown in FIG. 4 is performed only during the first one-frame image reading period and the process shown in FIG. 5 is repeated thereafter, the data is stored in the storage unit during the first one-frame image reading period. Based on the held data, it is possible to obtain the difference data from the pixel signal read from each photodiode in the storage area thereafter. By performing this processing, it is possible to perform image processing for obtaining a difference from the subject image read from each photodiode in the storage area thereafter, with the pixel data corresponding to the reference subject image as a reference. Become.

Further, in this embodiment, the vertical scanning circuit 21
Although the shift register is applied to the horizontal scanning circuit 22, the random access decoder may be applied to randomly scan the photodiodes PD _{11 to} PD _mn and the storage bits. By applying the random access decoder in this way, it is possible to selectively perform processing of a desired image portion, and it is possible to improve the function.

[0031]

As described above, according to the present invention, the photodiode group in the light receiving area and the storage bit in the storage section are scanned by the same scanning signal, so that each bit in the storage section is addressed. The means can be omitted, and simplification of the device can be realized. Further, the difference data corresponding to the pixel array can be EXORed only by scanning the photodiode group and the memory bit, without the conventional program control by the MPU.
Since it is output from the gate, the processing speed is improved.
Further, by controlling the switching means in accordance with the switching control signal, the data once held in the memory bit can be read and processed any number of times, which has the effect that the range of application to signal processing technology is wide. There is.

[Brief description of drawings]

FIG. 1 is a configuration explanatory diagram showing a configuration of an embodiment according to the present invention.

FIG. 2 is a timing chart for explaining an operation example of one embodiment.

FIG. 3 is a configuration explanatory view showing a configuration of another embodiment according to the present invention.

FIG. 4 is a timing chart for explaining an operation example of another embodiment.

FIG. 5 is a timing chart for further explaining an operation example of another embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional image processing apparatus.

[Explanation of symbols]

10 ... Light receiving area, 11 ... Horizontal scanning circuit, 12 ... Amplifier,
13 ... MOSFET, 14 ... Comparator, 15 ... EXOR gate, 16 ... Inverter, 17 ... Sense amplifier, 18 ...
D-type flip-flop, 19 ... OR gate, 20 ... Storage unit, 21 ... Vertical scanning circuit, 22 ... Horizontal scanning circuit, M ₁ to
_{M n, q 1, q 2} , q 1a ~q nb, m 11 ~m mn, N 1a ~N
_mb , q _{11a to} q _mnb ... MOSFET, C ... Capacitance element, L
_o ... horizontal signal read line, V ₁ ~V _n ... vertical signal read lines, G
_{1a to} G _nb , G _{11a to} G _mnb ... Inverter.

Claims (4)

[Claims] 1. A photodiode group corresponding to a pixel group arranged one-dimensionally, a switching element group interposed between each photodiode and a signal read line, and conduction / non-conduction of each switching element. A horizontal scanning circuit that transfers a pixel signal generated in a photodiode to a signal reading line through a switching element in a conductive state by outputting a scanning signal that is selectively controlled, and a storage bit as many as the photodiode group are stored. A storage unit that has a storage unit that writes or reads data to or from a storage bit designated by a scanning signal output by the horizontal scanning circuit; and a pixel signal of the signal readout line that is connected to the end of the signal readout line. An output amplifier for converting into a pixel signal, and a pixel signal of a voltage output from the output amplifier is set to a predetermined value. A comparator for converting into binary data for each pixel by comparing with a value voltage, and the binary data output from the comparator is transferred or non-transferred to the storage unit based on the switching control signal, and at the time of transfer Switching means for writing the binarized data in the storage unit and reading the data in the non-transfer state, and EXOR for performing an exclusive OR operation of the binarized data output from the comparator and the data output from the storage unit. An image processing apparatus comprising: a gate. 2. A photodiode group corresponding to a pixel group two-dimensionally arranged in a matrix in the horizontal and vertical directions, and a vertical signal read line provided corresponding to the photodiode group arranged in the vertical direction. A first switching element group interposed between the group and a vertical signal read line corresponding to each photodiode, and a second switching element interposed between the end of each vertical signal read line and the horizontal signal read line. And a pixel generated in the photodiode by outputting a vertical scanning signal for selectively controlling conduction / non-conduction for each switching element group of the first switching element group and the switching elements arranged in the horizontal direction of the first switching element group. A vertical scanning circuit for transferring a signal to a vertical signal read line through a conductive switching element, and a switch for the second switching element group. A horizontal scanning circuit for transferring the pixel signal of the vertical signal read line to the horizontal signal read line through the conductive switching element by outputting a horizontal scanning signal for selectively controlling conduction / non-conduction for each scanning element. A storage unit having the same number of storage bits as the photodiode group, for writing or reading data to or from the storage bits designated by the scanning signals output from the vertical scanning circuit and the horizontal scanning circuit; An output amplifier connected to the end of the signal output line for converting the pixel signal of the horizontal signal readout line into a pixel signal of a voltage, and comparing the pixel signal of the voltage output from the output amplifier with a predetermined threshold voltage. A comparator for converting into binary data for each pixel, and the binary data output from the comparator based on the switching control signal. Storage means for transferring or non-transferring to the storage portion, writing binary data in the storage portion at the time of transfer, and reading data at the time of non-transfer, and binarized data output from the comparator and output from the storage portion. And an EXOR gate for performing an exclusive OR operation with the data. 3. The horizontal scanning circuit or the vertical scanning circuit,
The image processing apparatus according to claim 1 or 2, comprising a shift register. 4. The horizontal scanning circuit or the vertical scanning circuit,
The image processing apparatus according to claim 1 or 2, comprising a random access decoder.