JPH0697281A - Electrode wiring structure of semiconductor device - Google Patents
Electrode wiring structure of semiconductor deviceInfo
- Publication number
- JPH0697281A JPH0697281A JP4243285A JP24328592A JPH0697281A JP H0697281 A JPH0697281 A JP H0697281A JP 4243285 A JP4243285 A JP 4243285A JP 24328592 A JP24328592 A JP 24328592A JP H0697281 A JPH0697281 A JP H0697281A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- wiring
- wiring layer
- aluminum
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000470 constituent Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 52
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 51
- 238000000034 method Methods 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置（以後、Ｉ
Ｃと記す）に関し、特に多層の電極配線構造に関する。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device (hereinafter referred to as I
C), and particularly to a multilayer electrode wiring structure.
【０００２】[0002]
【従来の技術】従来のＩＣにおいては、電極配線はアル
ミ等の金属配線層を１層又は２層使用し、配線を行って
いた。また、この金属配線層は信号配線にも使用されて
いた。2. Description of the Related Art In a conventional IC, electrode wiring is performed by using one or two metal wiring layers such as aluminum. Further, this metal wiring layer was also used for signal wiring.
【０００３】１層の金属配線層（アルミ）を使用した時
の従来例を図３に示す。ＩＣチップ２００上に内部素子
（トランジスタ）領域２０４が配置され、内部素子間が
信号アルミ配線２０５又は信号ポリシリコン配線２０６
で接続されている。２０３はボンディングパッドであ
る。FIG. 3 shows a conventional example in which one metal wiring layer (aluminum) is used. An internal element (transistor) region 204 is arranged on the IC chip 200, and a signal aluminum wiring 205 or a signal polysilicon wiring 206 is provided between the internal elements.
Connected by. 203 is a bonding pad.
【０００４】また内部素子へ電力を供給するための接地
及び電源の２種の電極アルミ配線２０１，２０２が配線
されている。電極アルミ配線及び信号アルミ配線は、同
一のアルミ配線層を使用している。そのため、信号アル
ミ配線，電源アルミ配線は、それぞれ自由に配線できる
のではなく互いに制限を及ぼしながら混在している。Further, two kinds of electrode aluminum wirings 201 and 202 for grounding and power supply for supplying electric power to the internal elements are wired. The same aluminum wiring layer is used for the electrode aluminum wiring and the signal aluminum wiring. Therefore, the signal aluminum wiring and the power aluminum wiring cannot be freely wired, but are mixed while limiting each other.
【０００５】図４は、図３のＣ−Ｃ′線断面図である。
２０６は信号ポリシリコン配線，２０７はポリシリコン
−アルミ配線間絶縁膜，２０８はパッシベーション用絶
縁膜である。接地及び電源電位の２種の電極アルミ配線
は同一のアルミ配線層で形成されており、同一の平面
（高さ）上にある。これは信号アルミ配線についても同
様である。FIG. 4 is a sectional view taken along the line CC 'of FIG.
Reference numeral 206 is a signal polysilicon wiring, 207 is a polysilicon-aluminum wiring insulating film, and 208 is a passivation insulating film. The two types of electrode aluminum wirings, that is, the ground and the power supply potential, are formed of the same aluminum wiring layer and are on the same plane (height). This also applies to the signal aluminum wiring.
【０００６】[0006]
【発明が解決しようとする課題】この従来ＩＣの電極配
線では、電極アルミ配線，信号アルミ配線が同一平面上
にあるため、自由な配線が互いにできず、充分な電極ア
ルミ線幅が確保できず、電極に抵抗が付くため、ＩＣの
電気特性に悪影響を与えるという問題点があった。In the electrode wiring of this conventional IC, since the electrode aluminum wiring and the signal aluminum wiring are on the same plane, free wiring cannot be performed with each other and a sufficient electrode aluminum line width cannot be secured. However, since the electrodes have resistance, there is a problem that the electric characteristics of the IC are adversely affected.
【０００７】アルミ配線は、きわめて低抵抗であるが、
電極アルミ配線幅は通常数１０μｍ〜１００μｍ程度ま
でしかとれないため、１０ｍｍ程度配線すると、１０Ω
（ρS＝０．１Ω／□）程度の抵抗が付く。この配線に
数１０ｍＡの電流が流れて数１００ｍＶの電圧降下が起
こる。この程度の電圧降下でも、ＩＣへの入出力回路で
は電気特性に大きな影響があり、ＩＣの設計，製造上の
大きな問題となっている。Aluminum wiring has a very low resistance,
The width of the aluminum electrode wiring is usually several tens of μm to 100 μm.
It has a resistance of (ρ S = 0.1Ω / □). A current of several tens of mA flows through this wiring and a voltage drop of several hundred mV occurs. Even such a voltage drop has a great influence on the electrical characteristics of the input / output circuit to the IC, which is a big problem in the design and manufacturing of the IC.
【０００８】本発明の目的は、電源ＧＮＤのアルミ配線
に電流が流れることにより生じる電圧降下を低減させた
半導体装置の電極配線構造を提供することにある。An object of the present invention is to provide an electrode wiring structure of a semiconductor device in which a voltage drop caused by a current flowing through an aluminum wiring of a power supply GND is reduced.
【０００９】[0009]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置の電極配線構造は、信号配
線層と、電極配線層とを有する半導体装置の電極配線構
造であって、信号配線層は、半導体装置の構成素子間を
配線するものであり、電極配線層は、信号配線層上に相
互に絶縁されて２層構造として設けられ、２層構造の配
線層が接地電極と電源電極に接続されたものである。To achieve the above object, an electrode wiring structure of a semiconductor device according to the present invention is an electrode wiring structure of a semiconductor device having a signal wiring layer and an electrode wiring layer. The wiring layer is for wiring between the constituent elements of the semiconductor device, and the electrode wiring layer is provided on the signal wiring layer so as to be insulated from each other to have a two-layer structure, and the wiring layer having the two-layer structure has a ground electrode and a power supply. It is connected to the electrodes.
【００１０】[0010]
【作用】電極配線用として２層の配線層を備えている。
この２層の配線層が接地電極と電源電極となる。このこ
とにより、従来制限されていた電源線の幅を広げて電源
線の電圧降下を防ぐことができる。Function: Two wiring layers are provided for electrode wiring.
The two wiring layers serve as a ground electrode and a power electrode. As a result, the width of the power supply line, which has been conventionally limited, can be widened to prevent the voltage drop of the power supply line.
【００１１】[0011]
【実施例】次に本発明について図面を参照して説明す
る。図１は、本発明の一実施例を示す平面図、図２
（ａ）は図１のＡ−Ａ′線断面図、（ｂ）は図１のＢ−
Ｂ′線断面図である。The present invention will be described below with reference to the drawings. 1 is a plan view showing an embodiment of the present invention, FIG.
1A is a sectional view taken along the line AA ′ of FIG. 1, and FIG.
It is a B'line sectional drawing.
【００１２】図１において、半導体チップ１００上に
は、内部素子領域１０４，信号ポリシリコン配線１０
６，第１のアルミ配線層（信号アルミ配線）１０５を形
成する。ここまでは従来のＩＣチップと変りはない。In FIG. 1, an internal element region 104 and a signal polysilicon wiring 10 are formed on a semiconductor chip 100.
6, a first aluminum wiring layer (signal aluminum wiring) 105 is formed. Up to this point, it is no different from the conventional IC chip.
【００１３】本発明では上記構造上にＳｉＯ2等の絶縁
膜１１１を形成する。次にホトリソグラフィ技術を用い
て絶縁膜１１１に第１のスルーホール１０９を設ける。
第１のスルーホール１０９は、第１のアルミ配線層１０
５と後述の第２のアルミ配線層１０１を電気的に接続す
るものである。１０３はボンディングパッドである。さ
らに絶縁膜１１１上には第２のアルミ配線層１０１を形
成し、ホトリソグラフィ技術を用いてパターンニングを
行う。この際、アルミのパターンとしては、なるべく広
範囲に形成する。In the present invention, an insulating film 111 such as SiO 2 is formed on the above structure. Next, the first through hole 109 is provided in the insulating film 111 by using the photolithography technique.
The first through hole 109 is the first aluminum wiring layer 10
5 and a second aluminum wiring layer 101 described later are electrically connected. 103 is a bonding pad. Further, the second aluminum wiring layer 101 is formed on the insulating film 111, and patterning is performed using the photolithography technique. At this time, the aluminum pattern is formed as widely as possible.
【００１４】次に第２のアルミ配線層１０１を含む領域
上にＳｉＯ2等の絶縁膜１１２を形成し、絶縁膜１１２
上に第２のスルーホール１１０を設ける。第２のスルー
ホール１１０は、第１のアルミ配線層１０５と後述の第
３のアルミ配線層１０２とを電気的に接続するものであ
る。Next, an insulating film 112 of SiO 2 or the like is formed on the region including the second aluminum wiring layer 101, and the insulating film 112 is formed.
A second through hole 110 is provided on the top. The second through hole 110 electrically connects the first aluminum wiring layer 105 and a third aluminum wiring layer 102, which will be described later, to each other.
【００１５】次に絶縁膜１１２上に第３のアルミ配線層
１０２を形成しホトリソグラフィ技術を用いてパターン
ニングを行う。この際、アルミのパターンとしては第２
のアルミ配線層と同様になるべく広範囲に形成する。こ
こに、第２アルミ配線層１０１は電極電位となり、第３
アルミ配線層１０２は接地電位となる。尚、電位の関係
は、逆であってもよい。Next, a third aluminum wiring layer 102 is formed on the insulating film 112 and patterned by using the photolithography technique. At this time, the second aluminum pattern
The aluminum wiring layer is formed as widely as possible. Here, the second aluminum wiring layer 101 has an electrode potential,
The aluminum wiring layer 102 has a ground potential. The potential relationship may be reversed.
【００１６】内部素子領域１０４への電源，接地電極の
配線は次のように行われる。電源電位電極の配線は第２
アルミ配線層１０１より第１スルーホール１０９を介し
て第１アルミ配線層の電源電位電極配線１０７に接続さ
れ、この第１アルミ配線により内部素子領域に配線され
る。Wiring of the power source and the ground electrode to the internal element region 104 is performed as follows. The power supply potential electrode wiring is second
The aluminum wiring layer 101 is connected to the power supply potential electrode wiring 107 of the first aluminum wiring layer via the first through hole 109, and is wired to the internal element region by this first aluminum wiring.
【００１７】接地電位電極の配線は、第３アルミ配線層
１０２より第２スルーホール１１０を介して第１アルミ
配線層の接地電位電極配線１０８に接続され、この第１
アルミ配線により内部素子領域に配線される。The wiring of the ground potential electrode is connected from the third aluminum wiring layer 102 to the ground potential electrode wiring 108 of the first aluminum wiring layer through the second through hole 110.
It is wired in the internal element area by aluminum wiring.
【００１８】従来のＩＣでは、第１アルミ配線層１０
７，１０８の配線がボンディングパッドより数ｍｍ程度
の長さで配線されるため、１０Ω程度の抵抗値を有して
いた。In the conventional IC, the first aluminum wiring layer 10 is used.
Since the wirings 7, 108 are wired with a length of several mm from the bonding pad, they had a resistance value of about 10Ω.
【００１９】これに対して本発明では、十分に広い幅が
とれる第２，第３アルミ配線層により配線されるため、
正方形に近いチップの場合、前記の配線も正方形に近い
形にでき、この部分の抵抗はρS（０．１０Ω／□以
下）程度にできる。On the other hand, in the present invention, the wiring is performed by the second and third aluminum wiring layers which can have a sufficiently wide width.
In the case of a chip close to a square, the wiring can also be formed into a shape close to a square, and the resistance of this portion can be about ρ S (0.10 Ω / □ or less).
【００２０】第１アルミ配線層についても１ｍｍ程度で
済むため、全体としては１Ω以下にすることが可能であ
る。１Ω以下にすることにより、数十ｍＡの電流が流れ
ても電圧降下を０．１Ｖ以下にすることができる。この
程度であれば、ＩＣの入出力回路への影響は問題になら
ない。Since the thickness of the first aluminum wiring layer is about 1 mm, it is possible to reduce the total resistance to 1Ω or less. By setting the resistance to 1 Ω or less, the voltage drop can be set to 0.1 V or less even when a current of several tens of mA flows. At this level, the influence on the input / output circuit of the IC does not matter.
【００２１】他の実施例としては、第２アルミ配線層と
第３アルミ配線層の間の絶縁膜を強誘電体にすることに
より、電源電位電極−接地電位電極間の容量を大きくで
きる。この容量が大きくなると、電極配線にパルス電流
が流れた時、ある程度吸収でき、電圧降下を小さくでき
るという利点がある。In another embodiment, by using an insulating film between the second aluminum wiring layer and the third aluminum wiring layer as a ferroelectric material, the capacitance between the power supply potential electrode and the ground potential electrode can be increased. When this capacitance becomes large, there is an advantage that when the pulse current flows through the electrode wiring, it can be absorbed to some extent and the voltage drop can be made small.
【００２２】[0022]
【発明の効果】以上説明したように本発明は、電源接地
電極専用のアルミ配線層を２層有することにより、電極
配線を広範囲に全面的に形成することが可能となり、電
極の配線抵抗を１Ω以下のきわめて低い値にすることが
できる。As described above, according to the present invention, by having two aluminum wiring layers dedicated to the power supply ground electrode, the electrode wiring can be formed over a wide area and the wiring resistance of the electrode is 1Ω. It can have the following very low values:
【図１】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.
【図２】（ａ）は図１のＡ−Ａ′線断面図、（ｂ）は図
１のＢ−Ｂ′線断面図である。2A is a sectional view taken along the line AA ′ of FIG. 1, and FIG. 2B is a sectional view taken along the line BB ′ of FIG.
【図３】従来例を示す平面図である。FIG. 3 is a plan view showing a conventional example.
【図４】図３のＣ−Ｃ′線断面図である。FIG. 4 is a sectional view taken along the line CC ′ of FIG.
１００ 半導体チップ（基板） １０１ 第２アルミ配線層 １０２ 第３アルミ配線層 １０３ ボンディングパッド １０４ 内部素子領域 １０５ 第１アルミ配線層 100 Semiconductor Chip (Substrate) 101 Second Aluminum Wiring Layer 102 Third Aluminum Wiring Layer 103 Bonding Pad 104 Internal Element Area 105 First Aluminum Wiring Layer
Claims (1)
導体装置の電極配線構造であって、 信号配線層は、半導体装置の構成素子間を配線するもの
であり、 電極配線層は、信号配線層上に相互に絶縁されて２層構
造として設けられ、２層構造の配線層が接地電極と電源
電極に接続されたものであることを特徴とする半導体装
置の電極配線構造。1. An electrode wiring structure of a semiconductor device having a signal wiring layer and an electrode wiring layer, wherein the signal wiring layer is for wiring between constituent elements of the semiconductor device, and the electrode wiring layer is a signal wiring layer. An electrode wiring structure for a semiconductor device, wherein the wiring layer is provided as a two-layer structure insulated from each other on a wiring layer, and the wiring layer having a two-layer structure is connected to a ground electrode and a power supply electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4243285A JPH0697281A (en) | 1992-09-11 | 1992-09-11 | Electrode wiring structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4243285A JPH0697281A (en) | 1992-09-11 | 1992-09-11 | Electrode wiring structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0697281A true JPH0697281A (en) | 1994-04-08 |
Family
ID=17101581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4243285A Pending JPH0697281A (en) | 1992-09-11 | 1992-09-11 | Electrode wiring structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0697281A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0864768A (en) * | 1994-08-18 | 1996-03-08 | Nec Corp | Semiconductor integrated circuit device |
| JPH08124928A (en) * | 1994-10-21 | 1996-05-17 | Nec Corp | Semiconductor integrated circuit |
-
1992
- 1992-09-11 JP JP4243285A patent/JPH0697281A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0864768A (en) * | 1994-08-18 | 1996-03-08 | Nec Corp | Semiconductor integrated circuit device |
| JPH08124928A (en) * | 1994-10-21 | 1996-05-17 | Nec Corp | Semiconductor integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4654689A (en) | Structure of power supply wirings in semiconductor integrated circuit | |
| JPH061802B2 (en) | Semiconductor device | |
| JPH0697281A (en) | Electrode wiring structure of semiconductor device | |
| JP2752832B2 (en) | Semiconductor integrated circuit device | |
| JPS6329962A (en) | Semiconductor device | |
| JP2778235B2 (en) | Semiconductor device | |
| JPS6127691A (en) | Internal wiring structure of magnetoresistance element | |
| JPH0728004B2 (en) | Semiconductor integrated circuit device | |
| JPH065784A (en) | Input protection circuit | |
| JPS62165362A (en) | Semiconductor integrated circuit device | |
| JPH0888319A (en) | Semiconductor integrated circuit | |
| JPS605055B2 (en) | semiconductor equipment | |
| JPH04286150A (en) | Semiconductor integrated circuit device | |
| JPS63124539A (en) | Hybrid integrated circuit | |
| JP2901280B2 (en) | Semiconductor device | |
| JPH0429320A (en) | Semiconductor device | |
| JPH04249325A (en) | Semiconductor integrated circuit | |
| JPS63304645A (en) | Semiconductor integrated circuit | |
| JPH025416A (en) | Semiconductor integrated circuit device | |
| JPS6154646A (en) | Wiring of semiconductor device | |
| JPH02177451A (en) | Semiconductor integrated circuit device | |
| JPH02126641A (en) | Semiconductor device | |
| JPH01283896A (en) | Hybrid integrated circuit | |
| JPS62274654A (en) | Input protection device | |
| JPH0620111B2 (en) | Monolithic IC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |