JPH0697408A - Photoelectric conversion device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a photoelectric conversion device which prevents the generation of noise due to dark current of a photoelectric conversion cell and eliminates its noise thus induced and a manufacturing method for the device. CONSTITUTION:There are continuously laid out without any gap a high concentration impurity area 52 and a high concentration impurity area 34 under a light receiving part in a photoelectric conversion device which is equipped with a plurality of bipolar photoelectric conversion cells, with a high concentration impurity area, higher in concentration than a collector area of the bipolar transistor which constitutes the photoelectric conversion cell and the same conductivity type in the area 52 under an insulating film 51 in an element isolation area between the photoelectric conversion cells and in the area 34 under an insulating film 35 of the light receiving part.

Description

Detailed Description of the Invention

According to the present invention, a plurality of photoelectric conversion elements are arranged,
A photoelectric conversion device for controlling each photoelectric conversion element by a driving pulse and a manufacturing method thereof, in particular, by controlling a potential of a control electrode of a transistor, carriers generated by photoexcitation are accumulated in the control electrode region, and a storage voltage thereof is stored. The present invention relates to a photoelectric conversion device having a bipolar photoelectric conversion cell that performs an operation of reading out data and removing accumulated carriers.

[0002]

2. Description of the Related Art (Prior Art A) FIG. 5 is a part of a circuit diagram of a photoelectric conversion device described in Japanese Patent Publication No. 1-222583 as an example of a conventional photoelectric conversion device.

In FIG. 5, 1 _-1 to 1 _-n are storage type phototransistor arrays (cells), a common power source is connected to the collectors thereof, and photoelectrically converted charges are stored in a control electrode region (base). It has a structure in which it can be stored and read out from the main electrode region (emitter), and its specific contents are, for example, JP-A-62-128678, JP-A-62-113468, and JP-A-61-168286. ,
Japanese Patent Application No. 61-219668, Japanese Patent Application No. 61-21966
No. 9 etc. have detailed description.

2 _{−1 to} 2 _{−n denote} the bases of the bipolar transistors forming the phototransistor array 1 by φ.
A PMOS switch for connecting to the power supply V _C and resetting when _res is given, 3 _{-1 to} 3 _-n are connected to respective emitters of the bipolar transistor and the accumulated signal is synchronized with φ _t in the subsequent stage. The NMOS switches 4 _-1 to 4 _-n for taking out the image signals to the A / D converter are connected in series to the NMOS switches 3 _{-1 to} 3 _-n , respectively.

5 _{-1 to} 5 _-n are NMOS switches 3 _{-1 to} 3
_-n and a storage capacitor for reading out the signal for each pixel connected between each connection point of 4 _-1 to 4 _-n and the ground, 6 is an NMOS switch 4 _-1 to 4 _-n sequentially turned on A shift register for sequentially reading image signals.

Reference numeral 8 is an NMOS switch for grounding and initializing the read line 7 to which the output terminals of the NMOS switches 4 _-1 to 4 _-n are commonly connected, when the signal φ _hrs is applied. output amplifier, NMOS switches for grounding the respective emitters of the photo transistor array 1 _-1 to 1 _-n when 10 _-1 to 10 _-n are given the phi _vrs for amplifying the image signal output to the line 7 Is.

FIG. 6 is a timing chart for explaining the operation of the photoelectric conversion element array of FIG.

As shown in FIG. 6, first, reset is performed. By turning _φres to a low level and turning on the PMOS switches 2 _-1 to 2 _-n in the period from time t _{1 to} t ₂ , the bases of the phototransistor arrays (hereinafter, referred to as pixel columns) 1 _-1 to 1 _-n are changed. It is fixed at the potential of V _C.

Next, in the period from time t _{3 to} t ₄ , φ _vrs
And φ _t are set to high level (ON),
The OS switches 10 _-1 to 10 _-n and 3 _{-1 to} 3 _-n become conductive,
The storage capacitors 5 _{-1 to} 5 _-n are grounded and the residual charges are reset. When the reset for each of the base and the emitter of the pixel columns 1 _-1 to 1 _-n is completed, the storage operation is started next.

When the accumulation operation is started, the photoelectrically converted charges are accumulated in the base regions of the pixel columns 1 _-1 to 1 _-n . At this time, the base and emitter of the pixel column are in a floating state (capacitive load state), and a voltage reflecting the base potential is generated at the emitter.

When reading signals sequentially, an NMOS is used.
The switches 4 _-1 to 4 _-n are sequentially turned on by the shift register 6.
The signal charge stored in the storage capacitors 5 _{-1 to} 5 _-n is read out to the read line 7. The shift register 6 turns on the NMOS switch 8 for φ _hrs immediately before sequentially selecting the NMOS switches 4 _-1 to 4- _n each time φ _ck is input, and resets the charges remaining on the read line 7.

Next, FIG. 7A shows a schematic plan view of an example of the photoelectric conversion cell shown in FIG. A sectional view taken along the line AA 'is shown in FIG. 7 (b), and a sectional view taken along the line BB' is shown in FIG. 7 (c). Note that FIG. 8 is an equivalent circuit diagram thereof.

In each figure, an n ⁺ buried layer 12 and an n ⁻ epitaxial layer 13 are formed on a p-type silicon substrate 11. An n ⁺ region (not shown) for taking out a collector and a p base region 21 are formed in the n ⁻ epitaxial layer 13. p base region 2
1, an n ⁺ emitter region 22 is formed. An emitter electrode 31 is connected to the n ⁺ emitter region 22.

Further, in this example, the isolation region I is formed by the insulating region 51 and the n ⁺ region 52 provided therebelow.
SO is formed, and adjacent photoelectric conversion cells are electrically isolated from each other.

The p base region 21 also serves as the drain of the MOSFET, and is separated from the other electrode (source) 33 by the gate electrode 32.

An n ⁺ region 34 is formed in each of the p base region 21 and the n ⁻ epitaxial region 13, and the n ⁻ epitaxial region 13 and the insulating film 35 formed on the n ⁻ epitaxial region 13 are formed. Contributes to the removal of the current component that is generated and recombined near the interface. (Conventional Example B) Next, an example of a three-value level drive type photoelectric conversion element will be described. A photoelectric conversion element of this type is disclosed in detail in Japanese Patent Application No. 62-17150 (Title of Invention: Photoelectric conversion device), and therefore will be briefly described here.

FIG. 12 is a schematic cross-sectional view of a photoelectric conversion element. A plurality of photoelectric conversion elements S ₁ are formed on an n-silicon substrate 101.
.. S _n are formed, a p region 103 is formed by doping a p-type impurity on the n ⁻ region 102 having a low impurity concentration formed by an epitaxial technique or the like, and an impurity diffusion is performed in the p region 103. The n ⁺ region 104 is formed by the technique or the ion implantation technique. P region 103 and n ⁺ region 104 are the base and emitter of the bipolar transistor, respectively.

N ⁻ region 1 in which each region is formed in this way
An oxide film 105 is formed on the oxide film 105, and a capacitor electrode 106 having a predetermined area is formed on the oxide film 105 so as to extend between the p base regions 103 and the adjacent p base regions 103. This p base region 10
The capacitor electrode 106 on 3 forms a capacitor C _ox facing the p base region 103 to control the base potential, and the electrodes 106 between adjacent bases source the adjacent p base region 103 respectively. It serves as a gate electrode of the MOS transistor Tr which serves as a drain region.
Therefore, the capacitor electrode and the MOS transistor Tr
The gate electrode is connected to.

The MOS transistor Tr is a p-channel type and normally-off type, and is in an off state if the potential of the electrode 106 is the ground potential or a positive potential. Therefore, the p base region 103 between adjacent elements is electrically isolated, and it is not necessary to form an element isolation region, which is advantageous for miniaturization of the element.

On the contrary, when the electrode 106 has a negative potential exceeding the threshold potential V _th , the MOS transistor Tr is turned on, and the p base regions 103 of the respective elements are brought into conduction with each other.

Besides, the emitter electrode 107 connected to the n ⁺ emitter region 104, the protective film 108, and the substrate 101.
An n ⁺ region 109 having a high impurity concentration and a collector electrode 110 for applying a potential to the collector of the bipolar transistor are formed on the back surface of the bipolar transistor.

FIG. 13 is an equivalent circuit diagram, and a portion surrounded by a broken line in the drawing corresponds to an equivalent circuit of one photoelectric conversion element.

In the figure, the photoelectric conversion elements S _{1 to} S _{n are shown.}
The electrodes 106 of the
A pulse φd is input to.

Further, the MOS transistors Tr of the respective elements S _{1 to} S _n are connected in series, and the p base regions 103 of the terminal elements S ₁ and S _n are further spaced apart from each other by p regions (not shown). No.) is formed, and a p-channel type normally-off type MOS transistor Q _X is formed on the element S _n side.

A pulse φd is input to the gate electrode of the MOS transistor Q _X , like the electrode 106, and the p region (not shown) is fixed at a constant potential V _c . The p region (not shown) of the MOS transistor Tr of the element S ₁ is also fixed to the constant potential V _c .

Therefore, by turning on all the MOS transistors Tr and Q _X , the potential of the p base region 103 of each element can be set to a constant potential V _c . In addition, in the off state, each element is in an electrically separated state.

The emitter electrode 107 of each element is grounded via a reset transistor Qb ₁ ~Qb _n, in common to the gate electrode of the transistor Qb ₁ ~Qb _n pulses φ
r inputs.

A positive voltage V _cc is applied to the collector electrode 110.
Is being applied.

FIG. 14 is a schematic circuit diagram of a conventional solid-state image pickup device using such a photoelectric conversion element.

This device is based on the photoelectric conversion element S shown in FIG.
The ₁ to S _n is m × n area sensor having a structure in which overlapping m lines. However, although each line has the structure shown in FIG. 12, a normal element isolation region is formed between the lines to electrically isolate the lines.

The electrodes 106 of the elements in each line are commonly connected to the horizontal lines HL _{1 to} HL _m , respectively, and connected to the terminal 120 via the switches SW _{1 to} SW _m , respectively. The pulse φd is input to the terminal 120.

The switches SW _{1 to} SW _m are analog switches composed of nMOS transistors, and the output terminals of the vertical scanning circuit 121 are connected to their gate terminals.
It is controlled by the output pulses φv _{1 to} φv _m .

The emitter electrode 107 of each element is connected to the vertical lines VL _{1 to} VL _n column by column. The vertical lines VL _{1 to} VL _n are reset transistors Qb _{1 to} Qb.
through _n are grounded, the pulse φr is input to the gate electrode of the transistor Qb ₁ ~Qb _n.

Further, the vertical line VL ₁ ~VL _n, is connected to each storage capacitor C ₁ -C _n via the transistor Qa ₁ ~Qa _n, further capacitors C ₁ -C _n transistor Q ₁ to Q _n Is connected to the output line 122 via.

The common type pulse φt to the gate electrode of the transistor Qa ₁ ~Qa _n, transistor Q ₁ to Q
_A pulse φh from the horizontal scanning circuit 123 is applied to the gate electrode of _{n.
1 to} φh _n are input respectively.

The output line 122 is grounded via the transistor Qrh and is connected to the input terminal of the amplifier 124. The pulse φrh is input to the gate electrode of the transistor Qrh.

The constant potential V _c for setting the base potential of each element is the ground potential.

Next, the operation will be described with reference to the timing chart of FIG.

First, the pulse φv ₁ of the vertical scanning circuit 121
Only the high level is turned on and the switch SW ₁ is turned on. Also, the ON state of the transistor Qa ₁ ~Qa _n by a pulse φt to the high level.

Next, when the pulse φd is set to a positive potential for the period T ₁ , the element S _{11 on} the first line is passed through the switch SW ₁ .
A positive voltage is applied to the electrodes 106 of S _1n . Thus the read operation of the first line is performed, the read signal is the vertical line VL ₁ of the first line ～VL _n and transistors Qa
They are respectively stored in the capacitor C ₁ -C _n through _{1 ~Qa n.}

Next, the pulse φt goes low and the transistors Qa _{1 to} Qa _n are turned off. The pulse φh ₁ ~φh _n are sequentially output from the horizontal scanning circuit 123, the read signal stored in the capacitor C ₁ -C _n is fetched sequentially to the output line 122 via the transistor Q ₁ to Q _n accordingly, The output signal V _out is serially output to the outside through the amplifier 124. In addition,
The pulse Qrh rises each time each read signal is output, and the transistor Qrh is turned on to remove the carrier on the output line 122.

In parallel with this signal output operation, the pulse φr is set to the high level to turn on the transistors Qb ₁ to Qb _n , and the vertical lines VL _{1 to} VL _n are grounded. Further, the pulse φd is set to a negative potential in the period T ₂ to turn on the MOS transistor Tr on the first line.

As a result, as described above, the element S
The potential of the p base region 103 of _{11 to} S _1n is the ground potential V _c.
Is uniformly set to 0, and the initial negative potential is restored by the refresh operation in the periods T ₃ and T ₄ , and the accumulation operation is started.

When the operation of the first line is completed in this way,
The pulse φv ₁ falls, and the switch SW ₁ is turned off. Then, the pulse φt rises and the transistor Qa
And turned on the _{1 ~Qa n.} As a result, the carriers remaining in the capacitors C _{1 to} C _n are transferred to the vertical line VL.
_{1 through} VL _n and transistors Qb ₁ through Qb _n .

Thereafter, the same operation is performed for each line and the second
~ The read signals of the m-th line are sequentially output.

As described above, by using the photoelectric conversion element driven by the pulse φd of three levels, the base potential of the element of each line is set to a constant potential in the period T ₂ .
After that, since the refresh operation is performed in the periods T ₃ and T ₄ , a solid-state imaging device having favorable afterimage characteristics and good linearity of photoelectric conversion characteristics can be obtained. Moreover, since the element isolation region is not required in the line direction, it is possible to obtain the solid-state imaging device which is suitable for the miniaturization of the element and can easily cope with the high resolution.

[0047]

(Problem A) However, in FIG. 7C, the insulating region 51 of the element isolation region is formed.
There is a possibility that the n ⁺ region 52 as a high-concentration impurity region provided directly under the region will be displaced from the insulating region 51 during patterning. FIG. 7C is a diagram showing a state where the n ⁺ region 52 is displaced and a gap is formed between the n ⁺ region 52 and the n ⁺ region 34 as a high-concentration impurity region under the light receiving portion.

This is because in the conventional method for manufacturing such a photoelectric conversion device, the n ⁺ region 52 is particularly under the element isolation region.
As a method of forming the n ⁺ region 34 under the light receiving part, patterning of the Si ₃ N ₄ film for forming the element isolation region 51 and patterning for forming the n ⁺ region 52 immediately below the element isolation region are performed respectively. Using the resist as a mask,
This is because methods such as patterning are performed independently of each other.

When such a displacement occurs, the n ⁻ epitaxial region 13 contacts the insulating film 51, and the current component generated and recombined near the interface cannot be ignored.

In particular, since the current component generated and recombined from the vicinity of the interface near the element isolation region causes the dark current, in the above conventional photoelectric conversion cell, the noise component due to the dark current of the photoelectric conversion cell is included in the signal. It had a problem that

(Object A) An object of the present invention is to provide a photoelectric conversion device which prevents the generation of dark current in a photoelectric conversion cell and eliminates noise due to the dark current, and a method for manufacturing the same.
In particular the source of the dark current, n ^- so that the insulating layer of the epitaxial layer and the element isolation region does not contact the photoelectric conversion device formed without gaps n ⁺ layer in succession in the meantime, and implementing the manufacturing method To do. (Problem B) In the conventional example of FIG. 14, in order to pass the driving pulse φd of three-valued level to the horizontal lines HL _{1 to} HL _m , the pulse φd is applied to the gate electrodes of the nMOS transistors forming the switches SW _{1 to} SW _m. It is necessary to supply scan pulses φv _{1 to} φv _m with an amplitude (L level to H level + threshold voltage of nMOS transistor) sufficient to pass.

The H level of the input clock of the scanning circuit is φ
It is necessary to set _{Vth of} the nMOS transistor higher than the H level of d, which causes a problem that the load of the clock generation circuit becomes large.

Therefore, the vertical scanning circuit driven by the input clock from the normal clock generating circuit may not be able to output the scanning pulse having a sufficient amplitude, and the reliability of the vertical scanning circuit is deteriorated. The problem arises.

(Object B) The object of the present invention is preferable in a photoelectric conversion element in which a plurality of photoelectric conversion elements are arranged and the photoelectric conversion elements are driven through a switch means, by reducing the load of the clock generation circuit. The reliability of the photoelectric conversion device is improved by outputting the scanning pulse having the amplitude.

[0055]

(Means A) The present invention constitutes the photoelectric conversion cell in a photoelectric conversion device having a plurality of bipolar photoelectric conversion cells as means for solving the above-mentioned problems. A high-concentration impurity region having a higher concentration and the same conductivity type than that of the collector region of the bipolar transistor is provided in a region under the insulating film in the element isolation region between the photoelectric conversion cells and a region under the insulating film in the light receiving portion. However, the photoelectric conversion device is characterized in that the high-concentration impurity region below the element isolation region and the high-concentration impurity region below the light receiving portion are continuously arranged without a gap.

Further, in the method for manufacturing a photoelectric conversion device having a plurality of bipolar photoelectric conversion cells, the resist in a portion which becomes an element isolation region between the photoelectric conversion cells is removed,
In order to form a high-concentration impurity region below the element isolation region, a step of implanting impurity ions, a step of forming a thick oxide film to be an insulating film of the element isolation region after the ion implantation, and the thick oxide film After the step of forming a step of removing the resist, a step of forming a thin oxide film which becomes an insulating film of a light receiving portion on the removed surface, and a step of forming a thin oxide film under the light receiving portion of the photoelectric conversion cell and under the element isolation region. To form a high-concentration impurity region that is continuous with a high-concentration impurity region, a step of implanting impurity ions through the thin oxide film, Is the means of. (Means B) As a means for solving the above-mentioned problems, the present invention provides a photoelectric conversion device in which a plurality of photoelectric conversion elements are arranged and the photoelectric conversion elements are driven through a switch means, and outputs from a vertical scanning circuit. There is provided a photoelectric conversion device comprising a booster circuit having a bootstrap effect, which is provided with a bootstrap capacitance means on the output side of the switch means for boosting the scanning pulse to be generated.

[0057]

(Function A) The above-mentioned conventional problem is that the n ⁺ region 52 and n ^{− which} are provided immediately below the insulating region 51 in the element isolation region.
A gap is formed between the epitaxial region 13 and the n ⁺ region 34 below the light receiving portion formed in a part of the p base region 21, and the n ⁻ epitaxial region 13 becomes the insulating region 3.
By contact with 5, 51, a dark current component is generated,
This was due to the increased recombination current.

Therefore, in the photoelectric conversion device according to the present invention, in the element isolation region of the photoelectric conversion device, the low impurity concentration region (n ^- epitaxial layer 13) is isolated from the insulating regions 51 and 3.
N ⁺ region 52 as a high-concentration impurity region provided under the element isolation region so as to be disposed without contacting with 5,
It is characterized in that n ⁺ regions 34 as high-concentration impurity regions under the light receiving portion are continuously arranged without a gap.

As described above, since the element isolation region and the portion of the bipolar transistor collector region in contact with the insulating region are continuously formed by the n ⁺ region having a high impurity concentration, the generation and recombination current is small. That is, it is possible to obtain a photoelectric conversion device with a small dark current.

(Operation B) Further, according to the present invention, by providing the booster circuit using the bootstrap effect between the vertical scanning circuit and each photoelectric conversion device, the scanning pulse output from the vertical scanning circuit is generated. The voltage can be boosted and the drive pulse φd is applied to each photoelectric conversion element without a voltage drop, so that the reliability of the vertical scanning circuit can be improved.

[0061]

(Embodiment A1) An embodiment of the present invention will be described in detail below with reference to the drawings.

First, the structure of the photoelectric conversion cell used in this embodiment will be described.

FIG. 1A is a schematic plan view of a photoelectric conversion cell used in one embodiment of the photoelectric conversion device according to the present invention.
1B is a sectional view taken along the line AA ′, FIG. 1C is a sectional view taken along the line BB ′, and FIG. 8 is an equivalent circuit diagram thereof. However, the same numbers are assigned to the regions having the same functions as those of the conventional example described with reference to FIGS.

In each figure, an n ⁺ buried layer 12 is formed on a p-type silicon substrate 11, and an n ⁻ epitaxial layer 13 is further formed.

In the n ⁻ epitaxial layer 13, an n ⁺ region (not shown) for taking out a collector and a p base region 2 are formed.
1 is formed. An n ⁺ emitter region 22 is formed in the p base region 21. An emitter electrode 31 is connected to the n ⁺ emitter region 22.

The p base region 21 also functions as the drain of the MOSFET, and is separated from the other electrode (source) 33 by the gate electrode 32.

[0067] Also, the p base region 21, n ^- each portion of the epitaxial region 13, n ⁺ region 34 as a high concentration impurity region of the light receiving portion of the photoelectric conversion cells are formed, n ^- epitaxial region 13 Contributes to the removal of current components that are generated and recombined in the vicinity of the interface between the insulating film 35 and the insulating film 35 formed thereabove.

Further, in this example, the element isolation region I is formed by the insulating region 51 and the n ⁺ region 52 provided therebelow.
SO is formed, and adjacent photoelectric conversion cells are electrically isolated from each other. At this time, the insulating region 5 of the element isolation region
1. An n ⁺ region 52, which is a high-concentration impurity region provided immediately below 1, and an n ⁺ region 34, which is a high-concentration impurity region provided immediately below the insulating region 35 of the light receiving portion, are connected to each other and arranged without a gap. Has been done.

Further, an insulating layer (not shown) is formed on the upper part of the AL wiring used for the electrode, and the light shielding AL (not shown) covers the upper part of the insulating film. At this time, light-shielding AL
The film covers the emitter electrode portion 31 of the bipolar transistor.

Further, plasma S is used as a passivation film.
An iN film (not shown) is formed.

Next, a manufacturing method according to the embodiment of the present invention will be described with reference to FIGS. 2 to 4, (a) is a cross-sectional view corresponding to FIG. 1 (b),
FIG. 1B is a sectional view corresponding to FIG.

First, the p-type has a specific resistance of 10 to 20 Ω · c.
An n-type region 12 and a p-type region (not shown) were formed on the m silicon substrate 11.

Next, the n ^- epitaxial layer 13 was formed in the atmosphere of H ₂ + SiHCl ₃ + PH ₃ .

Next, the silicon substrate is oxidized to a film thickness of 35n.
An oxide film 14 having a thickness of m was formed, and then a Si ₃ N ₄ film 15 was deposited by an LPCVD apparatus. At this time, the thickness of the Si ₃ N ₄ film 15 was 150 nm.

Next, Si ₃ N _{4 in a} portion to be an element isolation region
The film 15 was removed by photolithography and dry etching, and then the resist in the element isolation region and the entire light receiving portion was removed by resist patterning.

Next, using an ion implantation apparatus, phosphorus of 2 ×
I hit 10 ¹³ cm ^-2 . The acceleration voltage at this time is 45 ke
It was V (FIGS. 2 (a) and 2 (b)).

Under this condition, phosphorus ions are injected into the silicon substrate at the portion where the Si ₃ N ₄ film 15 is removed, but not at the portion where the Si ₃ N ₄ film 15 is present.

Next, after removing the resist, the substrate was oxidized. The oxide film thickness at this time was 800 nm.

The partially remaining Si ₃ N ₄ film 15 was removed with phosphoric acid, and after hydrofluoric acid treatment, an oxide film 35 having a thickness of 30 nm was formed (FIGS. 3A and 3B). ).

Subsequently, polysilicon to be the gate electrode of the MOSFET is deposited and selectively removed, followed by NPN.
Bipolar transistor emitter 22 and NMO
SFET source, drain (not shown), and PM
The source 33 and the drain of the OSFET were formed respectively.

Then, by resist patterning,
Element isolation region and p base region 21 and n ^{− of the} light receiving portion
The resist 80 on the entire epitaxial region 13 was removed.

Next, arsenic ions were implanted at 5 × 10 ¹² cm ^-2 by an ion implantation device. The acceleration voltage at this time was 150 keV (FIGS. 4 (a) and 4 (b)).

Under this condition, arsenic ions are not implanted into the silicon substrate below the insulating region formed of a thick oxide film. By adopting the above manufacturing method, FIG.
As shown in (b) and (c), the n ⁺ region 52 provided directly under the insulating region ISO and the n ⁺ region 34 provided in the light receiving portion PD can be continuously arranged, and low impurity There is no region where the high concentration n ⁻ epitaxial region 13 is in contact with the insulating films 51 and 35.

Then, a SiO film is deposited by CVD,
After opening the contact holes, an AL film for wiring was formed, and further, an insulating film, a light-shielding AL film, and a passivation film were formed to manufacture the photoelectric conversion device of the present invention. (Embodiment B1) FIG. 9 is a schematic circuit diagram showing an embodiment of the solid-state imaging device according to the present invention.

The point different from the conventional example shown in FIG. 14 is that a circuit for boosting the output of the vertical scanning circuit 121 is added, and the boot strap capacitance C _B1 is added to each horizontal line HL _{1 to} HL _m. ~ C _Bm is added, switch
Transistor Qt ₁ ~Qt transistor Qu ₁ ~Qu _m for resetting the gate electrode of the _m, and Qt ₁ ~Qt
_The circuit has transistors Qs _{1 to} Qs _m for floating the gate electrode of _m and an inverter 131.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. In this example,
The high level of the pulse φd is output to the horizontal lines HL _{1 to} HL _m without voltage drop, and all input clocks are the same as those in the timing chart of FIG. It is the same as FIG. 14 of the example.

First, the pulse φv ₁ of the vertical scanning circuit 121
Becomes high level, the transistor Qs ₁ is turned on, and the gate potential v ₁ of the transistor Qt ₁ becomes (high level of pulse φv ₁ −threshold voltage of nMOS transistor). Further, the pulse φt is set to the high level to turn on the transistors Qa ₁ to Qa ₂ .

Next, when the pulse φd becomes high level,
Although positive voltage to the horizontal line HL ₁ through the transistor Qt ₁ is applied, through a boot strap capacitor C _B1, the gate voltage v ₁ of the transistor Qt ₁ is raised in the positive direction. However, at this time, the voltage increase of v ₁ is not absorbed by φv ₁ by the transistor Qs ₁ .

As a result of an experiment in this embodiment, the channel width / channel length of the transistors Qs ₁ and Qt ₁ is: W
/ L is 6/2, 50/2, C _B1 is 0.4 pF,
If all high level of input pulse is 5V, V ₁
The voltage of about 3.7 is immediately after φv ₁ becomes high level.
Immediately after the voltage became V and φd became high level, it was confirmed that the voltage increased to about 9V, and therefore the horizontal line HL ₁ increased to 5V without a voltage drop.

As a result, the read operation of the first line is performed, and the signals of the first line are changed to the vertical lines VL _{1 to} VL _n.
And through the transistor Qa ₁ ~Qa _n, are respectively stored in the capacitor C ₁ -C _n.

Next, the pulse φt goes low, turning off the transistors Qa ₁ -Qa _n . The pulse φh ₁ ~φh _n are sequentially output from the horizontal scanning circuit 121, the read signal stored in the capacitor C ₁ -C _n is fetched sequentially to the output line 122 via the transistor Q ₁ to Q _n accordingly, The output signal V _out is serially output to the outside through the amplifier 124.

Note that the pulse φrh rises every time each read signal is output, the transistor Qrh is turned on, and the carrier on the output line 122 is removed.

In parallel with this signal output operation, the pulse φr is set to the high level to turn on the transistors Qb ₁ to Qb _n , and the vertical lines VL _{1 to} VL _n are grounded. Further, the pulse φd is set to a negative potential in the period T ₂ , and the MOS transistor Tr on the first line is turned on.

As a result, as described above, the element S
The potential of the p base region 103 of _{11 to} S _1n is the ground potential V _c.
Is uniformly set to 0, and the initial negative potential is restored by the refresh operation in the periods T ₃ and T ₄ , and the accumulation operation is started. Even in the period T ₄ , V ₁ rises to a sufficiently high voltage (for example, 9V), and the same effect as described above can be obtained.

When the operation of the first line is completed in this way,
When the pulse φv ₁ falls, the transistor Qu ₁ is turned on by the inverter, V ₁ becomes the ground potential, and the switch Qt ₁ is turned off. Subsequently, the ON state pulse φt is a rising transistor Qa ₁ ~Qa _n. As a result, carriers remaining in the capacitors C _{1 to} C _n are transferred to the vertical lines VL _{1 to} VL _n and the transistor Qb.
Remove through _1- Qb _n .

Thereafter, the same operation is performed for each line, and the second
~ The read signals of the m-th line are sequentially output. (Embodiment B2) FIG. 11 is a schematic circuit diagram showing another embodiment according to the present invention. For Example B1 (FIG. 9),
Reset transistors Qv _{1 to} Qv _m are added to each horizontal line HL _{1 to} HL _m . Further, the gate of the transistor Qv ₁ ~Qv _m, pulse .phi.v ₁ ~
φv _m is connected via an inverter, and in each of the horizontal lines HL _{1 to} HL _m , when not selected, that is, φv m
Horizontal lines HL _{1 to} H when _{1 to} φv _m is low level
L _{m is set} to the ground potential.

As a result, in the horizontal direction, HL _{1 to} HL _m
It is possible to suppress the influence of crosstalk via the.

The operation of this embodiment is the same as that of the embodiment B except for the above.
Since it is exactly the same as 1, it is omitted. (Embodiment B3) FIG. 16 is a schematic circuit diagram showing another embodiment of the present invention. In Examples B1 and B2, each horizontal line HL _{1 to} HL _m was driven by a pulse having a three-valued level, but in this embodiment, HL _{1 to} HL _m are driven by a pulse having a two-valued level. Is.

[0099] This example booster circuit portion of the horizontal line HL ₁ ~HL _m is the same manner as in Example B1, newly, reset transistor Qc ₁ ~Qc _n vertical line VL ₁ ~VL _m Has been added. Further, the element S ₁₁
The base reset potential v _{c of} ~ S _mn can also be input from an external terminal.

The operation of this embodiment will be described with reference to FIG.

First, at time t _o , the pulse φv ₁ rises. At this time, φr is at the high level and the vertical line V
All of L _{1 to} VL _n are reset to the ground potential.

Next, φt rises, and the capacitors C _{1 to} C
_{n is} also reset to the ground level, and at time t ₂ , φ
r falls, and each vertical line is in a floating state.

After that, when the pulse φd goes high for the period T _{1, the} high level of the pulse φd drops to the electrodes 106 of the elements S _{11 to} S _1n on the first line, as in the first embodiment. Applied without. As a result, the signal of the first line is read, and the signals of the elements S _{11 to} S _1n are read onto the capacitors C _{1 to} C _n .

[0104] Then, pulse φt becomes a low level, the transistor Qa ₁ ~Qa _n is turned off, the time t ₂
Then, φv ₁ also becomes low level and the transistor Qt ₁ is also turned off.

Then, the pulse φ is output from the horizontal scanning circuit 123.
h₁~ Φh_nAre output in sequence and the capacitors are
C₁~ C_nThe read signal stored in the transistor Q₁
~ Q _nAre sequentially taken out to the output line 122 via
Output signal V through the pump 124_outTo the outside as Syria
Will be output. It should be noted that each time each read signal is output
The pulse φrh rises, turning on the transistor Qrh.
The carrier on the output line 122 is removed.

In parallel with this signal output operation, the pulse φr is set to the high level to turn on the transistors Qb ₁ to Qb _n , and the vertical lines VL _{1 to} VL _n are grounded.

In this way, after all the read signals on the capacitors C _{1 to} C _n are output to the outside, the signal reading of the elements on the m-th line from the second line onward is performed in exactly the same manner.

At the time t after the signal reading of all the elements is completed.
_{At 3} , V _c rises above the threshold voltage of the p-MOS transistor in each device. Each horizontal line H
Since L _{1 to} HL _m are at the ground potential, the p-MOS transistor in the element is turned on by this, and all the pixels are reset from the ground voltage to the positive potential by the threshold voltage of the p-MOS transistor. Will be done (collective complete reset).

After that, V _c falls to the ground potential again, and the reset is completed. Next, at time t ₄ , when the pulse φr ₂ rises, all pixels are simultaneously refreshed.

At this time, by setting the terminal voltage V _r to an appropriate value, it is possible to set the base potentials of all pixels at the end of refreshing to near the ground potential (collective refresh operation).

After that, the pulse φr ₂ falls, and the above-mentioned refresh operation is completed.

Next, at time t ₅ , pulse φv ₁ rises, and thereafter pulse φd also rises, refreshing the elements on horizontal line HL _{1 and} performing base region 103 of elements S ₁₁ -S _1n. Potential returns to the initial negative potential, and the accumulation operation starts. The refresh operation is performed for every horizontal line, and all the elements are in the storage state (sequential refresh operation).

Through the series of read-out operations, batch complete reset operation, batch refresh operation, and sequential refresh operation, a solid-state image pickup device having good afterimage characteristics and good linearity of photoelectric conversion characteristics can be obtained.

[0114]

As described above, according to the present invention, in the photoelectric conversion device having the bipolar type photoelectric conversion cell, the element isolation region between the photoelectric conversion cells and the light receiving region are in the vicinity of the interface contacting the insulating film. By disposing a region having a high impurity concentration in the photoelectric conversion device, a dark current is small, that is, a S / N is large.

(Effect B) Further, according to the present invention, the scanning pulse output from the vertical scanning circuit for driving a plurality of photoelectric conversion elements is boosted by the boosting circuit having the bootstrap effect and supplied. The drive clock of the photoelectric conversion element can be applied to each photoelectric conversion element without a voltage drop.

As a result, a photoelectric conversion device having good afterimage characteristics and good linearity of photoelectric conversion characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing the structure of a photoelectric conversion device of Example A1 of the present invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of a photoelectric conversion device of the present invention.

FIG. 3 is a schematic cross-sectional view showing a manufacturing process of the photoelectric conversion device of the present invention.

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of the photoelectric conversion device of the present invention.

FIG. 5 is a circuit diagram of a photoelectric conversion device according to a conventional example and the present invention.

FIG. 6 is an operation timing chart of a photoelectric conversion device according to a conventional example and the present invention.

FIG. 7 is a schematic diagram showing a structure of a conventional photoelectric conversion device.

FIG. 8 is an equivalent circuit diagram of a conventional example and a photoelectric conversion device of the present invention.

FIG. 9 is a circuit diagram of a photoelectric conversion device of Example B1 of the invention.

FIG. 10 is a timing chart of the embodiment B1 of the present invention.

FIG. 11 is a circuit diagram of a photoelectric conversion device of Example B2 of the invention.

FIG. 12 is a schematic view showing a cross section of a conventional photoelectric conversion device.

13 is an equivalent circuit diagram of the photoelectric conversion device of FIG.

FIG. 14 is a circuit diagram showing an overall view of a conventional photoelectric conversion device.

FIG. 15 is a timing chart showing a driving method of a conventional example.

FIG. 16 is a circuit diagram of a photoelectric conversion device of Example B3 of the invention.

FIG. 17 is a timing chart of Example B3.

[Explanation of symbols]

1 _-1 to 1 _-n phototransistor array 2 _-1 to 2 _-n PMOSFET switch 3 _{-1 to} 3 _-n , 4 _-1 to 4 _-n , 10 _-1 to 10 _-n NMOS
FET switch 6 shift register 11 p-type silicon substrate 13 n-type epitaxial layer 21 p base region 22 n-type emitter region 34 n-type high impurity concentration region 35 insulating film 51 insulating film 52 n-type high impurity concentration region 80 photoresist 121 vertical scanning Circuit 122 Output line 123 Horizontal scanning circuit 124 Amplifier 131 Inverter C _{B1 to} C _Bm Bootstrap capacitance VL _{1 to} VL _n Vertical line HL _{1 to} HL _m Horizontal line

Claims (6)

[Claims] 1. A photoelectric conversion device comprising a plurality of bipolar photoelectric conversion cells, wherein a high-concentration impurity region of the same conductivity type and having a higher concentration than a collector region of a bipolar transistor forming the photoelectric conversion cell is formed, A region under the insulating film in the element isolation region between photoelectric conversion cells, and a region under the insulating film in the light receiving portion, a high concentration impurity region under the element isolation region, and a high concentration impurity region under the light receiving portion A photoelectric conversion device, wherein the photoelectric conversion devices are continuously arranged without gaps. 2. A method of manufacturing a photoelectric conversion device having a plurality of bipolar photoelectric conversion cells, wherein a resist in a portion which becomes an element isolation region between the photoelectric conversion cells is removed, and a high concentration impurity is formed under the element isolation region. A step of implanting impurity ions to form a region, a step of forming a thick insulating film in the element isolation region after the ion implantation, and a step of forming the thick insulating film, and then removing the resist, Forming a thin insulating film of a light receiving portion on the removed surface; and forming a high concentration impurity region continuous with the high concentration impurity region under the element isolation region under the light receiving portion of the photoelectric conversion cell, And a step of implanting impurity ions through the insulating film. 3. A photoelectric conversion device in which a plurality of photoelectric conversion elements are arranged and which drives the photoelectric conversion elements via a switch means, wherein the switch means for boosting a scan pulse output from the vertical scanning circuit. A photoelectric conversion device having a circuit having a bootstrap effect in which a bootstrap capacitor means is provided on the output side of the photoelectric conversion device. 4. The photoelectric conversion device according to claim 3, further comprising a switch means for grounding the horizontal line when the horizontal line is not selected and having a function of resetting all pixels at once. 5. The photoelectric conversion device according to claim 3, further comprising reset switch means for each vertical line. 6. The photoelectric conversion device according to claim 5, further comprising a variable power supply V _C for resetting the bases of the transistors forming the plurality of photoelectric conversion elements.