JPH0697687B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In the present invention, when a three-dimensional semiconductor integrated circuit device is manufactured by a master slice method, a conductor pattern having general versatility is provided in the same layer as a lower semiconductor element, and this is customized. By trimming according to the wiring design and connecting to the wiring formed on the upper semiconductor element, the degree of integration is increased and wiring failure is suppressed.

[Industrial application field]

A method of manufacturing a custom LSI in order to cope with system diversification under conditions such as shortening of development period and improvement of economic efficiency, and to realize a more advanced large-scale semiconductor integrated circuit device (hereinafter abbreviated as LSI). As the master slice (master slic
e) The method is widely used. The master slice method is a method in which a semiconductor wafer on which necessary elements are formed is prepared in advance, and wiring is connected to the semiconductor wafer according to customer requirements to complete an LSI, which has a great effect on the realization of a custom LSI.

On the other hand, for the purpose of higher integration and higher speed of LSI,
A three-dimensional structure for three-dimensionally integrating semiconductor devices has been developed. For the three-dimensional structure, a master slice method is required as a method for manufacturing a custom LSI, but there is a big problem in wiring connection to a semiconductor element or the like in the lower layer stacked.

[Conventional technology]

In the master slice method, usually, the central portion of each chip area is an area in which unit cells (basic circuit composed of a plurality of transistors, resistors, etc.) necessary for forming a functional block such as a logic circuit are arranged in an array, and its periphery. Is used as a peripheral circuit region such as an input / output cell, for example, for a field effect transistor (FET) element, a standardized semiconductor wafer formed up to a gate electrode and a source / drain region is used.

The wiring pattern that connects the elements in the unit cell is designed according to the function of each block, and the wiring pattern of the entire chip that connects the functional blocks and peripheral circuits is designed according to the function required as an LSI. .

In the conventional master slice method, the number of wiring layers is normally set to two in this wiring pattern, and the main wiring direction is determined for each wiring layer, and the lower first layer wiring is arranged on the wiring area between the internal wiring of the functional block and the array. Set the wiring parallel to the second upper
The layer wiring is orthogonal to the first layer wiring, and the second layer wiring is mainly connected to the first layer wiring.

In order to suppress the number of wiring layers or increase the degree of freedom of wiring, an impurity diffusion region or a gate electrode layer using the same layer as the semiconductor element is used to form a conductive pattern such as an array in a wiring region between cell arrays. There is also an attempt to form it in advance, select it, and use it as the first wiring layer.

On the other hand, as described above, a three-dimensional structure in which semiconductor elements are three-dimensionally integrated has been developed for the purpose of further increasing the integration and speeding up of the LSI. In a three-dimensional LSI, at least the semiconductor elements on the second layer and above are SOI (Silicon (Semiconductor) on Insula)
tor) structure.

For the SOI structure, for example, polycrystalline silicon (Si) or the like is deposited on an insulating film such as silicon dioxide (SiO ₂ ) and made into a single crystal by a method such as laser light scanning, and a transistor element or the like is formed there to perform wiring connection. It is a thing. This SOI structure is characterized in that the capacitance between the SOI substrate and the substrate is reduced compared to the normal structure in which transistor elements are formed on the semiconductor substrate, and latch-up does not occur even if the element spacing is shortened. Suitable for high integration and high integration. Because of this feature, SOI structures were first developed in a single layer and often applied to the first layer in a three-dimensional structure.

[Problems to be solved by the invention]

When the master slice method is applied to such a three-dimensional LSI, it is necessary to provide various wiring connections on a wafer formed by stacking semiconductor elements in advance.

The lower layer can be connected to the semiconductor element by making the upper part a wiring area without the semiconductor element, but this makes the three-dimensional structure meaningless, and the upper and lower semiconductor element forming areas are overlapped, and the lower layer is used as the wiring. Should be fully utilized to increase the degree of integration.

Note that if the number of wiring layers increases, a failure due to step coverage failure or the like becomes more prominent. Therefore, it is particularly desirable in a three-dimensional LSI to suppress the number of wiring layers.

[Means for solving problems]

As shown in FIG. 1, which is a schematic plan view of the steps of the embodiment of the present invention, the problem is that the conductor pattern 4 is disposed in the vicinity of the semiconductor element 3 of the first layer, and the semiconductor of the first layer is formed. First on the element 3 and the conductor pattern 4
Is formed on the first insulating film 5, and the semiconductor pattern 6 of the second layer is formed on the first insulating film 5, and the conductor pattern 4 exposed by forming an opening 7 in the first insulating film 5 is cut. Then, a second insulating film is formed on the semiconductor element 6 of the second layer and the opening 7, and the wiring 8 connected to the conductor pattern 4 is formed on the second insulating film. This is solved by a method of manufacturing an integrated circuit device.

[Action]

In the manufacturing method according to the present invention, a conductor pattern having general versatility is previously provided in the same layer as the lower semiconductor element, trimmed according to a custom wiring design, and the conductor pattern and the wiring layer formed on the upper semiconductor element. And constitute wiring.

With this wiring configuration, it is possible to increase the integration degree of the three-dimensional LSI and suppress wiring failures.

〔Example〕

 The present invention will be specifically described below with reference to examples.

See FIG. 1 (a). According to the conventional technique, an SiO ₂ insulating film 2 having a thickness of, for example, about 1 μm is formed on a Si semiconductor substrate 1, and a Si polycrystalline layer has a thickness of, for example, about 0.5 μm on the SiO ₂ film 2. To form a single crystal by scanning with laser light, for example.

For example, the semiconductor element 3 of SOI structure such as MOS FET is
Although it can be formed by a conventional technique using a single crystal layer, in this embodiment, the standardized and versatile conductor pattern 4 is formed in parallel with the semiconductor element 3.

That is, in this embodiment, a large number of conductor patterns 4 are formed in parallel with each other between the arrays of the semiconductor elements 3 by using the gate electrode layers of the FETs, and some of the conductor patterns 4 are adjacent to the gate electrodes of the FETs. Are connected to each other.

The conductor pattern according to the present invention can also be formed by patterning the Si single crystal layer and introducing a high concentration of impurities into the semiconductor element 3 which is the semiconductor element of the first layer and the conductor pattern 4 at the same time. Alternatively, the patterning can be performed by forming a field oxide film instead of etching.

See FIG. 1B. A SiO ₂ film 5 as the first insulating film is deposited on the wafer, and a semiconductor element 6 of a second layer is formed thereon. The semiconductor elements 6 of the second layer are arranged in an array so as to overlap the semiconductor elements 3 of the first layer.

The wafer in which the semiconductor elements 3 and 6 are formed in the upper and lower two layers is the master slice of this embodiment.

Custom wiring is arranged on this wafer according to the customer's request. First, in the wiring design, the buried conductor pattern 4 is divided into a plurality of wiring portions, and this is sufficiently utilized to make full use of this, so that the semiconductor element of the second layer is formed. A wiring layer made of aluminum (A1) or the like and a conductor pattern 4 provided on the wiring 6 via the second insulating film (not shown) are used to form wiring that meets the requirements.

When the conductor pattern 4 is cut into a plurality of wiring portions or for the purpose of reducing capacitance, the conductor pattern 4 is cut in the SiO ₂ film 5 in the figure. It can be easily implemented by providing the opening 7 and etching the conductor pattern 4.

The wiring 8 (only a part of which is shown in the figure) of the A1 wiring layer is usually formed parallel to each other and orthogonal to the conductor pattern 4. The connection point 9 shown in (1) connects to the conductor pattern 4, the second-layer semiconductor element 6 and the first-layer semiconductor element 3.

This connection can be performed by a conventional technique, but in the present embodiment, the connection to the semiconductor element 3 of the first layer is performed, for example, simultaneously with the etching for cutting the conductor pattern 4 and the semiconductor of the second layer on the connection position. The element 6 is provided with an opening in advance.

As described above, the formation and trimming of the conductor pattern 4 can be easily carried out without increasing the number of steps in the conventional manufacturing method, and the wiring layer by A1 etc. is often stopped at one layer. This is possible, and the effect of increasing the degree of integration of the three-dimensional LSI by the master slice method and reducing obstacles can be obtained.

In order to further increase the scale, the wiring layer with A1 etc.
Layering is also possible without problems.

〔The invention's effect〕

As described above, according to the present invention, when a three-dimensional LSI is manufactured by the master slice method, it is possible to obtain an effect of increasing the degree of integration without increasing the number of steps and reducing obstacles due to the multilayer wiring. .

[Brief description of drawings]

1 (a) and 1 (b) are schematic plan views showing an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, 3 is a first layer semiconductor element, 4 is a conductor pattern, 5 is an insulating film, 6 is a second layer semiconductor element, 7 is an opening for cutting the conductor pattern, Reference numeral 8 indicates wiring by A1 or the like, and 9 indicates a connection point of the wiring.

Claims (1)

[Claims] 1. A conductor pattern (4) is provided in the vicinity of a semiconductor element (3) of a first layer, and the semiconductor element (3) of the first layer and the conductor pattern (4).
A first insulating film (5) is formed on the first insulating film (5), a second-layer semiconductor element (6) is formed on the first insulating film (5), and an opening () is formed in the first insulating film (5). 7) is provided and the exposed conductor pattern (4) is cut, and a second conductor pattern (4) is formed on the semiconductor element (6) of the second layer and the opening (7).
2. The method for manufacturing a semiconductor integrated circuit device, comprising: forming an insulating film of 1. and forming a wiring (8) connected to the conductor pattern (4) on the second insulating film.