JPH0697832A - Code conversion circuit and A / D converter including the same - Google Patents

Abstract

(57) [Summary] [Object] The present invention uses a binary code for an A / D converter that has a short conversion time to a binary code and generates little noise due to a code change. The object is to realize a precision A / D converter. In a code conversion circuit that converts a binary code input 19 into a binary code 15 and outputs the binary code 15, at least two or more bits including the least significant bit of the binary code 15 excluding the most significant bit are converted into the binary code 19. The exclusive OR of the jth bit and the (j + 1) th bit of the binary code 15 is a Gray code type exclusive OR circuit 16b.
Is output as the binary code of the j-th bit, and the remaining bits are the exclusive OR of the k-th bit of the binary code 19 and the (k + 1) -th bit of the binary code 19 in the pseudo code Gray code type exclusive logic. It is a code conversion circuit in which a binary code is set so as to be output as the k-th bit binary code 15 using the sum circuit 16a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter.

[0002]

2. Description of the Related Art In many industrial fields, digitization of signal processing has advanced, and an A / D having a function of converting an analog value into a digital value, which is a key device for digital signal processing.
The converter is also required to have high speed and high accuracy. In particular, a parallel A / D converter is mentioned as a basic configuration method of an image A / D converter mounted on a VTR or the like for converting an analog video signal into a digital value. Therefore, the configuration and operation of the parallel A / D converter will be shown.

FIG. 2 shows the configuration of a 3-bit parallel A / D converter. Between the reference voltage 1 and the reference voltage 2, the reference resistor string 3
Are connected. The reference resistor string 3 divides the potential difference between the reference voltages 1 and 2 into equal potentials by the reference resistor 4.
The corresponding potential point is connected to one input terminal of each voltage comparator 6 included in the voltage comparator array 5. That is, each voltage value VRi (i = 1, 2, 3, ..., 7) is VRi-1.
-VRi becomes a constant value. The other input terminal of each voltage comparator 6 included in the voltage comparator array 5 is connected to the analog input signal 7. The output terminal of the voltage comparator array 5 is connected to the input terminal of the code selection circuit 8, and the output terminal of the code selection circuit 8 is connected to the input terminal of the coding circuit 9. The output circuit of the encoding circuit 9 is connected to the input terminal of the code conversion circuit 10, and the 3-bit A / D conversion output 11 is output from the code conversion circuit 10.

The above is the configuration of the parallel A / D converter. Next, the operation of the A / D converter for converting an analog value into a digital value will be described with reference to FIGS. 4 (a) and 4 (b).
In FIG. 4A, the horizontal axis represents time and the vertical axis represents the voltage value of the analog signal. The A / D converter has sampling time TSi (i
= -1, 0, 1, ..., 7) The voltage value ANi of the analog signal is sampled. Sampling time TSi
Satisfies the condition that TSi + 1−TSi is constant. That is, the A / D converter samples the signal whose voltage value changes with the passage of time at equal time intervals.
The sampled analog input signal voltage ANi is compared with the comparison reference voltage VRi by each voltage comparator 6.
For example, when the reference voltages 1 and 2 are selected so that VR0 <VR8 in FIG. 2, when the analog signal 7 satisfying the condition of VR4 <ANi <VR5 is input, VR1, VR2, VR3, VR4
The voltage comparator connected to the node judges that the analog input signal voltage value is larger than the comparison reference voltage value, outputs 1 level (high level of the logic amplitude level), and the voltage comparison circuit connected to VR5, VR6, VR7. The detector judges that the analog input signal voltage value is smaller than the comparison reference voltage value and outputs 0 level (low level of logic amplitude level). In this way, when the analog input signal voltage ANi exists between the comparison reference voltages VR4 and VR5, the voltage comparator string 5 outputs the output of the voltage comparator connected between VR4 and VR5 from 0 level to 1 level. The comparison result C7 to C1 (0001111) which changes to the level is output. The code selection circuit 8 detects a boundary between the 0-level and 1-level of the input bit string C7 to C1 and sets only the bit corresponding to the position of the boundary to the 1-level and sets all the other bit strings to the 0-level to select a code. Signals P7 to P1 (000100
0) is output. The encoding circuit 9 outputs a 3-bit binary code determined corresponding to the 1-level position of the code selection signals P7 to P1 output from the code selection circuit 8. The 3-bit binary code output from the encoding circuit 9 is converted into a 3-bit binary code (100) by the code conversion circuit 10, and this becomes the A / D conversion output 11. Like this
The output value of the / D converter changes with the reference voltage as the threshold value. FIG. 4B shows the relationship between the reference voltage VRi and the output value of the A / D converter. The above is the operation of the parallel A / D converter.

In order to realize a high resolution A / D converter, it is necessary to divide the two reference voltages 1 and 2 with many reference resistors. That is, as the resolution of the A / D converter increases, the potential difference between adjacent comparison reference voltages also decreases. At this time, however, in the A / D converter composed of CMOS transistors in particular, the constituent elements of each circuit are There is a problem that a miscode occurs in the A / D conversion output 11 due to the variation of the above. As a means for solving this problem, a structure for outputting the Gray code shown in (Table 1) or the pseudo Gray code shown in (Table 2) is generally used for the encoding circuit 9 in FIG. The converter once converts the voltage comparison result into a gray code or a pseudo gray code, and then converts it into a binary code by the code conversion circuit 10 and outputs the A / D conversion result (JP-A-58-71726 and JP-A-62-62). 3272
4).

[0006]

[Table 1]

[0007]

[Table 2]

The mechanism for preventing the occurrence of miss codes by the gray code shown in (Table 1) and the pseudo gray code shown in (Table 2) will be described below. For example, if the potential difference between VR4 and VR5 is very small under the above conditions in FIG. 2, it is connected to VR5 due to variations in the components of the voltage comparator connected to VR4 and the voltage comparator connected to VR5. The output voltage comparator judges that the analog input signal voltage value is larger than the comparison reference voltage value and outputs 1 level, and the voltage comparator connected to VR4 has an analog input signal voltage value higher than the comparison reference voltage value. The phenomenon that the level is judged to be small and 0 level is output occurs, and the voltage comparator array 5 causes the incorrect comparison result C7
~ C1 (0010111) is output. Code selection circuit 8
Due to incorrect output of the voltage comparator array 5, P5, P4, P
Incorrect code selection signals P7 to P1 (0011100) for setting the three outputs of 3 to 1 level are output. Encoding circuit 9
Then, the composite code of three binary codes corresponding to one level of the incorrect output of the code selection circuit 8 is output. Here, the encoding circuit 9 of the 6-bit A / D converter is (Table 3).
Consider a case in which the structure outputs a 6-bit binary code shown in.

[0009]

[Table 3]

Now, the code selection signal is a decimal number 14, 1
If three binary codes corresponding to 5 and 16 are selected, three codes of 001110, 001111, and 010000 are simultaneously selected. The encoding circuit 9 outputs the composite code of the three codes with priority on the 0 level (AN
0 (000000) is output in decimal when outputting (D output), and 1 when outputting with 1 level priority (OR output)
31 (011111) is output as a decimal number. When the structure for outputting the binary code to the encoding circuit 9 is used in this way, the A / D conversion output 11 becomes a miscode for the incorrect comparison result of the voltage comparator array 5.

On the other hand, when the encoding circuit 9 has a structure for outputting a 6-bit Gray code as shown in (Table 1), under the above conditions, 001001, 001000,
When three codes of 011000 are selected at the same time, and the encoding circuit 9 outputs 15 (10
00) or 17 (01100 in decimal) for OR output
1) is output. In addition, the encoding circuit 9 has 6 shown in (Table 2).
In the case of a structure that outputs a pseudo gray code of bits, if the code selection signal selects three binary codes corresponding to decimal numbers 14, 15, and 16, 0010
Three codes 11, 001010, and 011111 are selected at the same time, and the encoding circuit 9 is 15 (001010) in decimal when it is an AND output and 1 when it is an OR output.
16 (011111) is output as a decimal number. In this way, if the structure for outputting the gray code shown in (Table 1) or the pseudo gray code shown in (Table 2) is used for the encoding circuit 9, the A / D conversion is performed for the wrong comparison result of the voltage comparator array 5. It is possible to prevent the generation of miscoded conversion output.

However, in the structure shown in FIG.
Considering the case where an analog signal satisfying the condition of Ni = VR4 is input, the comparison result C of the voltage comparator connected to VR4
4 is an intermediate level between 0 level and 1 level. If there are variations in the constituent elements of the two exclusive OR circuits that output P3 and P4 to the input C4 in the code selection circuit 8, both outputs P3 and P4 may output 0 level. In such a case, the code selection signal input to the encoding circuit 9 is in the non-selection state (0000000),
Depending on the structure of the code conversion circuit 9, the A / D conversion output 11 generates a miscode having a minimum value (000) or a maximum value (111). In order to avoid this phenomenon, in FIG. 3, the outputs CK-1 and CK + 1 (K = 2, 3, 4, 5,
The exclusive OR of 6) is used as the code selection signal PK (Japanese Patent Laid-Open No. 63-269829).

The operation of the A / D converter shown in FIG. 3 will be described below. For example, when the reference voltages 1 and 2 are selected so that VR8> VR0 in FIG. 3, when an analog signal satisfying the condition of VR5>ANi> VR4 is input, the voltage comparator array 5 has a voltage comparator array between VR5 and VR4. The comparison result C7 to C1 in which the output of the connected voltage comparator changes from 1 level to 0 level
(0001111) is output. The code selection circuit 12 is
The 0-level and 1-level boundaries of the input bit string are detected, two bits corresponding to the position of the boundary are set to 1 level, and the code selection signals P7 to P1 (0011000) in which all other bit strings are set to 0 level are output. Output. Encoding circuit 1
Reference numeral 3 has a structure for outputting (AND-outputting) a composite code of two 3-bit binary codes respectively corresponding to the two 1-level positions of the code selection signal with 0 level priority. The 3-bit binary code output from the encoding circuit 13 is converted into a 3-bit binary code (100) by the code conversion circuit 10, and this is the output of the A / D converter. According to this structure, for example, when an analog signal satisfying the condition of ANi = VR4 is input, the code selection is performed even if the comparison result C4 of the voltage comparator connected to VR4 becomes the intermediate level between 0 level and 1 level. The output P4 for the input C5 (0 level) and C3 (1 level) in the circuit 12 is 1
The level is output, and the code output by the code selection circuit 12 is not at least in the non-selected state. Therefore, the A / D
The conversion output 11 has a minimum value (000) or a maximum value (11
There is no mistake in 1).

In order to prevent the occurrence of a miscode in the structure as shown in FIG. 3, the pseudo gray code shown in (Table 4) is effective in addition to the gray code shown in (Table 1) (Japanese Patent Laid-Open No. Hei 1). -202928).

[0015]

[Table 4]

A mechanism for preventing a miscode when the structure for outputting the pseudo gray code shown in (Table 4) is used for the encoding circuit 13 in FIG. 3 will be described below. For example, in FIG. 3, reference voltages 1 and 2 are set so that VR0 <VR8.
And the analog signal 7 satisfying the condition of VR4 <ANi <VR5 is input, and the potential difference between VR4 and VR5 is very small, the voltage comparator connected to VR4 and the voltage comparator connected to VR5 are selected. The voltage comparator array 5 has an erroneous comparison result C7 to C1 (0010111) due to variations in the constituent elements of
Is output. The code selection circuit 12 outputs erroneous code selection signals P7 to P1 (0100100) that set the two outputs P6 and P3 to one level due to the erroneous output of the voltage comparator array 5. Here, consider a case where the encoding circuit 13 of the 6-bit A / D converter has a structure for outputting a 6-bit pseudo Gray code shown in (Table 4). Table 5 shows setting codes for the encoding circuit 13 to output the 6-bit pseudo Gray code shown in Table 4.

[0017]

[Table 5]

Now, the code selection signal is a decimal number 13, 1
If two code setting codes corresponding to No. 6 are selected, two codes 001001 and 0011110 are simultaneously selected from (Table 4). The encoding circuit 13 outputs an AND output (001000) of the selected two codes. From Table 4, the code (001000) output from the encoding circuit is a decimal number corresponding to 12, and the error in the A / D conversion output 11 is small. As described above, even when the encoding circuit 13 shown in FIG. 3 has the structure for outputting the pseudo gray code shown in (Table 4), it has the function of preventing the occurrence of a miscode in the A / D conversion output 11.

As described above, in order to prevent the occurrence of output miscode in the A / D converter, (Table 1)
The gray code shown in, the pseudo gray code shown in (Table 2), and the pseudo gray code shown in (Table 4) are effective.
The Gray code has a long conversion time when it is converted into a binary code, which is disadvantageous for increasing the speed of the A / D converter. FIG. 5 shows a code conversion circuit for converting the 6-bit Gray code input 14 into the 6-bit binary code output 15. However, in order to output the least significant bit B1 of the 6-bit binary code, 5 exclusive codes are required. It is necessary to pass the logical sum circuit 16. That is, since the least significant bit output of the N-bit binary code is output after passing through N-1 exclusive OR circuits, the conversion time to the binary code becomes longer as the resolution of the A / D converter increases. .

On the other hand, the pseudo gray code shown in (Table 2) and the pseudo gray code shown in (Table 4) are short in conversion time to a binary code, and are advantageous for increasing the speed of the A / D converter. . FIG. 6 shows the 6-bit pseudo gray code input 17 shown in (Table 2) and the 6-bit binary code output 15
The pseudo gray code shown in (Table 2) can be converted into a binary code by passing through only one exclusive OR circuit 16 for all bits except the most significant bit. is there. FIG. 7 shows 6 in (Table 4).
This is a code conversion circuit that converts a bit pseudo Gray code input 18 into a 6 bit binary code output 15. The pseudo gray code shown in (Table 4) is one for the other bits except the most significant bit and the least significant bit. The binary code is output only by passing through the exclusive OR circuit 16 and the binary code is also output for the least significant bit B1 only by passing through the two exclusive OR circuits 16. As described above, the pseudo gray code shown in (Table 2) and the pseudo gray code shown in (Table 4) are always converted into the binary code at high speed regardless of the resolution of the A / D converter.

When the bits of the binary code output from the encoding circuits 9 and 13 in the A / D converters shown in FIGS. 2 and 3 are sign-reversed from 0 level to 1 level or from 1 level to 0 level. Causes the generation of noise, which causes the comparison reference voltage value or the voltage value of the analog input signal 7 to fluctuate and deteriorates the voltage comparison accuracy of the voltage comparator array 5. The Gray code is calculated every time the boundary between the 0 level and the 1 level of the comparison result of the voltage comparator array 5 increases or decreases by one.
Since the sign inversion always has only one bit, the occurrence of noise accompanying the sign change is always the minimum, and the voltage comparator array 5
There is an advantage that the influence on the voltage comparison accuracy is always minimal. However, as shown in (Table 6) for the pseudo gray code shown in (Table 2) and as shown in (Table 7) for the pseudo gray code shown in (Table 4), a specific value increases or decreases. At this time, the sign inversion occurs at a plurality of bits at the same time, so that the noise caused by the sign change is large, and therefore the influence on the comparison accuracy of the voltage comparator array 5 is large, which deteriorates the accuracy of the A / D converter. To have.

[0022]

[Table 6]

[0023]

[Table 7]

[0024]

[Problems to be Solved by the Invention] As shown above,
Gray code or pseudo Gray code is used for the binary code output of the encoding circuit in the conventional A / D converter in order to prevent the occurrence of a miss code. In addition, the conversion time is long, which is disadvantageous in increasing the speed of the A / D converter. On the other hand, the pseudo Gray code has a drawback in that many bits are simultaneously sign-inverted when a certain value is increased or decreased, so that noise is largely generated due to a sign change and the accuracy of the A / D converter is deteriorated.

In view of the above problems, the present invention has a short conversion time to a binary code and is therefore advantageous for increasing the speed of an A / D converter, and the number of bits whose sign is inverted at the same time when the value increases or decreases. To realize a high-speed and high-accuracy A / D converter by using a binary code that is advantageous in increasing the accuracy of the A / D converter in the encoding circuit of the A / D converter. With the goal.

[0026]

In order to achieve the above object, in the present invention, for at least two bits including the least significant bit of a binary code output, the j-th bit of a binary code input and the binary code. Output of the (j +
1) The exclusive OR of bits is output as a binary code of the jth bit, and the remaining bits are the kth bit of the binary code and the (k + 1) th bit of the binary code. The code conversion circuit is configured so that the binary code input is set so as to be output as a binary code of bits. Further, the code conversion circuit is used for an A / D converter.

[0027]

By using the above binary code and code conversion circuit in the A / D converter, the conversion time to the binary code is short, so that high speed operation is possible, and the increase / decrease of the comparison result of the voltage comparator array is simultaneously performed. Since the number of bits in which the sign changes is small, it is possible to realize an A / D converter that has a small amount of noise and is highly accurate, and that is also effective in preventing the occurrence of miscode.

[0028]

(Embodiment 1) As an embodiment according to claim 1 of the present invention, in a code conversion circuit for converting a binary code into a binary code, for example, the (3j + 1) th bit (j = 0, 1, 2, ...) is output by an exclusive OR of the (3j + 1) th bit of the binary code and the (3j + 2) th bit of the binary code, and the remaining bits are the binary code of the present invention. 2 as the binary code of the k-th bit by the exclusive OR of the k-th bit of the and the (k + 1) -th bit of the binary code.
The structure of the code conversion circuit with the base code set. That is, in the binary code in the present embodiment, the (3j + 1) th bit is set similarly to the (3j + 1) th bit of the conventional Gray code, and the remaining kth bit is the kth bit of the conventional pseudo Gray code. It is set by the same method.

FIG. 1 shows a code conversion circuit for outputting a 6-bit binary code according to this embodiment. An exclusive OR of the fifth bit output B5 of the binary code output 15 and the fourth bit binary code input 19 is performed using the Gray code type exclusive OR 16b, and a fourth bit binary code B4 is output. . Similarly, the exclusive OR of the output B2 of the second bit and the binary code input 19 of the least significant bit is performed using the Gray code type exclusive OR 16b, and the binary code B1 of the least significant bit is output. For the remaining binary code outputs B2, B3, and B5, the exclusive OR of the kth bit (k = 2, 3, 5) of the binary code and the (k + 1) th bit of the binary code is calculated as a pseudo gray code. This is performed by using the type exclusive OR 16a, and the binary code Bk of the kth bit is output. According to this structure,
The conversion speed from the binary code to the binary code output 15 is equivalent to that when using the conventional pseudo Gray code shown in FIG. 7 and (Table 4), and passes through at most two exclusive OR circuits. The binary code output 15 is obtained later.

Table 8 is a 6-bit binary code according to the present embodiment capable of outputting a 6-bit binary code by using the code conversion circuit shown in FIG. 1, the least significant bit and the fourth bit.
The bits are set similarly to the least significant bit and the fourth bit of the conventional Gray code shown in (Table 1), and the remaining 2nd, 3rd, and 5th bits are the conventional pseudo Gray code shown in (Table 2). It is set in the same way as.

[0031]

[Table 8]

[0032]

[Table 9]

Further, as shown in (Table 9), the binary code used in the code conversion circuit of the present invention is as described above (Table 6),
Compared to the case of the conventional pseudo-Gray code shown in (Table 4), the number of bits whose sign is inverted at the same time is smaller, so that the noise caused by the sign change is reduced. The binary code of the present invention shown in (Table 8) is used as the setting code of the encoding circuit 9 in the A / D converter shown in FIG. 2, and the code conversion circuit of the present invention shown in FIG. 1 is used as the code conversion circuit 10. Thus, the generation of noise that affects the voltage comparison accuracy of the voltage comparator array 5 is small, and it is possible to realize a highly accurate A / D converter. Further, this effect becomes more remarkable as the number of bits of the binary code increases, and thus it is advantageous to realize a high resolution A / D converter. High speed and high precision A
A / D converter can be obtained, and it is effective in preventing the occurrence of a miss code as well as the conventional Gray code and pseudo Gray code.

The operation of preventing the occurrence of a miss code when the binary code of the present invention is used in the A / D converter shown in FIG. 2 will be described below. For example, in FIG. 2, VR0 <V
Select reference voltage 1 and 2 so that R8, VR4 <ANi <VR
VR when analog signal 7 that satisfies the condition 5 is input
4. If the potential difference between VR5 and VR5 is very small, the voltage comparator connected to VR5 will have a comparative reference voltage due to variations in the components of the voltage comparator connected to VR4 and the voltage comparator connected to VR5. The analog input signal voltage value is judged to be larger than the value and outputs 1 level, and the voltage comparator connected to VR4 judges that the analog input signal voltage value is smaller than the comparison reference voltage value and outputs 0 level. Occurs, and the voltage comparator array 5 causes incorrect comparison results C7 to C1 (00
10111) is output. The code selection circuit 8 uses the erroneous output of the voltage comparator array 5 to set the erroneous code selection signals P7 to P1 (0
011100) is output. The encoding circuit 9 outputs a composite code of three binary codes corresponding to one level of the incorrect output of the code selection circuit 8. Here, consider a case where the encoding circuit 9 of the 6-bit A / D converter has a structure for outputting the 6-bit binary code of the present invention shown in (Table 8). Now the code selection signals are decimal numbers 14, 15, 1
If three codes corresponding to 6 are selected, 001
Three codes of 011, 001010 and 011110 are selected at the same time. The encoding circuit 9 outputs 15 (001010) in a decimal number as a composite code of three codes, and outputs 1 (0,0110) in decimal when giving priority to 0 level (AND output).
When the level is given priority (OR output), 17 (011111) is output in decimal. As described above, even when the binary code of the present invention is used for the A / D converter shown in FIG.
It is possible to prevent the generation of miscoded conversion output.

In this embodiment, binary code output 1
The outputs B1 and B4 of the first and fourth bits in No. 5 are output using the Gray code type exclusive OR 16b, and the pseudo binary code type exclusive OR 16a is output for the remaining binary code outputs B2, B3, and B5. However, the bit position in the binary code output 15 output using the Gray code type exclusive OR 16b may be any, and in this case, the bit position of the encoding circuit 9 corresponding to the bit position is the gray code. , And the bit positions of the encoding circuit 9 corresponding to the remaining bit positions may be set to the pseudo Gray code.

Further, at the two places of the outputs B1 and B4 of the first and fourth bits in the binary code output 15, the gray code type exclusive OR 16b is used for output. ) May be output using the Gray code type exclusive OR 16b. That is, if the pseudo Gray code type exclusive OR 16a is output at at least one place, a high-speed and high-accuracy A / D converter can be obtained as in the above embodiment.

(Embodiment 2) The above description is about the operation when the binary code of the present invention is used in the A / D converter shown in FIG. Is also used in the A / D converter shown in FIG.
A highly accurate A / D converter can be obtained. in this case,
In order to output the binary code of the present invention shown in (Table 8),
The coding circuit setting code shown in (Table 10) is used for the coding circuit 13 in FIG.

[0038]

[Table 10]

Adjacent two output from the code selection circuit 12
Assuming that two binary codes k and (k + 1) in decimal in Table 10 are selected corresponding to each one level, the encoding circuit 13 outputs an AND of the two codes.
As the output, the binary code corresponding to k in decimal in Table 10 is output. Code conversion circuit 1 in FIG.
By using the code conversion circuit of the present invention shown in FIG. 1 for 0, the binary code output from the encoding circuit 13 is converted into a binary code, which is the A / D conversion output 1
It becomes 1. Also in this case, it is effective to prevent the occurrence of miscode.

The operation of preventing a miscode when the binary code of the present invention is used in the A / D converter shown in FIG. 3 will be described below. For example, under the above-mentioned conditions in FIG. 3, the voltage comparator array 5 produces incorrect comparison results C7 to C1 (001011).
When 1) is output, the code selection circuit 12 causes the erroneous output of the voltage comparator array 5 to cause the erroneous code selection signals P7 to P1 (010) to set the two outputs of P6 and P3 to 1 level.
0100) is output.

Consider a case where the encoding circuit 13 of the 6-bit A / D converter has a structure for outputting the 6-bit binary code of the present invention shown in (Table 8). Assuming that the code selection signal selects a code corresponding to decimal numbers 13 and 16, two codes of 001001 and 0011110 in the coding circuit setting code shown in (Table 10) are simultaneously selected, and the coding circuit 13 Is selected 2
The AND output (001000) of the two codes is output as the binary code of the present invention. From Table 8, the binary code (00100) output from the encoding circuit 13 is output.
0) is a number corresponding to 12 in decimal, and the error in the A / D conversion output 11 is small. Thus, the A / D shown in FIG.
Even when the binary code of the present invention is used for the converter, it also has a function of preventing the occurrence of a miscode in the A / D conversion output 11.

In this embodiment, binary code output 1
The outputs B1 and B4 of the first and fourth bits in No. 5 are output using the Gray code type exclusive OR 16b, and the pseudo binary code type exclusive OR 16a is output for the remaining binary code outputs B2, B3, and B5. However, the bit position in the binary code output 15 output using the Gray code type exclusive OR 16b may be any, and in this case, the bit position of the encoding circuit 9 corresponding to the bit position is the gray code. Is set to be output, and the bit positions of the encoding circuit 9 corresponding to the remaining bit positions may be set to output the pseudo Gray code.

Furthermore, at the two locations of the first and fourth bit outputs B1 and B4 in the binary code output 15, the gray code type exclusive OR 16b is used to output (the number of bits of the binary code output-2-2 ) May be output using the Gray code type exclusive OR 16b. That is, if the pseudo Gray code type exclusive OR 16a is output at at least one place, a high-speed and high-accuracy A / D converter can be obtained as in the above embodiment.

[0044]

By using the binary code and code conversion circuit of the present invention in the A / D converter, the conversion time to the binary code is short, so that high speed operation is possible and the comparison result of the voltage comparator array is increased or decreased. On the other hand, since the number of bits whose sign is inverted at the same time is small, it is possible to realize an A / D converter which has a small amount of noise and is highly accurate, and which is also effective in preventing the occurrence of a miscode.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a code conversion circuit for converting a binary code of the present invention into a binary code.

FIG. 2 is a block diagram of a conventional parallel type A / D converter.

FIG. 3 is a block diagram of a conventional parallel type A / D converter.

FIG. 4A is a diagram showing the voltage value of the analog signal with respect to the time when the A / D converter samples the analog signal;
(B) is an operation explanatory diagram of the A / D converter showing the output value of the A / D converter with respect to the analog input voltage value.

FIG. 5 is a configuration diagram of a code conversion circuit for converting a conventional Gray code into a binary code.

FIG. 6 is a configuration diagram of a conventional code conversion circuit for converting a pseudo Gray code into a binary code.

FIG. 7 is a block diagram of a code conversion circuit for converting a conventional pseudo Gray code into a binary code.

[Explanation of symbols]

 1,2 Reference voltage 3 Reference resistance series 4 Reference resistance 5 Voltage comparator series 6 Voltage comparator 7 Analog input signal 8,12 Code selection circuit 9,13 Coding circuit 10 Code conversion circuit 11 A / D conversion output 15 Binary code Output 16a Pseudo code Gray code type exclusive OR circuit 16b Gray code type exclusive OR circuit 19 Binary code input

Claims (3)

[Claims] 1. A code conversion circuit for converting an input of a binary code into a binary code and outputting the binary code, wherein the binary code is applied to at least two or more bits including the least significant bit of the binary code excluding the most significant bit. Is output as the binary code of the j-th bit by the exclusive OR of the j-th bit of the binary code and the (j + 1) -th bit of the binary code, and the remaining bits are the k-th bit of the binary code and the second bit of the binary code. A code conversion circuit in which a binary code is set so as to be output as the binary code of the kth bit by an exclusive OR of (k + 1) bits. 2. Means for generating a plurality of comparative reference voltages that increase or decrease in order to sample an analog voltage value that fluctuates over time and convert it into a digital value, and the analog voltage value and the comparison value. A voltage comparator array that compares reference voltage values and outputs a comparison result, and the i-th voltage when the order of the voltage comparators in the voltage comparator array is i in the order in which the comparison reference voltage increases or decreases. A code selection circuit that outputs the i-th code selection signal using the comparison result of the comparator and the comparison result of the (i + 1) th voltage comparator as inputs, and an i-th code selection signal of the code selection circuit. An encoding circuit that outputs a selected binary code; and a code conversion circuit that converts the binary code into a binary code and outputs the binary code, The encoding circuit outputs the binary code according to claim 1,
An A / D converter, wherein the code conversion circuit comprises the code conversion circuit according to claim 1. 3. A means for generating a plurality of comparison reference voltages that increase or decrease in order to sample an analog voltage value that fluctuates over time and convert it into a digital value, and the analog voltage value and the comparison value. A voltage comparator array that compares reference voltage values and outputs a comparison result, and the i-th voltage when the order of the voltage comparators in the voltage comparator array is i in the order in which the comparison reference voltage increases or decreases. A code selection circuit that outputs the i-th code selection signal using the comparison result of the comparator and the comparison result of the (i + 2) th voltage comparator as input, and is selected by the i-th code selection signal of the code selection circuit An encoding circuit for outputting a composite code of the selected binary code and the binary code selected by the (i + 1) th code selection signal; A code conversion circuit for converting into a Nari code and outputting as the digital value, wherein the encoding circuit outputs the binary code according to claim 1.
An A / D converter, wherein the code conversion circuit comprises the code conversion circuit according to claim 1.