JPH06993A - Printing device - Google Patents

Abstract

(57) [Summary] [Object] To provide a printing apparatus capable of high-speed transfer by outputting a transfer clock according to a first and a second reference clock. [Structure] J-Sampling BD signal 101 from a printer unit (not shown) at the rising edge of CLK signal 102
K. The FF 103 or the JK. When any one of the FFs 104 becomes valid, the other JK. FF is the AND gate 105, 106
Masked by. Then, a valid JK. The CLK signal or its inverted signal is output from the AND gate 10 by the Q output of the FF.
8 and 109 are supplied to the counter 112 through the OR gate 110, and the VCK signal 12 is supplied by the signal.
4 is output to a video signal transfer circuit (not shown).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing apparatus for printing image data transferred from a controller section to a printer section via printer interface means.

[0002]

2. Description of the Related Art Conventionally, in a raster scan type printer such as a laser beam printer, a controller section and a printer section (not shown) are provided, and a synchronizing circuit in a printer interface circuit section in the controller section is constructed as shown in FIG. .

In the figure, 501 is a JK flip-flop (hereinafter abbreviated as FF), 502 is a negative logic OR gate, 503 is a binary up counter, and 5
Reference numeral 04 is a beam detect (synchronization) signal (hereinafter abbreviated as BD) input from a printer unit (not shown), 505 is a reference clock (hereinafter abbreviated as CLK), and 506 is a reset signal in this circuit block, 507 is J
-K. The Q output of the FF 501, the Qc output of the binary up counter 503, and the video signal transmission clock in the subsequent circuit blocks (hereinafter V
Abbreviated as CK). 509 is a reset signal for the binary up counter 503.

The operating principle will be described below with reference to FIG.

First, the CLK signal 505 is a reference clock and is supplied from a circuit device such as an oscillator. B
The D signal 504 is kept at a low level inside the printer until the print start timing. Reset signal 50
6 is JK. After initializing the FF 501 and the binary up counter 503, it is fixed at a high level. In addition, JK. After the FF 501 is initialized, the J input is at the low level and the K input is also at the low level, so the Q output 507 is fixed at the low level, becomes the reset signal 509 through the gate 502, and resets the binary up counter 503. Hold on.

Next, when the printing operation is started, the paper position is at a printable position in the printer, and the BD signal 504 becomes high level when the laser beam scans and reaches a certain reference position, J -K. Since the J input of the FF 501 is at the high level, the Q output thereof is at the high level, the reset state of the counter 503 is released, and the counter 503 receives the C input after the reset state is released.
Counting is started by the LK signal 505, and the VCK signal 5
Since 08 is connected to the Qc output of the counter 503, as a result, the VCK signal 508 becomes a signal having a frequency ⅛ of that of the CLK signal 505. The timing chart at this time is shown in FIG.

Here, the meaning of the above-mentioned circuit is shown in FIGS. 6 and 7.
This will be described with reference to the timing chart shown in FIG.

First, in FIG. 6, the BD signal 504 is C
It is written so as not to conflict with the LK signal 505. This is because the BD signal 504 is generally input at an asynchronous timing with respect to the CLK signal 505, and as shown in FIG. 6, the BD signal 504 is not always input with a sufficient setup margin with respect to the rising edge of the CLK signal 505. That is, as shown in FIG. 7, BD signal 504 and CLK
It is expected that signal 505 will rise at approximately the same time.
Therefore, as a result, there are two kinds of phenomena such as case 1 and case 2 shown in FIG.

Case 1: The rising edge of BD is set to JK. F
When F is caught Case 1: The rising edge of BD is set to JK. When the FF is not captured, that is, in the worst case, the synchronization deviation of the above case exists with respect to the input timing of the BD signal 504. The synchronization shift is called a jitter and is a value determined by the sampling frequency, and is a value for one cycle of the CLK signal 505 indicated by Tz in the example of FIG.

If the jitter is greater than a certain ratio with respect to the dot width, it causes deterioration of the printing result. Therefore, it is generally necessary to suppress the jitter to about 1/8 of the dot width.

Therefore, in the circuit of FIG. 5, the frequency of the CLK signal is eight times the frequency of the video clock, and the B signal is generated by the CLK signal.
After sampling the D signal, V
Making a CK signal.

FIG. 8 shows a case in which the CLK signal and the VCK signal have the same frequency, and as shown in the figure, a full dot of jitter is generated, which is not practical.

[0013]

However, in the above-mentioned conventional example, when the jitter is determined to be 1/8 of the dot width, the reference clock CLK signal needs to have a frequency eight times that of the video transfer clock VCK signal. To
In recent years, as the dot density of devices and the printing speed have improved, it has become necessary for the video transfer frequency itself to be quite high, and it has become difficult to create a frequency eight times that frequency.

The present invention has been made to solve the above problems, and provides a printing apparatus capable of high-speed transfer by outputting a transfer clock according to the first and second reference clocks. To aim.

[0015]

In order to achieve the above object, the printing apparatus of the present invention has the following configuration.

That is, in the printing apparatus for printing the image data transferred from the controller section to the printer section through the printer interface section, the first sampling section for sampling the synchronizing signal from the printer section at the first reference clock. And second sampling means for sampling the synchronizing signal from the printer section with the second reference clock, and either the first or second reference clock based on the sampling by the first and second sampling means. And selecting means for selecting, and output means for outputting a transfer clock for transferring the image data according to the reference clock selected by the selecting means.

[0017]

In the above structure, the synchronization signal input from the printer section to the controller section is sampled at the first reference clock and at the second reference clock, and the first or the first reference clock is sampled based on the sampling. Two
Select either of the reference clocks of. Then, the transfer clock for transferring the image data is output according to the selected reference clock.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a synchronizing circuit section in the main scanning direction in the printer interface circuit section. By using not only the rising edge but also the falling edge of the reference clock, the frequency required conventionally is It realizes the same jitter standard at 1/2 frequency.

In the figure, 101 is a BD signal, which is input from a printer unit (not shown). Reference numeral 102 is a reference clock of the present synchronizing circuit. The signal 119 input to the FF 103 and inverted through the inverter gate 107 is output by the JK. It is also input to the FF 104. 105,
Reference numeral 106 is an AND gate, and each output 113,
114 is each JK. It is input to the J input terminals of the FFs 103 and 104. Reference numeral 108 denotes an AND gate, which is a JK. F
The Q output 116 of F104 and the CLK signal 102 are ANDed, and the output 120 is input to the OR gate 110. 109 is an AND gate, and JK. FF103
Of the Q output 115 and the inverted signal 119 of the CLK signal 102 are ANDed, and the output 121 is input to the OR gate 110. Reference numeral 110 is an OR gate, which has the output 12 described above.
The logical sum of 0 and 121 is performed, and the output 122 is input to the clock terminal of the counter 112. Reference numeral 111 is an OR gate, and JK. Q output 11 of FF103, 104
The logical sum of 5, 116 is performed, and the output 123 is input to the reset terminal of the counter 112. A VCK signal 124 is output from the Qb terminal of the counter 112, and outputs a frequency signal of 1/4 of the supplied clock signal 122 to a video signal transfer circuit (not shown). 125,126
Are JK. This is a K input to the FFs 103 and 104, and is fixed at a low level. Further, 127 is a reset signal, which is inputted as needed from a control circuit of a controller unit (not shown).

Next, the operation of the circuit shown in FIG. 1 will be described with reference to the timing charts shown in FIGS.

1) When the BD signal 101 is input with a margin with respect to the rising edge of the CLK signal 102. For this case, refer to the timing chart in FIG.

First, the JK. It is assumed that the FFs 103 and 104 are reset, and the Q outputs 115 and 116 are initialized to a low level and then the reset signal is released. Each Q output 115, 116 (low level) is input to the OR gate 111, and its output 123 is the counter 112.
Input to the reset terminal of the counter 112 and holds the counter 112 in the reset state. The Q outputs 115 and 116 are also connected to the AND gates 108 and 109, respectively, and the CLK signal 102 and the nCLK signal 119 that are connected to the other input terminals of the AND gates 108 and 109, respectively.
Are masked. Then, each JK. FF103, 1
Since the nQ outputs 117 and 118 of 04 are high level, the high level is supplied to the AND gates 105 and 106. The BD signal 101 is connected to the other input terminals of the AND gates 105 and 106,
The signal 101 is kept at the low level until the print start timing.

Next, when the BD signal 101 is input, AN
The D gates 105 and 106 respectively set the high level to the next JK. It is supplied to the J input terminals of the FFs 103 and 104, and then the JK. The FF 103 inverts the output at the rising edge of the clock of CLK 102. This JK. FF1
With the output inversion of 03, the nQ output 117 becomes low level, supplies the low level to the AND gate 106, and masks the BD signal 101 which is the other terminal signal. Then J-K. The J input terminal of the FF 104 is fixed to low level again. That is, JK. C to FF104
Even if the LK signal 102 is input, since the J input terminal is at the low level, the Q and nQ outputs 116 and 118 of the FF 104
Keeps the initial state.

Further, since the Q output 115 of the FF 103 becomes high level, the high level output 123 is supplied to the reset terminal of the counter 112 through the OR gate 111, thereby making the counter 112 operable. Further, since the Q output 115 of the FF 103 becomes high level, the nCLK signal 119 which is the CLK signal passed through the inverter gate 107 is directly output from the AND gate 109, and the output 121 thereof is passed through the OR gate 110 to the clock terminal of the counter 112. Is supplied to. This causes the counter 112 to output the VCK signal 124 from the Qb terminal.
1 that is synchronized with the falling edge of the CLK signal 102 which is the reference clock input to this circuit block.
The signal of frequency 4 is output to the circuit block of the next stage as a video signal transfer clock.

2) When the BD signal 101 is input with a margin with respect to the falling edge of the CLK signal 102. For this case, refer to the timing chart in FIG.

First, the JK. It is assumed that the FFs 103 and 104 are reset, and the Q outputs 115 and 116 are initialized to a low level and then the reset signal is released. Each Q output 115, 116 (low level) is input to the OR gate 111, and its output 123 is the counter 112.
Input to the reset terminal of the counter 112 and holds the counter 112 in the reset state. The Q outputs 115 and 116 are also connected to the AND gates 108 and 109, respectively, and the CLK signal 102 and the nCLK signal 119 that are connected to the other input terminals of the AND gates 108 and 109, respectively.
Are masked. Then, each JK. FF103, 1
Since the nQ outputs 117 and 118 of 04 are high level, the high level is supplied to the AND gates 105 and 106. The BD signal 101 is connected to the other input terminals of the AND gates 105 and 106,
The signal 101 is kept at the low level until the print start timing.

Next, when the BD signal 101 is input, AN
The D gates 105 and 106 respectively set the high level to the next JK. The signal is supplied to the J input terminals of the FFs 103 and 104, and then the falling edge of the clock of the CLK signal 102 is output from the inverter 107 as the nCLK signal 119 by the JK.
It is input to the clock terminal of the FF 104, and the Q and nQ outputs 116 and 118 are inverted. And AND gate 10
5 is supplied with the low-level nQ output 118, masks the BD signal 101, and outputs the low-level output 113 from JK.
It is supplied to the J input terminal of the FF 103, and the J input terminal is fixed to the low level again. That is, after this, FF10
Since the J input terminal is at a low level even when the clock signal is input to the 3rd terminal, the Q and nQ outputs 115 and 11 of the FF 103 are input.
7 continues to hold the initial state.

Further, since the Q output 116 of the FF 104 becomes high level, the high level output 123 is supplied to the reset terminal of the counter 112 through the OR gate 111, thereby making the counter 112 operable. Further, since the Q output 116 of the FF 104 becomes high level, the CLK signal 102 is directly output from the AND gate 108, and its output 121 is supplied to the clock terminal of the counter 112 through the OR gate 110.

As a result, the counter 112 outputs the VCK signal 124 from the Qb terminal, that is, the signal of 1/4 frequency synchronized with the rising edge of the CLK signal 102 which is the reference clock input to this circuit block is used for video signal transfer. Output as a clock to the circuit block at the next stage.

3) Summary Based on the results of the above 1) and 2), the BD signal 101 is set to CLK.
By using the circuit of FIG. 1 when sampling with the signal 102, sampling is performed at the rising edge or the falling edge, whichever comes first, the counter becomes operable from that moment, and then the reference clock is sampled differently. The counter 112 can be operated in synchronization with the rising or falling edge to output the VCK signal 124.

FIG. 4 illustrates the above operation.
In the figure, the BD signal 101 and the CLK signal 102 are shown as intentionally rising at the same timing. At this time, BD
Case 1 is when the rising edge of the signal 101 is faster than the rising edge of the CLK signal 102, and case 2 is when it is late.

In case 1, since the BD signal 101 can be sampled at the rising edge of the CLK signal 102, the output of the FF 103 is inverted, the FF 104 is masked, and the counter 112 is released from the reset state. Signal 119 to counter 11
Supply to 2.

On the other hand, in case 2, CLK signal 1
Since the BD signal 101 could not be sampled at the rising edge of 02, the output of the FF104 is inverted at the next falling clock, masking the FF103 and releasing the reset of the counter 112, and then the CLK signal 10
2 is supplied to the counter 112.

As described above, in order to realize the jitter accuracy of ⅛ in the related art, the reference clock which is eight times the video transfer frequency is required, but by adopting the circuit of FIG. 1 in the embodiment. It is possible to realize a jitter accuracy of 1/8 cycle with a clock four times as high as the video signal transfer frequency.

[0036]

Other Embodiments Next, other embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 9 is a diagram showing a structure of a synchronizing circuit portion in another embodiment, in which a synchronizing D type flip-flop (D-FF) is added to the circuit shown in FIG.

In the figure, 925 and 926 are D-FFs,
The role of the D-FFs 925 and 926 is the function of the JK.
This is to prevent metastable of the FFs 903 and 904. In the above description, in order to simplify the description, JK. The metastable state, which is an unstable state when the input signal of the FF and the clock signal compete with each other, is not taken into consideration. However, in the actual circuit design, the metastable state becomes a problem in the asynchronous signal circuit. In particular, in the circuit of FIG. 1, the JK.
Since the output of the FF is connected to the clock terminal and the reset terminal of the next-stage counter through the respective gates, some measures may be required.

The countermeasure is taken by the D-FF added in this embodiment. The D-FF samples the BD signal at the rising edge and the falling edge, respectively.
K. The BD signal synchronized with the FF is input. That is, B
A conflict between the D signal and the CLK signal occurs, and the D-FF 925,
Even if the 926 becomes a metastable state, the next JK. If the FFs 903 and 904 have returned to the normal state by the time they operate on the clock, there is no problem, and JK. F
F903 and 904 never enter the metastable state.

In the circuit shown in FIG. 9, the D-FF 92
5,926 and JK. Although the FFs 903 and 904 are connected by the anti-phase clock, there is no particular problem with the in-phase clock.

Next, FIG. 10 is a diagram showing a modification of the embodiment shown in FIG. 1, and in FIG. FF10
Although the BD signal 101 connected to the J inputs of 3, 104 is masked, in this example, the CLK signal is masked. That is, the JK. When the output of the FF is inverted, the inversion of the other JK. The clock signal to the FF is forcibly fixed at the low level.

In the embodiment described above, the circuit for dividing the reference clock is a binary up counter for the sake of convenience of explanation, and other circuits may be used.

Also, the jitter accuracy is set to 1 of the video dot width.
However, this is a reasonable value in general, and it was thought that it would not cause confusion if the description was fixed at a fixed value, and these values are not restricted to the present invention. Does not give.

Further, the specification is such that the BD signal is input to the timing circuit asynchronously from the printer unit (not shown). However, these timing circuits are in the printer unit, and the CLK, BD signal or VCK,
It is also possible to input a BD signal.

As a sampling means for achieving synchronization, JK. Although the FF is used, this selection does not impose any restrictions on the present invention, and other circuit means may be used.

Further, although all flip-flops are used as rising clocks and inverted clock signals are used for falling, the specifications of the falling-clock flip-flops are sufficiently expected.

Although the sampling edge and the video transfer clock edge are opposite in phase, they are unified for convenience of explanation, and do not limit the present invention. Therefore, it is determined by the sampled edge from the gist of the present invention. Obviously, in-phase edges may be used.

As described above, according to the embodiment, the reference clock, which is the gist of the present invention, is divided into two systems, the positive phase and the negative phase, and the synchronization circuits are provided for the respective systems. By providing a means for selecting whether to generate the reverse clock of the signal at the rising edge or the falling edge of the reference clock, conventionally, when the jitter accuracy of 1 / N of the video transfer width is required, the reference is N times the video transfer frequency. Whereas the clock was required, the same accuracy can be realized with half the reference clock of N / 2, and the following effects are obtained.

1. High-speed transfer of video signals becomes possible.

2. The frequency of the reference clock device is lowered and the cost is reduced.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device.

It goes without saying that the present invention can also be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0053]

As described above, according to the present invention,
By outputting the transfer clock according to the first and second reference clocks, it is possible to perform the transfer at high speed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration of a synchronization circuit unit in a printer interface circuit unit according to an embodiment.

FIG. 2 is a sampling timing chart at the rising edge of FIG.

FIG. 3 is a sampling timing chart at the falling edge of FIG.

FIG. 4 is a timing chart when the jitter of FIG. 1 is maximized.

FIG. 5 is a diagram showing a configuration of a synchronization circuit section in a printer interface circuit section in a conventional example.

6 is a sampling timing chart at the rising edge of FIG.

FIG. 7 is a timing chart when the jitter in FIG. 5 is maximized.

FIG. 8 shows jitter when the sampling frequency and the video transfer frequency are the same.

FIG. 9 is a diagram showing a configuration of a synchronization circuit unit according to another embodiment.

FIG. 10 is a diagram showing a modification of the circuit unit shown in FIG.

Claims (1)

[Claims] 1. A printing apparatus for printing image data transferred from a controller section to a printer section via a printer interface section, wherein first sampling means samples a synchronization signal from the printer section at a first reference clock. And second sampling means for sampling the synchronizing signal from the printer section with the second reference clock, and either the first or second reference clock based on the sampling by the first and second sampling means. A printing apparatus comprising: a selection unit that selects the image data, and an output unit that outputs a transfer clock that transfers the image data according to the reference clock selected by the selection unit.