JPH07105172A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Configuration] When mounting multiple LSIs on a single chip,
A signal which becomes an internal signal by one chip is assigned to a vacant terminal or shared with an external terminal other than the portion to be tested so that the terminal is switched by a test mode control signal. The input gate and the output buffer of the bus connection part of the circuit other than the tested part are fixed to the high impedance state by the test mode control signal, and the input gate is fixed to the inactive state. [Effect] By setting the test mode, it is possible to selectively test an arbitrary part in the chip, and it becomes possible to input / output all input / output signals of the part to be tested through external terminals. Since the part other than the test part can be separated from the part to be tested, the test pattern already created can be reused for the test.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technique and a technique effective when applied to the testing of a semiconductor integrated circuit. For example, the present invention is applied to a microcomputer configured as an ASIC (special purpose semiconductor integrated circuit). And about effective technology.

[0002]

2. Description of the Related Art Conventionally, an ASIC microcomputer capable of designing and providing a microcomputer having a function required by a user in a short time by combining a microprocessor called a CPU core and a modularized circuit such as a DMA controller and a timer circuit. Is proposed.

[0003]

SUMMARY OF THE INVENTION The inventor of the present invention considered to construct an ASIC microcomputer by combining a general-purpose microcomputer and a gate array incorporating a logic designed by a user. However, the present inventor has clarified that the above technique has the following problems.

That is, when two LSIs of a general-purpose microcomputer and a gate array were mounted on a board and connected by printed wiring, the terminals that were exposed to the outside as terminals of the LSI were integrated into one chip. May cause an internal terminal. Therefore, if you try to reuse the already created general-purpose microcomputer test pattern and gate array test pattern as they are, there will be no external terminal to input the test pattern, and you will have to redesign the test pattern. Sometimes it doesn't.

Further, when the existing test pattern is used as it is, it is required that the circuit on the side not to be tested does not operate during the test. However, a general-purpose microcomputer and a gate array integrated into one chip are required. When and are connected by a bus, it has been clarified that there is a problem that a signal of one circuit is input to the other circuit via the bus to operate.

An object of the present invention is to provide a test in which, when a plurality of LSIs are mounted on one chip, a test pattern already created for each LSI is diverted so that a test can be performed on the chip. To provide control technology. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, when a plurality of LSIs are mounted on one chip, the signal that has become an internal signal due to one chip is shared with external terminals other than the part under test when there are no empty terminals allocated to the empty terminals or there is not enough empty terminals. Then, the terminals are switched by the test mode control signal. Further, the input gate and the output buffer of the bus connection portion of the circuit other than the portion to be tested fix the output buffer to the high impedance state and the input gate to the inactive state by the test mode control signal. To set the test mode, a mode setting external terminal may be separately provided, and the input value thereof may be decoded and used as a mode control signal.

[0008]

According to the above-mentioned means, by setting the test mode, it is possible to selectively test an arbitrary part in the chip and input all the input / output signals of the part to be tested through the external terminals. Since it is possible to output and the part other than the tested part can be separated from the tested part, the purpose of being able to carry out the test by utilizing the already created test pattern is achieved. .

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to an ASIC microcomputer. Although not particularly limited, a portion surrounded by a line indicated by reference symbol A in the drawing is formed on one semiconductor chip such as a single crystal silicon substrate.

In FIG. 1, reference numeral 1 is a microcomputer core portion, and 2 is a gate array core portion. Here, the core section means a functional circuit block obtained by removing an I / O interface section from a normal LSI. The microcomputer core unit 1 and the gate array core unit 2 are connected by an internal system bus 3 and an internal signal line 8. Reference numeral 4 is an external terminal of the LSI. Some of these external terminals 4a and 4b are shared by the microcomputer core unit 1 and the gate array core unit 2, and are selectively selected by the multiplexers 5a and 5b via the terminal 4a or 4b in the test mode. Signals can be input and output from the outside.

That is, the multiplexers 5a and 5b are
Normally selects signals so that the terminal 4a functions as an input / output terminal of the microcomputer core section 1 and the terminal 4b functions as an input / output terminal of the gate array core section 2. On the other hand, in the test mode, the multiplexer 5b selects a signal so that the signal of the internal signal line 8 can be output or input from the terminal 4b when the microcomputer core unit 1 is tested, and the gate array core unit 2 is tested. At this time, the multiplexer 5a selects a signal so that the signal of the internal signal line 8 can be output or input from the terminal 4a.

The multiplexers 5a and 5b are configured to be switched by a mode control signal from a mode control circuit 6 provided on the chip.
Reference numerals 7a and 7b are mode setting external terminals. These terminals 7a and 7b are not connected to the pins when mounted in the package, and a mode setting signal can be applied only when testing by a prober in a wafer state.

FIG. 2 shows a configuration example of a buffer circuit section provided on the bus connection side of the microcomputer core section 1 and the gate array core section 2. The signal line 3a forming the internal system bus 3 is connected to the tristate output buffer 11a of the microcomputer core unit 1 and the tristate output buffer 1 of the gate array core unit 2 as described above.
1b is connected, and an OR gate 12a as an input gate of the microcomputer core section 1 and an OR gate 1 as an input gate of the gate array core section 2
2b are commonly connected.

Although not shown, tri-state output buffers 11a and 11b and an OR gate 12 as an input gate are similarly provided to the other signal lines constituting the internal system bus 3.
a and 12b are commonly connected. The output buffers 11a and 11b and the input gates 12a and 12b
Is controlled by the input / output control circuits 13a and 13b, and functions to disconnect the non-test side circuit from the system bus 3 in the test mode.

The input / output control circuits 13a and 13b are connected to the test mode control signal T from the mode control circuit 6, respectively.
An OR gate G1 which receives M and the input / output control signal Ci / o at its input terminal and takes the logical sum of them, and an input / output control signal Ci / o
And an inverter G2 for inverting
The output signal of the gate G1 is the above-mentioned input gates 12a and 12b.
One of the input terminals and the output signal of the inverter G2 are supplied to the control terminals of the output buffers 11a and 11b.

Table 1 shows the test mode control signal TM.
Also, the relationship between the level of the input / output control signal Ci / o and the operation mode is shown.

[Table 1]

The input / output control circuit 13a (13b) is
When the test mode control signal TM is high level and the input / output control signal Ci / o is low level, the input gate 1
The output of 2a (12b) is fixed to the high level (inactive state), and the output buffer 11a (11b) is set to the output high impedance state. As a result, the microcomputer core unit 1 (gate array core unit 2) is separated from the system bus 3.

On the other hand, when the test mode control signal TM is low level and the input / output control signal Ci / o is low level, the output buffer 11a (11b) is set to the output high impedance state and the input gate 12a is set.
(12b) is activated to take in the signal on the signal line 3a and supply it to the inside. When the test mode control signal TM is at the low level and the input / output control signal Ci / o is at the high level, the input gate 12a (12b) is deactivated and the output buffer 11a (1
1b) is activated and outputs a signal from the inside onto the signal line 3a.

As described above, in the above embodiment, when the microcomputer and the gate array are mounted on one chip, the signal which becomes an internal signal by one chip is transmitted via the multiplexer to a portion other than the tested portion. In addition to being shared with external terminals and switching the terminals by the test mode control signal, the input gate and output buffer of the bus connection part of the circuit other than the part under test make the output buffer high impedance state by the test mode control signal. Since it is fixed and the input gate is fixed to the inactive state, it is possible to selectively test any part in the chip by setting the test mode, and all input / output signals of the part under test. Can be input and output via the external terminals, and the parts other than the tested part can be It is possible to separate from the test part, there is an effect that it becomes so perform the test by diverting a test pattern that has already been created.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the input / output control circuits 13a and 13b are not limited to the configuration shown in FIG. 2, and the mode control circuit 6 is omitted, and the test mode control signal TM and the input / output control signal C are omitted.
It is also possible to provide the i / o directly from the outside with a test probe or the like. In the above description, the case where the invention made by the present inventor is mainly applied to the ASIC microcomputer which is the field of application which is the background of the invention has been described. However, the present invention is not limited thereto, and a plurality of LSIs can be used. When mounted on a chip, it can be generally used.

[0021]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, when a plurality of LSIs are mounted on one chip, the test pattern already created for each LSI can be used to perform the test on the chip.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment when the present invention is applied to an ASIC microcomputer.

FIG. 2 is a circuit diagram showing a configuration example of a buffer circuit section provided on a bus connection side of a microcomputer core section and a gate array core section.

[Explanation of symbols]

 1 Microcomputer Core 2 Gate Array Core 3 Internal System Bus 4a, 4b Terminal 5a, 5b Multiplexer / Demultiplexer 6 Mode Control Circuit 7a, 7b Mode Setting External Terminal 11a, 11b Output Buffer 12a, 12b Input Gate 13a, 13b I / O control circuit

Claims (3)

[Claims] 1. In a semiconductor integrated circuit in which a plurality of functional circuit blocks connected to each other via a bus are formed on the same semiconductor chip, some external terminals are shared by the plurality of functional circuit blocks and signal switching is performed. Is configured to be connectable to any one of the functional circuit blocks via means, and a tristate output buffer and an input gate capable of controlling the input state are provided on the bus connection side of each of the functional circuit blocks. A semiconductor integrated circuit characterized in that the signal switching means, the output buffer, and the input buffer are controlled by a test mode control signal so that signals are input to and output from only one of the functional circuit blocks. 2. The test mode control signal is configured to be supplied from a mode setting circuit formed on the same chip as the semiconductor chip on which the functional circuit block is formed and which is connected to the mode setting terminal. The semiconductor integrated circuit according to claim 1, wherein: 3. The mode setting terminal is formed so that a test probe can be contacted from the outside, and is not connected to any pin when mounted in a package. The semiconductor integrated circuit described.