JPH07105247A - Delay calculation method and delay calculation device for logic simulation - Google Patents

Abstract

PURPOSE:To obtain the delay calculating device which can calculates a delay value with a small error without increasing the calculation quantity by making cell data of respective basic cells into graph data and making graph data to be approximated into common data. CONSTITUTION:The design of a logic circuit includes physical design of the layout pattern of respective elements, wiring, the sizes of the respective elements, etc. According to the physical structure of each designed basic cell, the operation of the basic cell is simulated to verify the logical operation of the basic cell and calculate the delay value (S2). Then parameters required for the arithmetic of a delay value arithmetic unit are extracted by the respective basic cells on the basis of the simulation result (S3). The extracted parameters are graphically represented by the basic cells (S4). The graph data are compared and parts which can be made common are made common to compress the graph data (S5). Consequently, the graph data showing the parameter group of the (n) basic cells are made common to reduce the amount of data to 1/n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay calculation device for calculating a delay value of an element in a logic integrated circuit when simulating the operation of the logic integrated circuit on a computer.

As the speed and the degree of integration of logic integrated circuits have increased in recent years, simulation on computers has become indispensable for verifying the design of logic integrated circuits. However, the electrical characteristics of a large-scale logic integrated circuit
Complete simulation with a circuit simulator is virtually impossible due to the increase in calculation scale. Therefore, in a large-scale logic integrated circuit, only the logical operation of the logic integrated circuit and the delay between each element are simulated and verified.

[0003]

2. Description of the Related Art In a conventional delay calculation device for a logic delay simulator, a parameter for each element calculated by a circuit simulator and wiring data of wiring connecting each element are calculated in advance and stored in a library. The delay value is calculated based on the parameters and the wiring data.

That is, the parameter for each element is a basic delay value of each element calculated under the most frequently used condition and a load dependence coefficient for linearly changing the basic delay value depending on the load connected to each element. Composed of and. The wiring data is a capacitance value existing in the wiring net.

In order to calculate the delay value under various conditions of the logic circuit, the parameter for each element under each condition and the wiring data are applied to a preset linear equation for calculation. Generally, the operation of a transistor is non-linear, but in order to accurately calculate the non-linear operation, a huge amount of calculation is required, which is practically impossible. Therefore, the delay value under all conditions of the logic integrated circuit is obtained as an approximate value by the linear equation as described above.

[0006]

However, in the calculation of the delay value by the rough approximation as described above, if the extraction condition of the parameter of each element is different from the actual use, the calculated delay value is However, there is a problem that a large error occurs with the actual delay value.

Further, as the integration degree of the logic integrated circuit is further increased, the operation speed is further increased, and further, for example, Bi
-In order to reduce the error in the calculated value due to the linear equation as described above when the number of elements increases, such as in a logic integrated circuit of CMOS configuration, it is necessary to complicate the linear equation and increase the number of parameters. is there.

However, in order to reduce the error of the calculated value,
Increasing the complexity of the linear equation and increasing the number of parameters increases the amount of calculation and requires a great deal of time for simulation. Even if the linear equation is complicated and the number of parameters is increased, the error cannot be reduced sufficiently.

An object of the present invention is to provide a delay calculation device capable of calculating a delay value with a small error without increasing the calculation amount.

[0010]

In order to calculate the delay values of a large number of basic cells, cell data is calculated in advance and stored in a library, and a delay value calculator delays each basic cell based on the cell data. Calculate the value. When the cell data of each of the basic cells is converted into graph data and the gradient of the graph data of the cell data is approximate, the approximated graph data is stored in the library as common data. The cell data of the basic cell whose delay value is to be calculated is read from the graph data stored in the library.

[0011]

In the cell data of the basic cells in the form of graph data, the graph data having a similar slope is stored in the library as common data, so that the amount of data stored in the library is compressed. As a result, the cell data amount of each basic cell that can be stored in the library in advance increases without increasing the capacity of the library.

Further, based on the increased cell data for each basic cell, the delay value calculator calculates a correct delay value by a simple calculation.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a delay calculating apparatus embodying the present invention. The circuit design device 1 is composed of a logic design device 2, a layout design device 3, and a cell design device 4.

The logic designing apparatus 2 creates a logic circuit which constitutes a chip or a module based on the input of a circuit diagram or the input of a structure description language which replaces each logic with a specific language and inputs.

Then, the logic design device 2 develops a circuit diagram or structure description language input inputted as data having a hierarchy into the same hierarchy to create a desired logic circuit. The layout designing device 3 lays out the logic circuit designed by the logic designing device 2 and stores the wiring data created by the layout in the first library 5.

The cell designing device 4 designs a basic cell used for designing the logic designing device 2 and stores the cell data in the second library 6. The delay value calculator 7 calculates the delay value of each element of the logic circuit designed by the logic designing device 2 from the wiring data stored in the first library 5 and the cell data stored in the second library 6. And the result of the operation is calculated by the logic simulator 8
Output to.

The logic simulator 8 is based on the delay value calculated by the delay value calculator 7 and is based on the delay value.
Simulate the operation of the logic circuit designed in.
The operation of the cell design device 4 will be described with reference to FIG. The cell designing device 4 designs the logic circuits forming various basic cells as a circuit diagram or by a structure description language.
The design of the logic circuit includes a physical design such as a pattern for laying out each element, a wiring, and a size of each element (step 1).

Next, the cell design device 4 simulates the operation of each basic cell from the designed physical structure of each basic cell, verifies the logical operation of each basic cell, and calculates the delay value. (Step 2).

Next, the cell design device 4 extracts the parameters necessary for the calculation in the delay value calculator 7 for each basic cell based on the simulation result (step 3).

That is, in the operating state of the basic cell,
Parameters are calculated for each basic cell not only in the most frequently used condition but also in all the conditions in which the chip including the basic cell is used.

Next, the cell design device 4 graphs the extracted parameters for each basic cell (step 4).
That is, the extracted parameter is set to the delay value calculator 7
A plurality of graph data are calculated as a set of parameter groups according to the delay calculation formula used in the delay calculation in.

In this graph data, for example, as shown in FIG. 3A, parameter groups L1a, L2a, L3a for three basic conditions for one basic cell are calculated as graph data. Further, as shown in FIG. 4A, parameter groups L1b and L2 for three different conditions for different basic cells are set.
b and L3b are calculated as graph data.

Next, the cell designing device 4 compares the graph data and commonizes the common parts to compress the graph data (step 5). That is, by integrating a group of parameters that draw similar curves as graph data,
Replace the parameter groups of multiple basic cells with one graph data.

For example, as shown in FIG. 3B, the Y intercepts of the parameter groups L1a, L2a and L3a are aligned with "0",
The parameter groups L1aa, L2aa, L3aa are calculated. In addition, as shown in FIG. 4B, the parameter groups L1b, L1
Align the Y intercepts of 2b and L3b to "0", and set the parameter group L1b
Calculate b, L2bb and L3bb.

Then, the cell designing device 4 compares the X and Y coordinates of a plurality of break points C1, C2, C3, C4 in the graph showing the parameter group L3aa and the parameter group L3bb, for example. As a result, if the error in the coordinate values of the break points C1 and C3 and the break points C2 and C4 is within a certain value, the slopes between the break points are approximate, and therefore the parameter groups L3aa and L3bb are different from each other. , Is determined as an approximate graph.

In this way, the cell design device 4 uses the parameter groups L1aa, L2aa, L3aa and the parameter group L1.
If it is determined that bb, L2bb, and L3bb are close to each other, both parameter groups are stored in the second library 6 as one parameter group, and the parameter groups L1a, L2a, L3a, and L1b are stored as data corresponding to each basic cell. , L2b,
The Y-intercept of L3b is stored in the second library 6.

With the above operation, if the graph data representing the parameter groups of n basic cells is made common, the data amount of the parameter group stored in the second library 6 is 1.
/ N.

Next, the operation of the delay calculation device configured as described above will be described. When a desired logic circuit is designed by the logic design device 2, the delay value calculator 7 reads the wiring data corresponding to the logic circuit from the first library 5,
The cell data of the basic cell is read from the second library 6 and the delay value of each basic cell forming the logic circuit is calculated.

At this time, the delay value calculator 7 uses the second library 6 to set the position of each basic cell, the wiring and load on the output side, the driving capacity on the input side, and parameters according to the wiring.
Calculated from the graph data stored in.

That is, the delay value calculator 7 reads out the graph data of the parameter group corresponding to the basic cell from the second library 6, and if the use condition of the basic cell is different from the read graph data, it is stored. The desired parameter is calculated by line complement from the graph data.

Then, the calculated parameter is applied to a preset linear equation to calculate the delay value of the basic cell. When the delay value calculator 7 calculates the delay value of each basic cell forming the logic circuit, the calculated value is output to the logic simulator 8. The logic simulator 8 simulates the operation of the logic circuit based on the calculated delay value of each basic cell.

As described above, in this delay value calculation device, when the delay value calculator 7 calculates the delay value of the basic cell,
The calculation is performed based on the wiring data stored in the first library 5 and the cell data stored in the second library 6.

In the cell data stored in the second library 6, the parameter groups of a plurality of basic cells are stored as a common graph. Therefore, the parameter group of a large number of basic cells can be compressed and stored in the second library. Therefore, even if the number of parameters forming the cell data is increased, the capacity of the second library 6 is not increased. Can be stored.

When the delay value calculator 7 calculates the delay value of the basic cell, the parameter group graphed as the cell data of the basic cell is read from the second library 6 and the line interpolation is performed from the graph data. Then, the desired parameters are obtained. Then, the obtained parameter is applied to a preset linear equation to calculate the delay value.

Therefore, the graph data stored in the second library 6 is interpolated between lines to obtain optimum parameters,
A precise delay value can be calculated by a simple calculation in which the parameter is applied to a linear equation to calculate the delay value.

As a result, if the parameters stored in the second library 6 are increased, the accuracy of the delay value can be improved. If the parameters stored in the second library 6 are not increased, necessary parameters can be read out from the graphed parameter group and the delay value can be calculated to shorten the calculation time.

[0037]

As described above in detail, the present invention exerts an excellent effect of being able to provide a delay calculation device capable of calculating a delay value with a small error without increasing the calculation amount.

[Brief description of drawings]

FIG. 1 is a block diagram showing a delay value calculation device according to an embodiment.

FIG. 2 is a flowchart showing the operation of the cell design device.

FIG. 3 is an explanatory diagram showing a state in which a parameter group of a basic cell is graphed.

FIG. 4 is an explanatory diagram showing a state in which a parameter group of a basic cell is graphed.

[Explanation of symbols]

 2 logic design device 4 cell design device 5 first library 6 second library 7 delay value calculator

Claims (2)

[Claims] 1. A cell data is calculated in advance for calculating delay values of a large number of basic cells and stored in a library, and a delay value calculator calculates a delay value of each basic cell based on the cell data. A delay calculation method, in which the cell data of each of the basic cells is converted into graph data, and when the gradient of the graph data of the cell data is approximate,
A delay calculation method for logic simulation, wherein approximate graph data is stored in a library as common data, and cell data of a basic cell whose delay value is to be calculated is read from the graph data stored in the library. 2. A cell stores pre-calculated cell data for calculating delay values of a large number of basic cells in a library, and a delay value calculator calculates a delay value of each basic cell based on the cell data. A delay calculation device, in which cell data of each of the basic cells is converted into graph data, and when the slope of the graph data of the cell data is approximate,
The delay value calculator includes a cell design device that stores approximate graph data in a library as common data, and a read device that reads cell data of a basic cell whose delay value is to be calculated from the graph data in the library. A delay calculation device for logic simulation, characterized by being provided.