JPH07105602B2 - Multilayer wiring board - Google Patents
Multilayer wiring boardInfo
- Publication number
- JPH07105602B2 JPH07105602B2 JP61263673A JP26367386A JPH07105602B2 JP H07105602 B2 JPH07105602 B2 JP H07105602B2 JP 61263673 A JP61263673 A JP 61263673A JP 26367386 A JP26367386 A JP 26367386A JP H07105602 B2 JPH07105602 B2 JP H07105602B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- ceramic
- adhesive resin
- metal terminals
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000919 ceramic Substances 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000004840 adhesive resin Substances 0.000 claims description 12
- 229920006223 adhesive resin Polymers 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 5
- 239000009719 polyimide resin Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 238000005245 sintering Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000007363 ring formation reaction Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はコンピュータ、電子交換装置などに用いられる
IC、LSI等に実装される大型の多層配線基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used in computers, electronic exchanges, and the like.
The present invention relates to a large-sized multilayer wiring board mounted on an IC, LSI or the like.
この種の大型の多層配線基板として、従来では主として
次の２種類のものが多用されている。As the large-sized multilayer wiring board of this type, the following two types are mainly used in the related art.
１つはフェノール、エポキシなどの樹脂で構成された積
層基板の表面に銅箔をはり付け、これをエッチング処理
によってパターン形成した樹脂配線基板としてのもので
ある。One is a resin wiring board in which a copper foil is glued on the surface of a laminated board made of a resin such as phenol or epoxy, and this is patterned by etching.
他はアルミナ粉末等のセラミック材料を液状のバインダ
を用いて粘り合わせたシート状のセラミック基板、いわ
ゆるグリーンシート上にパターンを印刷し、所要枚数を
積み重ねて圧着し、これを焼結させるセラミック配線基
板としてのものである。The other is a ceramic wiring board in which a pattern is printed on a sheet-shaped ceramic substrate made by sticking a ceramic material such as alumina powder using a liquid binder, a so-called green sheet, a required number of layers are stacked, pressure-bonded, and sintered. As is.
従来では、いずれの場合でも、予め基板を製品寸法に合
致させた大型のものとして構成し、これにパターンの形
成等を行っている。Conventionally, in any case, the substrate is preliminarily configured as a large size that matches the product size, and a pattern or the like is formed on this.
樹脂配線基板によるものでは、大型の基板にスルーホー
ルの形成、エッチング処理等を直接行っているため、比
較的誤差が大きくなり、スルーホール形式精度またはエ
ッチング精度が低下し易く、高密度化するうえで困難で
ある。In the case of using a resin wiring board, since a through hole is formed and an etching process is directly performed on a large board, the error is relatively large, and the through hole format accuracy or etching accuracy is liable to decrease, and in addition to high density. Is difficult.
また、セラミック配線基板によるものでは、パターンの
印刷性が悪くなり、また焼結時の焼縮みが大きくなるな
ど、やはり大型基板を直接用いることにより高密度化が
困難である。Further, in the case of using a ceramic wiring board, the printability of the pattern is deteriorated, and the shrinkage during sintering becomes large. Therefore, it is difficult to increase the density by directly using a large board.
なお、これらの樹脂配線基板やセラミック配線基板を用
いて高密度化を図る手段として超多層化構造とすること
が考えられる。しかし、この手段は技術的には可能で
も、生産リードタイムが長期化するとともに、所望の精
度のものが得にくく歩留りが低下するなどの欠点があ
り、実用上では問題が多い。An ultra-multilayered structure can be considered as a means for increasing the density by using these resin wiring boards and ceramic wiring boards. However, this means is technically feasible, but it has drawbacks such as long production lead time, difficulty in obtaining desired accuracy, and reduction in yield.
そこで本発明の目的は、高密度化が容易かつ確実に行
え、生産リードタイムの短縮および歩留りの向上が図れ
る大型の多層積層板を提供することにある。Therefore, an object of the present invention is to provide a large-sized multi-layer laminated board which can easily and surely increase the density, shorten the production lead time, and improve the yield.
本発明では、回路配線を積層基板内に多層に設けた大型
の多層配線基板において、セラミック基板に回路配線を
施してなる小型に分割された複数のセラミック配線基板
を備え、その各セラミック配線基板の側面には接着用樹
脂層が形成されており、かつ基板表面にそれぞれ延在す
る金属端子が前記接着用樹脂層の表面と面一な状態でこ
の側面に間隔を置いて配置されており、それぞれ対向す
る金属端子が圧接した状態で各セラミック配線基板のこ
れら金属端子が存在しない部位の接着用樹脂層同士を接
合することにより大型に形成するようにしている。According to the present invention, in a large-sized multilayer wiring board in which circuit wirings are provided in multiple layers within a laminated board, a plurality of ceramic wiring boards divided into small parts each of which is formed by applying circuit wiring to a ceramic substrate is provided, and each of the ceramic wiring boards is provided. An adhesive resin layer is formed on the side surface, and metal terminals respectively extending on the surface of the substrate are arranged at a distance from the side surface in a state of being flush with the surface of the adhesive resin layer. In a state in which the metal terminals facing each other are pressed against each other, the resin layers for adhesion are joined together at the portions of the respective ceramic wiring boards where the metal terminals do not exist, thereby forming a large size.
すなわち、本発明では各セラミック配線基板の側面の金
属端子同士を対向させて圧接し、このときこの側面の金
属端子が存在しない部位の接着用樹脂層同士を接合する
ようにしている。この結果、パターン印刷性がよく、焼
結時の焼縮みが小さく、しかも生産リードタイムが短
く，歩留りもよい高密度の多層配線基板を制作すること
ができ、また、金属端子同士が圧接するので、各セラミ
ック配線基板間の電気的接続も同時に行われることにな
る。That is, in the present invention, the metal terminals on the side surfaces of the respective ceramic wiring boards are made to face each other and are pressed into contact with each other, and at this time, the adhesive resin layers on the side surface where the metal terminals are not present are bonded. As a result, it is possible to produce a high-density multi-layer wiring board with good pattern printability, small shrinkage during sintering, short production lead time, and high yield, and because the metal terminals are pressed against each other. Electrical connection between the ceramic wiring boards is also made at the same time.
以下、本発明の一実施例を図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は最終成形品としての大型の積層配線基板１を示
す。この積層配線基板１はセラミック基板からなるもの
で、その内部に所要の回路配線が多層に設けられてい
る。すなわち、この積層配線基板１は、アルミナセラミ
ック製の基板表面にタングステン（Ｗ）またはモリブデ
ン（Mo）からなる電源パターンと、金（Au）または銀パ
ラジウム（Ag/Pd）からなる信号パターンとを形成し、
その表面にポリイミド樹脂を層間絶縁として、多数の金
（Au）または銅（Cu）の微細パターンを積層形成したも
のである。FIG. 1 shows a large laminated wiring board 1 as a final molded product. The laminated wiring board 1 is made of a ceramic substrate, and required circuit wirings are provided in multiple layers inside the laminated wiring board 1. That is, in this laminated wiring board 1, a power source pattern made of tungsten (W) or molybdenum (Mo) and a signal pattern made of gold (Au) or silver palladium (Ag / Pd) are formed on the surface of an alumina ceramic substrate. Then
A large number of gold (Au) or copper (Cu) fine patterns are laminated and formed on the surface by using polyimide resin as interlayer insulation.
第２図は、第１図に示す大型の積層配線基板１の構成素
材として予め小型に分割形成されたセラミック配線基板
２を示している。この実施例では四分割形とされてお
り、その分割された各セラミック配線基板２に予め前記
の多層回路配線が設けられ、また隣接する各１対の側面
が接合端縁部2aとされている。FIG. 2 shows a ceramic wiring board 2 which is previously divided into small pieces as a constituent material of the large-sized laminated wiring board 1 shown in FIG. In this embodiment, it is of a four-divided type, each of the divided ceramic wiring boards 2 is provided with the above-mentioned multilayer circuit wiring in advance, and each pair of adjacent side surfaces is a joint edge portion 2a. .
第３図は、第２図に示すセラミック基板２の接合端縁部
2aを拡大して示している。各セラミック基板２の接合端
縁部2aには、金（Au）からなる金属端子３と、ポリイミ
ド樹脂からなる接着用樹脂層４とが形成されている。金
属端子３は各パターン部から接合端縁部2aに突出すると
ともに、接合端縁部2aの端面に沿って折曲し延在してい
る。また、接着用樹脂層４は接合端縁部2aの端面全体に
沿い、かつ金属端子３と面一な状態で形成されている。FIG. 3 is a joining edge portion of the ceramic substrate 2 shown in FIG.
2a is shown enlarged. A metal terminal 3 made of gold (Au) and an adhesive resin layer 4 made of a polyimide resin are formed on the joint edge 2a of each ceramic substrate 2. The metal terminal 3 projects from each pattern portion to the joint end edge portion 2a, and is bent and extends along the end face of the joint end edge portion 2a. The adhesive resin layer 4 is formed along the entire end surface of the joining edge portion 2a and flush with the metal terminal 3.
なお、接着用樹脂層４を構成するポリイミド樹脂の厚さ
は50μｍ以下とされており、接合前においては閉環反応
の中間段階（Ｂステージ）となっている。The thickness of the polyimide resin constituting the adhesive resin layer 4 is 50 μm or less, and it is in the intermediate stage (B stage) of the ring closure reaction before joining.
また、金属端子３の線幅は、フォトリソグラフィおよび
エッチングにより、10μｍ程度とされている。The line width of the metal terminal 3 is set to about 10 μm by photolithography and etching.
第４図は第３図に示す分割形のセラミック配線基板２の
接合端縁部2aを接合した状態を示している。この接合を
行う場合には、各セラミック配線基板２を所定の治工具
によって位置決めし、接合面に約2kg/mm2の加圧力を作
用させる。そして約400℃の温度で約１時間、窒素
（N2）雰囲気中に保持する。これにより、ポリイミド樹
脂が完全に閉環反応し、接着用樹脂層４が相互に接着さ
れる。なお、金属端子３同士も熱圧着される。FIG. 4 shows a state in which the joint edges 2a of the split type ceramic wiring substrate 2 shown in FIG. 3 are joined. When performing this bonding, each ceramic wiring board 2 is positioned by a predetermined jig and tool, and a pressing force of about 2 kg / mm 2 is applied to the bonding surface. Then, it is kept in a nitrogen (N 2 ) atmosphere at a temperature of about 400 ° C. for about 1 hour. As a result, the polyimide resins undergo a complete ring-closing reaction, and the adhesive resin layers 4 are adhered to each other. The metal terminals 3 are also thermocompression bonded.
このようにして、第２図に示す全てのセラミック配線基
板２が接合されて第１図に示す大型の多層配線基板１が
形成されるものである。In this way, all the ceramic wiring boards 2 shown in FIG. 2 are joined to form the large-sized multilayer wiring board 1 shown in FIG.
このようにして形成される多層配線基板１によれば、分
割体としての小型のセラミック配線基板２の段階でパタ
ーン形成、焼結等が行われるのでパターン形成精度がよ
く、また焼縮みも小さくて済む。そして接合も能率よ
く、確実に行え、高密度の大型の多層配線基板１が短い
生産リードタイムで歩留りよく得られるようになる。According to the multilayer wiring board 1 formed in this way, pattern formation, sintering, etc. are performed at the stage of the small ceramic wiring board 2 as a divided body, so that the pattern formation accuracy is good and the shrinkage is small. I'm done. Then, the bonding can be performed efficiently and reliably, and the high-density large-sized multilayer wiring board 1 can be obtained with a short production lead time and a high yield.
なお、前記実施例における各部の材料、寸法、接合条件
等は必要に応じて変更できることはもちろんである。Of course, the materials, dimensions, joining conditions, etc. of the respective parts in the above-mentioned embodiment can be changed as necessary.
以上のように、本発明に係わる多層配線基板によると、
複数に分割された小型のセラミック配線基板が、その側
面に形成された金属端子と接着用樹脂層とを介して互い
に接合されて大型に形成されるものであるから、小型基
板段階で回路配線を施すことができ、歩留りが良く、か
つ生産リードタイムの短い高密度、大型の多層配線基板
が実現できる。また、各セラミック配線基板の側面の接
合に際して金属端子同士が圧接するので、各セラミック
配線基板間の電気的接続も同時に行われることになると
いう効果もある。As described above, according to the multilayer wiring board of the present invention,
Since a small ceramic wiring board divided into a plurality of pieces is joined to each other through a metal terminal formed on the side surface and an adhesive resin layer to form a large size, circuit wiring is performed at the small board stage. It is possible to realize a high-density, large-sized multilayer wiring board which can be applied, has a high yield, and has a short production lead time. Further, since the metal terminals are pressed against each other when the side surfaces of the respective ceramic wiring boards are joined together, there is an effect that electrical connection between the respective ceramic wiring boards can be performed simultaneously.
図面は本発明の一実施例を示すもので、第１図は最終成
形品としての大型の多層配線基板を示す斜視図、第２図
は分割されたセラミック配線基板を示す斜視図、第３図
は第２図の一部を拡大して示す図、第４図は基板の接合
状態を示す図である。 １……多層配線基板、２……セラミック配線基板、３…
…金属端子、４……接着用樹脂層。The drawings show one embodiment of the present invention. FIG. 1 is a perspective view showing a large-sized multilayer wiring board as a final molded product, FIG. 2 is a perspective view showing a divided ceramic wiring board, and FIG. 2 is an enlarged view of a part of FIG. 2, and FIG. 4 is a view showing a bonding state of substrates. 1 ... Multilayer wiring board, 2 ... Ceramic wiring board, 3 ...
… Metal terminals, 4 …… Adhesive resin layer.
Claims (2)
の多層配線基板において、 セラミック基板に回路配線を施してなる小型に分割され
た複数のセラミック配線基板を備え、その各セラミック
配線基板の側面には接着用樹脂層が形成されており、か
つ基板表面にそれぞれ延在する金属端子が前記接着用樹
脂層の表面と面一な状態でこの側面に間隔を置いて配置
されており、それぞれ対向する金属端子が圧接した状態
で各セラミック配線基板のこれら金属端子が存在しない
部位の接着用樹脂層同士を接合することにより大型に形
成してなることを特徴とする多層配線基板。1. A large-sized multi-layer wiring board in which circuit wiring is provided in multiple layers in a laminated board, comprising a plurality of ceramic wiring boards divided into small parts each of which is formed by applying circuit wiring to a ceramic substrate, and each ceramic wiring board. Adhesive resin layer is formed on the side surface of, and the metal terminals respectively extending to the substrate surface are arranged at a distance to this side surface in a state of being flush with the surface of the adhesive resin layer, A multi-layer wiring board, which is formed in a large size by bonding resin layers for adhesion of portions of each ceramic wiring board where these metal terminals do not exist in a state where metal terminals facing each other are pressed against each other.
はポリイミド樹脂であることを特徴とする特許請求の範
囲第１項記載の多層配線基板。2. The multilayer wiring board according to claim 1, wherein the metal terminal is made of gold (Au) and the adhesive resin is a polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61263673A JPH07105602B2 (en) | 1986-11-07 | 1986-11-07 | Multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61263673A JPH07105602B2 (en) | 1986-11-07 | 1986-11-07 | Multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63119293A JPS63119293A (en) | 1988-05-23 |
| JPH07105602B2 true JPH07105602B2 (en) | 1995-11-13 |
Family
ID=17392753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61263673A Expired - Lifetime JPH07105602B2 (en) | 1986-11-07 | 1986-11-07 | Multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105602B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108271314A (en) * | 2018-01-18 | 2018-07-10 | 郑州云海信息技术有限公司 | A kind of production method and backboard of oversize backboard |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58196867U (en) * | 1982-06-24 | 1983-12-27 | オンキヨー株式会社 | printed wiring board |
| US4520561A (en) * | 1983-12-16 | 1985-06-04 | Rca Corporation | Method of fabricating an electronic circuit including an aperture through the substrate thereof |
-
1986
- 1986-11-07 JP JP61263673A patent/JPH07105602B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63119293A (en) | 1988-05-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |