JPH07106925A - Latch circuit - Google Patents

Abstract

PURPOSE:To improve the alpha-ray resistance of a latch circuit which feeds back data via an emitter-following circuit. CONSTITUTION:A latch circuit 10 is provided with a delay circuit DL consisting of a 1st inverter INV1 which inverts the level of a negative phase clock CL2 transmitted through a 2nd output terminal of a clock driver D and a 2nd inverter INV2 which inverts the level of the output signal of the inverter INV1, and an AND circuit AND which takes an AND between the output signal of the circuit DL and a positive phase clock CL1 transmitted through a 1st output terminal of the driver D. Furthermore unlike the conventional latch circuits of this kind, the output signal (emitter-follower current control signal S) of the circuit AND is supplied to the bases of the 1st and 2nd emitter-follower current control transistors Q21 and Q22 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit, and more particularly to a latch circuit that feeds back data via an emitter follower circuit.

[0002]

2. Description of the Related Art A conventional latch circuit 100 of this type is shown in FIG.
As shown in, the first to third power supply lines L _{101 to} L ₁₀₃
, First to sixth transistors Q _{101 to} Q _106, and first and second emitter follower transistors Q ₁₁₁ and Q _112.
, First and second emitter follower current control transistors Q ₁₂₁ and Q ₁₂₂ , first and second output amplitude resistors R ₁₁₁ and R _112, and first and second emitter follower resistors R ₁₂₁ and It includes an R ₁₂₂ , an α-ray countermeasure capacitor C, a current source 110, and a clock driver D.

Here, the clock driver D has a first output.
Has a power terminal and a second output terminal, and the clock CL is external
When input from, a positive-phase clock in phase with the clock CL
CL ₁ (Emitter follower control signal) to the first output terminal
It is output from the
Click CL₂ Is output from the second output terminal.

The first transistor Q ₁₀₁ is a transistor for writing data, and its collector is connected to the first power supply line L ₁₀₁ via the first output amplitude resistor R ₁₁₁ . The input data A is externally input to the base of the first transistor Q ₁₀₁ . The second transistor Q ₁₀₂ is a data writing transistor, and its collector is connected to the first power supply line L ₁₀₁ via the second output amplitude resistor R ₁₁₂ . Further, the inverted input data BA, which is the inverted data (data of the opposite phase) of the input data A, is externally input to the base of the second transistor Q ₁₀₂ .

The third transistor Q ₁₀₃ is a data holding transistor, and its collector is connected to the collector of the first transistor Q ₁₀₁ . The fourth transistor Q ₁₀₄ is a data holding transistor, and its collector is connected to the collector of the second transistor Q ₁₀₂ .

The fifth transistor Q ₁₀₅ is a transistor for writing data, and has a collector having an emitter of the first transistor Q ₁₀₁ and a second transistor Q _102.
Of the clock driver D, and the base thereof is connected to the first output terminal of the clock driver D. Sixth
Of the transistor Q ₁₀₆ is a transistor for storing data, a collector connected to the emitter of the emitter and the fourth transistor Q ₁₀₄ of the third transistor Q _103, base connected to the second output terminal of the clock driver D And the emitter is connected to the emitter of the fifth transistor Q ₁₀₅ . The emitter of the fifth transistor Q _{105 and} the emitter of the sixth transistor Q ₁₀₆ are connected to the _third power supply line L _{10 3} via the current source 110, respectively.

When the positive-phase clock CL ₁ is input to the base of the fifth transistor ₁₀₅ from the first output terminal of the clock driver D, the latch circuit 100 is put in the data write state. Further, when the negative phase clock CL ₂ is input to the base of the sixth transistor Q ₁₀₆ from the second output terminal of the clock driver D, the latch circuit 100 is brought into the data holding state.

First emitter follower transistor Q
₁₁₁ has a collector connected to the first power supply line L ₁₀₁ , a base connected to the collector of the third transistor Q ₁₀₃ , and an emitter connected to the base of the fourth transistor Q ₁₀₄ . . The collector of the second emitter follower transistor Q ₁₁₂ is connected to the first power supply line L ₁₀₁ , and the base of the second emitter follower transistor Q ₁₁₂ is the fourth transistor Q.
The emitter is connected to the base of the third transistor Q ₁₀₃ while being connected to the collector of ₁₀₄ .
The α-ray countermeasure capacitor C is connected between the emitter of the first emitter follower transistor Q _{111 and} the emitter of the second emitter follower transistor Q ₁₁₂ .

The first emitter follower current controlling transistor Q ₁₂₁ has a collector connected to the emitter of the first emitter follower transistor Q ₁₁₁ and a base connected to the first output terminal of the clock driver D. The emitter is connected to the second power supply line L ₁₀₂ via the first emitter follower resistor R ₁₂₁ . Second
The emitter follower current control transistor Q ₁₂₂ of
The collector is the second emitter follower transistor Q _112.
Of the clock driver D
_It is connected to the first output terminal of ₁₀₁ and its emitter is connected to a second emitter follower resistor R ₁₂₂ .
_Is connected to the power supply line L ₁₀₂ .

With the latch circuit 100 configured as described above,
Is the first output amplitude resistor R₁₁₁And the first transistor
Q₁₀₁ And the fifth transistor Q₁₀₅ And current source 110 and second
Output resistance R₁₁₂ And the second transistor Q₁₀₂ When
However, depending on one level of the clock CL,
First differential transistor which is in a state (data write state)
Function as a pair. In addition, the first output amplitude resistor R
₁₁₁ And the third transistor Q₁₀₃ And the sixth transistor
Q₁₀₆ And current source 110 and second output amplitude resistor R ₁₁₂ And the
4 transistor Q₁₀₄ Is the other level of the clock CL.
Selective operation (data retention status) by bell
Function as a second differential transistor pair.

In the latch circuit 100, as shown in FIG. 5C, the first and second emitters are in the data write state (the positive phase clock CL ₁ shown in FIG. 5B is at a high level). The response speed of the first emitter follower transistor Q ₁₁₁ is increased by increasing the emitter follower current flowing through the follower transistors Q ₁₁₁ and Q _112, and at the same time as the data holding state (the positive phase clock CL ₁ shown in FIG. Is a low level), the first and second emitter follower transistors Q ₁₁₁ ,
By reducing the emitter follower current through Q ₁₁₂ to slow the response speed of the second emitter follower transistor Q _112, is incident on the collector of the collector and the fourth transistor Q ₁₀₄ of the third transistor Q ₁₀₃ alpha
The change in data due to the line is not transmitted.

[0012]

However, in the above-described conventional latch circuit 100, in the data write state, the collector of the data write transistors (the first and second transistors Q ₁₀₁ and Q ₁₀₂ ) receives α-rays. Is incident, the data is easily inverted because the emitter follower current flowing through the first and second emitter follower transistors Q ₁₁₁ and Q ₁₁₂ is increasing. At this time, normally, a transistor for writing data (first
Since the bases of the second transistors Q ₁₀₁ and Q ₁₀₂ ) are fixed to the output level of the preceding stage, the data can be returned to the original state. However, at the timing close to the switching timing of the clock CL, the inversion of the data due to the α-ray incidence is held as it is and the data holding state is obtained
Since the inverted data is retained, there is a problem that the α-ray resistance is poor.

An object of the present invention is to provide a latch circuit which can improve the α ray resistance.

[0014]

The latch circuit of the present invention comprises:
A first power supply line, a second power supply line, a first transistor whose base receives input data, and a second transistor whose base receives inverted data of the input data or a predetermined reference voltage. With
A first differential transistor pair that is selectively activated by one level of a clock; a third transistor whose collector is connected to the collector of the first transistor; and a second transistor whose collect is the second transistor. A second differential transistor pair having a fourth transistor connected to the collector of the second differential transistor and selectively activated by the other level of the clock; and a collector connected to the first power supply line; A first base whose base is connected to the collector of the third transistor and whose emitter is connected to the base of the fourth transistor;
An emitter follower transistor, and a first emitter follower current control transistor whose collector is connected to the emitter of the first emitter follower transistor,
A first emitter follower resistor having one end connected to the emitter of the first emitter follower current control transistor and the other end connected to the second power supply line, and a collector connected to the first power supply line. A second emitter follower transistor having a base connected to the collector of the fourth transistor and an emitter connected to the base of the third transistor; and a collector connected to the emitter of the second emitter follower transistor. A second emitter follower current control transistor connected to the second emitter follower, one end of which is connected to the emitter of the second emitter follower current control transistor and the other end of which is connected to the second power supply line. In a latch circuit including a resistor, delay the inverted signal of the clock A delay circuit which includes an AND circuit for taking a logical product of the output signal of the delay circuit clock, the output signal of the AND circuit, the base of said first emitter follower current control transistor and the second
Is input to the base of the emitter follower current control transistor of.

[0015]

According to the latch circuit of the present invention, in a latch circuit for feeding back data via an emitter follower circuit, a delay circuit for delaying an inverted signal of a clock and an AND circuit for ANDing an output signal of the delay circuit and the clock are used. ,
A signal (emitter follower control signal) having a width narrower than the data writing period of the clock cycle is created, and the created signal is input to the base of the first emitter follower current control transistor and the base of the second emitter follower current control transistor. As a result, the emitter follower currents flowing through the first and second emitter follower current control transistors are increased and the response speed is increased only during the period when this signal is input, whereby the emitter follower circuit based on the written data The output level of the emitter follower circuit can be made difficult to change by fixing the output level and decreasing the response speed of the emitter follower current in the other period of the clock cycle to reduce the response speed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of a latch circuit of the present invention.

The latch circuit 10 of this embodiment has a first inverter INV ₁ which inverts the level of the anti-phase clock CL ₂ output from the second output terminal of the clock driver D.
And a delay circuit DL including a _second inverter INV ₂ that inverts the level of the output signal of the first inverter INV _1, an output signal of the delay circuit DL, and a clock driver D.
AND circuit AND which ANDs with the positive phase clock CL ₁ output from the first output terminal of
An output signal of the AND circuit AND (hereinafter referred to as “emitter follower current control signal S”) is applied to the base of the first emitter follower current control transistor Q _{21 and} the base of the second emitter follower current control transistor Q ₂₂ . In the point of being supplied, the conventional latch circuit shown in FIG.
Different from 100.

In the latch circuit 10, the clock shown in FIG.
The clock driver D with the phase of the lock CL inverted
Opposite-phase clock CL output from the second output terminal₂ Is the
1 inverter INV₁ And the second inverter INV
₂ By passing through a delay circuit DL consisting of
As shown in (D), the clock cycle of the clock CL
It is delayed by less than half of T. Delay circuit D
L output signal and the first output terminal of the clock driver D
Output from the positive phase clock CL shown in FIG. ₁ With
As the logical product is taken by AND circuit AND,
As shown in (E), the positive phase clock CL₁ High level of
The pulse width is narrower than the period (data writing period)
The emitter follower current control signal S is generated. Create
The generated emitter follower current control signal S is
Tafoler current control transistor Q_{twenty one}The base of and
Second emitter follower current control transistor Q_{twenty two}of
Supplied to the base. As a result, as shown in FIG.
The data write state (that is, the positive phase clock CL₁ 
The high level) of the first and second emitter
Lower transistor Q₁₁, Q₁₂Flowing emitter follower
Since the period during which the current increases can be shortened, the data
First and second emitter followers during write
Langista Q₁₁, Q₁₂Short response time
With the first and second emitter follower transitions
Star Q₁₁, Q₁₂Clock response during periods when the response speed of the
It can be lengthened in the icicle T.

FIG. 3 is a circuit diagram showing a second embodiment of the latch circuit of the present invention.

The latch circuit 50 of this embodiment comprises a delay circuit D
L'is different from the latch circuit 10 of the first embodiment shown in FIG. 1 in that L'is composed of a low pass filter including a delay resistor R ₅₁ and a delay capacitor C ₅₁ .

[0022] In the latch circuit 50 of the present embodiment, the time constant of the low-pass filter, an emitter follower current having a pulse width narrower than the positive-phase period of the clock CL ₁ at high level constituting the delay circuit DL ' By setting the control signal S so as to be generated, the same effect can be obtained.

In the embodiment described above, the inverted input data BA, which is the inverted data of the input data A, is externally input to the base of the second transistor Q ₂ .
Even when a predetermined reference voltage is input, the same effect can be obtained.

The following latch circuits have been proposed as having improved α-ray resistance, but each of them is the latch circuit of the present invention having a structure for narrowing the pulse width of the emitter follower current control signal. different. (1) By interposing between the pair of feedback loops and the second logic gate a differential section that operates by receiving only two level relationships of non-inverted logic output and inverted logic, the level of the clock signal is increased. A latch circuit for obtaining a stable latch operation without requiring accuracy (Japanese Patent Laid-Open No. 2-332)
No. 15). (2) Set the node holding the data in the latch circuit to α
By separating from the p substrate which is the source of the line noise current, even if α-ray is incident on the transistor that constitutes the latch circuit, the data is not destroyed and the latch circuit that reduces the soft error of the semiconductor memory (special feature (Kaihei 2-78269). (3) When the emitter potential of the emitter follower that feeds back the output signal is at the high level, the emitter follower current is almost cut off, so that even if spike noise occurs at the data holding node due to the α line, the input side flip-flop A latch circuit that prevents transmission of spike noise to the gate (Japanese Patent Laid-Open No. 63-36609). (4) Between the collector and the base of the data holding differential transistor pair, a resistor provided between the bases of the differential transistor pair and a pair of switch means for selectively terminating one or the other of the resistors. , By providing a feedback circuit including a pair of feedback transistors that form the emitter follower circuit by selectively receiving the collector potential of one or the other of the differential transistor pairs in its base, and forming a emitter follower circuit. The pulsed noise generated in the collector of the holding differential transistor pair is divided according to the ratio of the parasitic capacitance coupled to the base of each feedback transistor to the opposing parasitic capacitance coupled to the base of the differential transistor, In addition to suppressing the decrease in the base potential of the differential transistor due to the noise, the emitter follower circuit By selectively terminating the one or other sharing anti a latch circuit (JP-A to secure a potential difference between the base of the differential transistor pair 1-1066
19 publication).

[0025]

Since the present invention is configured as described above, it has the following effects.

The latch circuit of the present invention is formed by a delay circuit that delays an inverted signal of a clock and an AND circuit that performs a logical product of the output signal of the delay circuit and the clock.
Only during the period when a signal (emitter follower control signal) narrower than the data write period of the clock cycle is input,
By increasing the emitter follower current flowing through the first and second emitter follower current control transistors and increasing the response speed thereof, the output level of the emitter follower circuit according to the written data is determined, and at the other time of the clock cycle. During the period, the output level of the emitter follower circuit can be made difficult to change by reducing the emitter follower current and slowing its response speed, so that α rays are incident on the collectors of the differential transistor pair. Since the period can be shortened even if the emitter follower current increases, the probability that the incidence of α rays will affect the output level of the emitter follower circuit can be reduced, and the α ray resistance is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a latch circuit of the present invention.

2 is a timing chart showing a method of generating an emitter follower control signal in the latch circuit shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of a latch circuit of the present invention.

FIG. 4 is a circuit diagram showing a conventional example of a latch circuit.

5 is a timing chart showing timings of a clock, a positive phase clock (emitter follower control signal) and an emitter follower current in the latch circuit shown in FIG.

[Explanation of symbols]

10, 50 Latch circuit 11 Current source Q _{1 to} Q ₆ transistor Q ₁₁ , Q ₁₂ Emitter follower transistor Q ₂₁ , Q ₂₂ Emitter follower current control transistor R ₁₁ , R ₁₂ Output amplitude resistor R ₂₁ , R ₂₂ Emitter follower resistor R ₅₁ Delay resistor C ₅₁ Delay capacitor C α line countermeasure capacitor D Clock driver L _{1 to} L ₃ Power supply line INV ₁ , INV ₂ Inverter DL Delay circuit AND AND circuit CL clock CL ₁ Positive phase clock CL ₂ Reverse phase clock S Emitter-follower current control signal T clock cycle

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[Procedure amendment]

[Submission date] January 21, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Claims (1)

[Claims] 1. A first power supply line, a second power supply line, and a first transistor to which input data is input to a base,
And a first differential transistor pair that has a second transistor to which inverted data of the input data or a predetermined reference voltage is input, and that is selectively activated by one level of a clock, A third transistor having a collector connected to the collector of the first transistor, and a collector having the second transistor;
A second differential transistor pair having a fourth transistor connected to the collector of the transistor and selectively activated by the other level of the clock; and a collector connected to the first power supply line. A first emitter follower transistor having a base connected to the collector of the third transistor and an emitter connected to the base of the fourth transistor; and a collector connected to the emitter of the first emitter follower transistor. A first emitter follower current control transistor connected to the first emitter follower, one end of which is connected to the emitter of the first emitter follower current control transistor and the other end of which is connected to the second power supply line. A resistor and a collector connected to the first power line, A second emitter follower transistor having an emitter connected to the collector of the fourth transistor and an emitter connected to the base of the third transistor; and a collector connected to the emitter of the second emitter follower transistor. A second emitter follower current control transistor, and a second emitter follower resistor having one end connected to the emitter of the second emitter follower current control transistor and the other end connected to the second power supply line. A latch circuit that delays the inverted signal of the clock, and an AND circuit that ANDs the output signal of the delay circuit and the clock, wherein the output signal of the AND circuit is 1. Emitter-follower current control transistor base and said second emitter Latch circuit, characterized in that input to the base of Oroa current control transistor.