JPH07106943A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To unnecessitate the insertion of an impedance matching resistor and to eliminate the distortion of an output waveform by providing a selecting/ connecting means for selecting the combination of connection between the 1st and 2nd matching means and connecting these means to an external line. CONSTITUTION:The ON resistance value of transfer gates Tr1 and Tr2 are used for the impedance matching resistance in a matching circuit 8. As the ON resistance deffers between both gates Tr1 and Tr2, three types of matching resistance are available by combination of control between external control signals C1 and C2. Therefore the matching is secured between the characteristic impedance ZO of wiring of a printed board connected to a terminal 4 and the output impedance value of the terminal 4. Then the distortion of a waveform is eliminated. Furthermore each of >=3 transfer gates is controlled by the external control signal so that more types of matching resistance value are available. Thus the best one of many types of matching resistance value is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a logic circuit and an output buffer circuit for supplying the output of the logic circuit to an external circuit.

[0002]

2. Description of the Related Art This type of semiconductor integrated circuit device (hereinafter referred to as LS
As I), an ECL circuit based on bipolar technology and a CMOS circuit based on MOS technology are widely used. Usually, a plurality of LSIs are mounted on a printed circuit board in order to realize the required functions.
The individual LSIs are connected to each other. In this configuration, one LSI output terminal (sending side)
There are two well-known wiring connection methods between the input terminals (reception end side) of other LSIs to which the signal is input, that is, the reception end resistance termination method and the reception end open method.

ECL is a typical example of the resistance termination method on the receiving end side.
There is a circuit, and the receiving end is normally terminated with 50Ω. The reason for this is that the characteristic impedance (Z
0) is generally designed with 50Ω,
The output waveform of the high speed operation is directly transmitted to the input terminal of each ECL circuit.

A typical example of the receiving end side opening method is a CMOS circuit. The receiving end is open without being resistance-terminated, and the output impedance (ZC) of the CMOS output is often much higher than the characteristic impedance (Z0) of the printed circuit board wiring. Also, the operating speed of the CMOS circuit is originally ECL. Since it is slower than the circuit and therefore the output waveform is slower than the ECL output waveform and the rising speed is also slow, there is practically no distortion of the waveform and no trouble occurs during use.

However, due to recent advances in semiconductor technology,
The speed of LSI devices made of CMOS circuits has also been increased, and the rising and falling speeds of output waveforms have been significantly improved.
Along with this, the output impedance of the output circuit also tends to decrease, causing a problem that the output waveform is distorted due to the mismatch with the characteristic impedance of the printed circuit board wiring.

Referring to FIG. 3, this figure shows a conventional CM.
Semiconductor integrated circuit device (LSI) including an OS circuit
1 and 2 and a wiring 3 on a printed circuit board that connects these LSIs 1 and 2 to each other. The LSI 1 includes an output terminal (pad) 4 and an output buffer 6, and the LSI 2 includes an input terminal 5 and an input buffer 7.

FIG. 4 showing an example of the waveform of the terminal 4 of the LSI 1.
Referring to, the output impedance Z of the output buffer 6
When C is equal to the characteristic impedance Z0 of the printed circuit board wiring, that is, in the matched state, there is no distortion in the output waveform as shown by the curve B. When the output impedance ZC is smaller than or larger than the characteristic impedance Z0, the output waveform is distorted as shown by curves A and C, respectively.

As a method of solving this problem, it can be considered to lower the characteristic impedance Z0 of the wiring 3.
Methods for reducing the characteristic impedance Z0 include changing the substrate material to one having a high dielectric constant such as alumina, and expanding the wiring width.

Further, there is also a method of inserting a matching resistor between the sending end side, that is, between the terminal 4 and the wiring 3 to achieve impedance matching and eliminate waveform distortion.

[0010]

In the above-mentioned conventional semiconductor integrated circuit device, the output impedance has been reduced in response to the speeding up of the operation accompanying the progress of semiconductor technology. There is a problem that the output waveform is distorted due to the mismatch with the impedance, and a method of reducing the characteristic impedance of the wiring, which is one of the solutions, is that the price rises due to the change of the printed circuit board material, There is a drawback in that the packaging density decreases due to the expansion of the wiring width.

Further, in the method of inserting a resistor for impedance matching between the output terminal and the printed circuit board wiring, the mounting density is lowered by the addition of the resistance element and the reliability of the entire device is lowered by the increase in the number of connected parts. There are drawbacks.

[0012]

A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having an output buffer circuit for supplying an output signal to an external line having a predetermined characteristic impedance, wherein the output buffer circuit outputs the output signal. First and second matching means for respectively matching the output impedance of the signal with the first and second output impedances in the vicinity of the characteristic impedance; and the first and second matching means.
Selective connection means for selecting a combination of connection of the matching means and connecting to the external line.

[0013]

The present invention will be described below with reference to the drawings.

Referring to FIG. 1 which is a circuit diagram showing a first embodiment of a semiconductor integrated circuit device (LSI) of the present invention, an LSI 1A of the present embodiment shown in this drawing has an output buffer 6 similar to the conventional one. In addition to the terminals 4, a matching circuit 8 inserted between the output buffer 6 and the terminals 4 for matching with the characteristic impedance Z0 of the wiring 3 of the printed circuit board is provided.

The matching circuit 8 is supplied with the output signal of the output buffer 6 and is controlled to be turned on / off in response to the external control signals C1 and C2, respectively.
And terminals T1 and T2 for receiving the respective supply of C2.

The operation will be described. Terminals T1 and T2
When a logic "0" is supplied as external control signals C1 and C2 to each of the transfer gates Tr1 and T
r2 is turned on. The on-on resistance values of the transfer gates Tr1 and Tr2 are used as matching resistors for impedance matching. Transfer gate Tr
1 and Tr2 have different on-resistance values, the external control signal C
Three types of matching resistors can be obtained by combining the control of 1 and C2. As a result, the characteristic impedance Z0 of the wiring of the printed circuit board connected to the terminal 4 and the output impedance value of the terminal 4 can be matched, and the distortion of the waveform can be eliminated.

In this embodiment, two transfer gates are used, but three or more transfer gates are used and each transfer gate is controlled by an external control signal, so that more kinds of transfer gates can be used. It is also possible to realize a matching resistance value. In that case, the optimum value can be selected from many matching resistance values. If the external control signal is encoded and a decoder circuit or the like is inserted between each transfer gate and the external control terminal to decode the code, the number of external control terminals can be reduced.

Referring to FIG. 2, which is a circuit diagram showing a second embodiment of the semiconductor integrated circuit device (LSI) of the present invention, the LSI 1A of the first embodiment of the LSI 1B of the present embodiment shown in the drawing is shown. Is different from the matching circuit 8 in that instead of the matching circuit 8, the matching resistance value corresponding to the characteristic impedance Z0 of the wiring of the printed circuit board which is preset at the start of the design of the functional circuit including the LSI 1B and the printed circuit board to be mounted is turned on. That is, a matching circuit 9 in which a transfer gate having a resistance is connected to the terminal 4 in advance is provided.

The matching circuit 9 includes transfer gates Tr1 and Tr2 having different on-state resistances as in the first embodiment.
And a wiring element 91 prepared for connecting the transfer gate selected at the time of designing so as to be inserted between the output buffer 6 and the terminal 4.

In this embodiment, the LSI 1B is a gate array, and the contents of the matching circuit 9 are registered in advance as one of the standard functional circuit blocks of the gate array of the LSI 1B. The functional circuit designer selects and determines the matching resistance value corresponding to the value of the characteristic impedance Z0 before starting the design of the functional circuit including the printed circuit board to be mounted. The designer selects a combination of the transfer gates Tr1 and Tr2 so as to have a value closest to the matching resistance value, and instructs the manufacturing specification sheet to carry out the wiring of the combination by the wiring element 91.

This embodiment is an application-specific LSI (AS) in which standard functional circuit blocks such as a gate array are prepared in advance.
This is effective when the characteristic impedance Z0 of the printed circuit board to be mounted and its wiring is determined at the start of designing this LSI, as in the case of application to IC).

[0022]

As described above, in the semiconductor integrated circuit device of the present invention, the output buffer circuit matches the output impedance to the vicinity of the characteristic impedance of the external line, and the first and second matching means. 2) a selection connection means for selecting a combination of connection of the matching means, and by the optimum matching between the output impedance and the characteristic impedance of the printed circuit board wiring, the characteristic impedance of the wiring, which causes a cost increase, and the reliability are reduced. The effect of eliminating the distortion of the output waveform by eliminating the need for inserting a resistor for impedance matching, which is a factor of deterioration, is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 3 is a block diagram showing a connection between a conventional semiconductor integrated circuit device and a wiring of a printed circuit board.

FIG. 4 is a waveform diagram showing distortion of a waveform of an output signal of the semiconductor integrated circuit device.

[Description of Reference Signs] 1, 1A, 1B, 2 Semiconductor integrated circuit device 3 Wiring 4,5, T1, T2 terminal 6 Output buffer 7 Input buffer 8, 9 Matching circuit 91 Wiring element Tr1, Tr2 Transfer gate

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having an output buffer circuit for supplying an output signal to an external line having a predetermined characteristic impedance, wherein the output buffer circuit outputs an output impedance of the output signal in the vicinity of the characteristic impedance. First and second matching respective second output impedances
2. The semiconductor integrated circuit device according to claim 1, further comprising: a matching unit and a selective connecting unit that selects a combination of connections of the first and second matching units to connect to the external line. 2. The semiconductor integrated circuit device according to claim 1, wherein the first and second matching means respectively include first and second transfer gates having different conduction resistance values. 3. The combination according to claim 1, wherein the selective connection means selects the combination of the connections by making either or both of the first and second transfer gates conductive by a control signal. The semiconductor integrated circuit device described. 4. The output buffer circuit comprises a functional circuit block including the first and second transfer gates prepared in advance, and one of the first and second transfer gates is set at a predetermined design time. 3. The semiconductor integrated circuit device according to claim 1, wherein the connection of the functional blocks is completed by selecting a combination of connections that make both conductive.