JPH07106954A - Pulse generating device - Google Patents

Abstract

PURPOSE:To reduce the operating frequency of a presettable counter and to produce a multiple pulse that includes a fraction of cycle of a clock pulse. CONSTITUTION:A presettable counter 1 counts the clock pulses received from a data input terminal 14, and this count output is detected by a detecting circuit 2. An integrating circuit 3 outputs the integrated value and the carry of data. A programmable delay circuit 4 delays the clock pulse by a time equivalent to the integrated value and produces a pulse having the multiple frequency including a fraction against the clock pulse. A shift circuit 5 is connected to the counter 1 and repeats the shift operations based on the clock pulse for output of clock pulses. The counter 1 counts these clock pulses for reduction of frequency of the counter clock pulse. Then the circuit 5 receives a carry signal from the circuit 3 and discontinues its shift operation for a prescribed time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator having a resolution higher than the clock pulse period.

[0002]

2. Description of the Related Art Next, a configuration of a conventional pulse generator is shown in FIG. This device has a presettable counter 1,
It is composed of a detection circuit 2, an integration circuit 3, and a programmable delay circuit 4. Next, the operation of FIG. 6 will be described with reference to the time chart of FIG. As shown in FIG. 7, the cycle of the output pulse can be set with a resolution finer than the clock pulse cycle. Such a technique is disclosed in Japanese Patent Publication Sho 63
It is also disclosed in Japanese Patent No. 9686.

[0003]

In the pulse generator having the configuration shown in FIG. 6, the basic clock pulse cycle may be shortened in order to improve the timing accuracy of the output pulse cycle, but the minimum clock pulse cycle is required. Has a problem of being limited to the frequency at the operating limit of the presettable counter.

An object of the present invention is to provide a pulse generator which sets the cycle of an output pulse with a resolution finer than the clock pulse cycle without being restricted by the frequency of the operation limit of the presettable counter.

[0005]

In order to achieve this object, the present invention provides a shift circuit 5 for setting data by a data input terminal 12 and performing a shift operation by a clock pulse from the input terminal 11, and a data input terminal. The data is set by 14, and the presettable counter 1 that counts down by the output of the shift circuit 5 and the output of the shift circuit 5 and the output of the presettable counter 1 are input, and a pulse is output when each output reaches a specific value, A shift circuit 5 and a detection circuit 2 for inputting to the presettable counter 1,
Data is input to the data input terminal 15, the data is integrated in synchronization with the output of the detection circuit 2, the integrated value is output, and a carry signal based on the integration result is output to the shift circuit 5 to shift the shift circuit 5. Integration circuit 3 that suspends operation
And a programmable delay circuit 4 for inputting the output of the detection circuit 2 and delaying the output in accordance with the integrated output 3A of the integrating circuit 3, and taking out a fractional multiple output from the clock pulse.

[0006]

In the pulse generator of the present invention, the presettable counter counts the clock pulses from the first data input terminal, and when the detection circuit detects that the output has reached the predetermined value, the integrating circuit outputs the data. Output the integrated value and carry. The programmable delay circuit delays the time corresponding to this integrated value and generates a pulse having a frequency with a fractional multiple with respect to the clock pulse. The shift circuit is
The shift operation is repeated based on the clock pulse and output to the presettable counter. When the presettable counter counts this, the frequency of the clock pulse input to the presettable counter is lowered. The shift circuit receives the carry signal from the integrating circuit and rests the shift operation for a predetermined time.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, FIG. 1 shows the configuration of an embodiment of the present invention. Reference numeral 5 in FIG. 1 denotes a shift circuit, and the other components are the same as those in FIG. The presettable counter 1 counts the output signal of the shift circuit 5.

The shift circuit 5 detects the detection signal 2 of the detection circuit 2.
Upon receiving A, the setting data from the data input terminal 12 is set, and the shift operation is performed by the clock pulse from the input terminal 11. When the carry signal 3B from the integrating circuit 3 is received, the shift operation is stopped by one clock when a carry occurs.

The presettable counter 1 includes a detection circuit 2
The setting data from the data input terminal 14 is set in response to the detection signal 2A, and the clock is down-counted in response to the shift output 5A from the shift circuit 5. Input terminal 13
Is the data set timing of the presettable counter 1 and is the same as the signal at the input terminal 11.

When the detection circuit 2 receives the output 5B of the shift circuit 5 and the output 1A of the presettable counter 1 and detects that each output has reached a specific value, it outputs a detection signal 2A.

The integrating circuit 3 has a detection signal 2A from the detection circuit 2.
In synchronization with the above, the data input to the data input terminal 15 are integrated, and the integrated value is output as a signal 3A and the carry is output as a signal 3B.

The programmable delay circuit 4 includes a detection circuit 2
Detection signal 2A from the output terminal 16 is delayed by a time corresponding to the integrated output 3A of the integrating circuit 3.
Is output. In FIG. 1, the data input terminals 12 and 14
・ The signal from 15 has multiple input terminals. The output signals 1A and 5B can take any number of signals depending on how the circuit is assembled.

Next, a configuration example of the shift circuit 5 is shown in FIG. In FIG. 2, the detection signal 2A from the detection circuit 2 is used as a load signal LD for loading the data received at the data input terminal 12 to the shift register 6, and gives the shift register 6 an initial value. This initial value is normally input from the input terminal 12 in the form of decoding a binary code. Here, an example in which the binary code is 2 bits is shown. For example, the binary code “11” (3 in decimal) is input to the shift register 6 as D3, D2, D1, D0 = 1,0,0,0.

In the circuit of this embodiment, the data inputs of the shift register 6 are arranged in the order of D2, D1, D0, D3, and this order directly corresponds to the order of the shift register outputs Q2, Q1, Q0, Q3. ing. Therefore, the time when the shift output 5A of the shift circuit 5 rises to "1" can be the timing when the next presettable counter 1 down-counts. Further, the shift output 5A is fed back to the serial input SI of the shift register 6 and repeatedly shifts "1" from Q2 to Q1, Q0, Q3 by the shift clock 5C.

The shift clock 5C is used in the shift register 6
Is a shift clock. That is, the shift clock 5C latches the carry output 3B of the integrating circuit 3 with the clock signal CK of the input terminal 11 in the flip-flop 7, and ORs the output at this time and the clock of the input terminal 11 to the OR gate 8. Is output. Therefore, the shift clock 5C is the same signal as the clock CK of the input terminal 11 when the carry output 3B is "0", while the clock CK of the input terminal 11 is ORed when the carry output 3B is "1". The gate 8 remains "1" for one cycle of the clock. As a result, when the carry output 3B is "1", the shift operation of the shift register 6 can be stopped once.

In the embodiment of the present invention, Q1 is output to the detection circuit 2 as the output of the shift circuit 5. This is the detection circuit 2, and the shift circuit 5 has the shift state "0" (Q0 =
The detection signal 2A can be output at a timing one clock before (indicating the state of "1").

Next, the configuration of an embodiment of the presettable counter 1 is shown in FIG. In FIG. 3, the signal 1B of the flip-flop 10 is the load clock LCK for loading the data of the data input terminal 14 into the down counter 9. The data input terminal 14 normally inputs data in binary code. The embodiment of the present invention handles 4-bit binary code data. Road clock 1B
Is the detection signal 2A of the detection circuit 2 latched by the clock signal of the input terminal 13. That is, the input terminal 1
3 by making the clock signal of 3 the same as the clock signal of the input terminal 11, the shift output 5A of the shift circuit 5
And the load clock 1B are synchronized with each other.

The data loaded by the load clock 1B is down-counted by inputting the shift output 5A. Output Q showing the state of the down counter 9
0, Q1, Q2, Q3 are input to the detection circuit 2 as outputs 1A of the presettable counter 1. Detection circuit 2
Outputs the detection signal 2A when the output 1A is "0" and the output 5B of the shift circuit 5 is "1".

Next, the operation example of FIG. 1 is shown in the time chart of FIG. In FIG. 4, the clock signal is the input terminal 1
1 and the signal input to the input terminal 13. In the embodiment, the clock cycle is 10 ns. The data input value is
A value obtained by normalizing the cycle of the pulse to be output to the output terminal 16 by the clock signal cycle (10 ns) is shown. This data input value is divided into data corresponding to the data input terminals 12, 14 and 15 and input. In this example, when the data input value is expressed in binary, a value obtained by decoding the 1s digit and the 10s digit is input to the input terminal 12, the 100th digit or more is input to the input terminal 14 as binary data, and the digit below the decimal point is input. The value is input to the data input terminal 15. FIG. 4 shows the case where the data input values “6” and “10” (decimal notation) are sequentially input, and the data input to each input terminal is shown below.

Data input value (6) (10) Data input terminal 14 1000 (4) 0100 (8) Data input terminal 12 1000 (2) 1000 (2) Data input terminal 15 0 (0) 0 (0) In parentheses The numbers in FIG. 3 are notation of weighted data and expressed in decimal, and the notation of 1000 or the like is the signal of each data input terminal in FIGS. 2 and 3 expressed in logical value in order from the left side of the drawing. .

The state of the presettable counter 1 of FIG.
The state of the shift circuit 5 and the state of the integrating circuit 3 are the decimal states of the counting state of each circuit.

In FIG. 4, when the state of the presettable counter 1 is "0" and the state of the shift circuit 5 is "1", the detection circuit 2 sends "1" to the detection signal 2A. Detection signal 2
A is delayed by the programmable delay circuit 4 by a delay time 0 ns corresponding to the integrated output 3A of the integrating circuit 3 and is output as the first pulse through the output terminal 16. The detection signal 2A is input to the shift circuit 5, the presettable counter 1, and the integrating circuit 3, respectively, and the shift circuit 5 and the presettable counter 1 perform the loading operation of the data input value, and the integrating circuit 3 performs the integrating operation. Be seen.
At this time, in the presettable counter 1, data is loaded by the load clock 1B.

As a result, the state of the presettable counter 1 is "1", the state of the shift circuit 5 is "2", and the integrating circuit 3
Is 0. Next, the shift circuit 5 performs a shift operation, and the states of the shift circuit 5 are “2”, “1”,
It changes from "0" to "3". When the state of the shift circuit 5 becomes "3", the shift output 5A becomes "1".

The presettable counter 1 has a shift output 5
The down-count operation is performed by A, and the state of the presettable counter 1 changes from "1" to "0". Next, the shift circuit 5 subsequently performs the shift operation, and the state of the shift circuit 5 changes to "2" and "1". At this time, the state of the presettable counter 1 is "0" again, the state of the shift circuit 5 is "1", and the detection circuit 2 outputs the detection signal 2A.

The detection signal 2A is delayed by the programmable delay circuit 4 in the same manner as above, and is output as the second pulse through the output terminal 16. Therefore, the interval between the first pulse and the second pulse is 60 ns, which is a value according to the data input value. Similarly, the data input value “10” (decimal notation) is added, and then 100n
Generate pulses at intervals of s. In this way, the presettable counter 1 needs to count only when the shift output 5A of the shift circuit 5 is generated, and the count frequency can be lowered.

Next, another operation example of the pulse generator according to the embodiment of the present invention will be described with reference to the time chart of FIG. In this operation example, the case where the data input value includes a value below the decimal point is shown.

In FIG. 5, first, "10.25" is input as the data input value. By the detection signal 2A, the presettable counter 1 is loaded with the decimal notation "2" corresponding to the data input value "8",
The shift circuit 5 has 10 corresponding to the data input value “2”.
"2" in decimal notation is loaded. The integrating circuit 3 integrates the value corresponding to the data input value "0.25". At this time, the integrated output 3A is used by the programmable delay circuit 4 to delay the next detection signal 2A.

Therefore, in this example, the first detection signal 2
A is delayed by the programmable delay circuit 4 by a delay time of 0 ns and is output through the output terminal 16. Next, the shift circuit 5 operates in response to the clock signal, and the presettable counter 1 counts down by the shift output 5A.
When the state of the shift circuit 5 is "1" and the state of the presettable counter 1 is "0", the detection circuit 2 outputs the second detection signal 2A. The detection signal 2A is delayed by 2.5 ns in the programmable delay circuit 4 and output to the output terminal 16. Therefore, the interval between the first output pulse and the second output pulse at the output terminal 16 is 102.5 ns.

Next, the detection signal 2A inputs the second data input value 2.5, the state of the shift circuit 5 is "2", the state of the presettable counter 1 is "0", and the state of the integrating circuit 3 is "2". 0.75 ". The shift circuit 5 is subsequently operated by the clock signal, and when the shift state is "1" and the counter state is "0", the third detection signal 2A is output. This detection signal 2A corresponds to the output value "0.75" of the integrating circuit in the programmable delay circuit 7.
Output terminal 1 as the third pulse with a delay of 5 ns
6 is output. Therefore, the pulse interval of the second and third output terminals 16 is 25 ns.

Next, by the third detection signal 2A, the third
The data input value "8.75" of the second time is input, the state of the shift circuit 5 is "0", the state of the presettable counter 1 is "2", and the state of the integrating circuit 3 is carry and the integrated value "0.
5 ”. At this time, a carry output is output to the output 3B of the integration circuit 3, and the shift clock 5C of the shift circuit 5 is output.
Is in the same state as when two clocks are connected to one and one shift clock is lost. Therefore, the shift circuit 5 operates with a delay of one clock, and is in a state equivalent to "9" being input for the data input value "8". Therefore, the fourth detection signal 2A is the clock signal 1
Delayed by an amount of 0.5 ns with programmable delay circuit 4
Be delayed. As a result, the interval between the third pulse and the fourth pulse at the output terminal 16 is 90 ns − 7.5 ns + 0.5 ns = 87.5 ns, which is the value corresponding to the data input value. Becomes When a pulse is generated with a resolution smaller than that of the above clock signal, it may be performed in the same manner as in JP-B-63-9686.

[0031]

According to the present invention, since the operating frequency of the presettable counter can be made lower than the basic clock frequency, it is not necessary to operate a complicated counter circuit at a high frequency, and a proper frequency can be set finely. It can be set by resolution.

[Brief description of drawings]

FIG. 1 is a block diagram of a pulse generator according to the present invention.

FIG. 2 is a circuit diagram of a shift circuit.

FIG. 3 is a circuit diagram of a presettable counter.

FIG. 4 is a time chart of each part of the pulse generator.

FIG. 5 is a time chart showing another operation example.

FIG. 6 is a block diagram of a conventional pulse generator.

FIG. 7 is a time chart of each part of a conventional pulse generator.

[Explanation of symbols]

 1 presettable counter 1A count output signal 1B load clock signal 2 detection circuit 2A detection output signal 3 integrating circuit 3A integrating output signal 3B carry output signal 4 programmable delay circuit 5 shift circuit 5A / 5B shift circuit output signal 5C shift clock signal 11・ 13 clock input terminal 12 ・ 14 ・ 15 data input terminal 16 output terminal

Claims (1)

[Claims] 1. A shift circuit (5) for setting data by a first data input terminal (12) and performing a shift operation by a clock pulse from the input terminal (11), and a second data input terminal (14). Data is set by the output of the shift circuit (5), and the output of the shift circuit (5) and the output of the presettable counter (1) are input, and each output is a specific value. When it becomes, a pulse is output and the detection circuit (2) that inputs to the shift circuit (5) and the presettable counter (1) and the data to the third data input terminal (15)
The data is integrated in synchronization with the output of (2), the integrated value is output, and the carry signal based on the integrated result is shifted (5).
Output to the integrating circuit (3) that interrupts the shift operation of the shift circuit (5) and the output of the detecting circuit (2).
Programmable delay circuit that delays (3A) (4)
A pulse generator, comprising: a fractional multiple output from the clock pulse.