JPH07106955A - Ternary counter - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the operational reliability of a ternary counter. The ternary counter includes two trigger type flip-flops TFF1 and TFF2, two delay type flip-flops DFF1 and DFF2, and a NOR gate 15.
It consists of. The input clock CK is sequentially counted ternary by the TFFs 1 and 2, and the reset signal of the TFFs 1 and 2 is generated by the logical output of the NOR gate 15. TF
Outputs Q ₁ and Q ₂ of F ₁ and ₂ are taken in by DFF ₁ and ₂ in synchronization with the input clock CK, and are once applied to the data input D of DFF ₁ and ₂ . Therefore, the outputs Q ₁ and Q ₂ of the TFFs ₁ and ₂ are output from the DFFs ₁ and ₂ with a delay of one pulse. As a result, even if the reset signal is generated with a delay in the NOR gate, the next input clock C
If K is generated by the time it arrives, it operates exactly as a ternary counter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is mainly applied to a digital communication system and, more particularly, to a ternary counter for counting incoming pulse signals.

[0002]

2. Description of the Related Art Conventionally, a ternary counter as shown in FIG. 3 has been known. In the conventional ternary counter, the input clock CK is applied to the data input D of the trigger flip-flop 11 in the first stage, and the inverted output Q is applied to the data input D of the trigger flip-flop 12 in the next stage. Further, the inverted output bar Q of each of the flip-flops 11 and 12 is given to the NOR gate 13, and this logical output is used as the reset signal of these two flip-flops 11 and 12.

By configuring the circuit as described above, the number of waveforms of the input clock CK to be input is counted, and the count value is converted into a binary level signal at each output terminal Q ₁₁ ,
And outputs it to the Q _12. In this case, (Q ₁₁ , Q ₁₂ )
(0,0), (1,0), (0,1), (1,1) are sequentially output, but at the moment when (1,1) is reached, the output of the NOR gate 13 is "1". Therefore, the flip-flops 11 and 12 are immediately reset. Therefore, (Q ₁₁ , Q ₁₂ ) has (0, 0), (1, 0),
(0,1), (0,0), ... Are sequentially output and function as a ternary counter.

[0004]

As described above, in the conventional ternary counter, the output of the NOR gate 13 is used as a reset signal for the two flip-flops 11 and 12, and this reset signal is used as the input clock CK. It is asynchronous with. Therefore, when the signal delay in the NOR gate 13 is large, there is a problem that resetting is not performed at an appropriate timing, a malfunction occurs, and a quaternary counter functions.

The present invention has been made to solve such a problem, and an object thereof is to prevent such malfunction and improve the operation reliability of the ternary counter.

[0006]

A ternary counter according to the present invention comprises a first trigger type flip-flop to which a pulse signal is applied and a second trigger type flip-flop to which an inverted output of the first trigger type flip-flop is applied. As a circuit that includes a trigger type flip-flop and generates a reset signal for resetting the two trigger type flip-flops, a logical sum of the inverted output of the first trigger type flip-flop and the inverted output of the second trigger type flip-flop Equipped with a logical sum circuit. Further, the non-inverted output of the first trigger type flip-flop is taken in synchronization with the pulse signal, and the non-inverted output of the first delay type flip-flop and the second trigger type flip-flop which give this output to the first output terminal. A second delay flip-flop is provided which takes in the inverted output in synchronization with the pulse signal and supplies the inverted output to the second output terminal.

[0007]

The outputs of the first and second trigger type flip-flops are once provided to the first and second delay type flip-flops, respectively. When input, it is given to each output terminal.

Therefore, the outputs of the first and second trigger type flip-flops are sequentially fetched by the first and second delay type flip-flops by one pulse of the pulse signal and given to the respective output terminals. It will be. In addition, at this time, since each delay flip-flop is driven by the pulse signal applied to the data input terminal, all of them are driven synchronously.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a circuit configuration of a ternary counter according to this embodiment. This circuit includes two trigger type flip-flops (hereinafter referred to as TFF), two delay type flip-flops (hereinafter referred to as DFF) and one NOR.
The gate 15 is provided with an input terminal 10 to which an input clock CK as a pulse signal to be counted is applied, and a pair of output terminals 21 and 22 for outputting a count value.

The TFF inverts the state of each output terminal Q and the bar Q every time one input clock CK is input to the data input terminal D, and when a reset signal is input to the reset input terminal R. , The output of each output terminal Q and bar Q is reset to the initial state. Also, DFF
When the input clock CK is applied to the clock input terminal C, the signal applied to the data input terminal D is taken in, the output Q is inverted, and when the reset signal is input to the reset input terminal R, the output Q is initialized. It is a circuit that is reset to the state.

Here, the connection relationship of each FF will be described. The data input terminal D of the TFF1 is connected to the input terminal 10 to which an input clock CK to be counted is given, and its inverting output terminal bar Q is connected to the data input terminal D of the TFF2. The inverting output terminal bar Q of the TFF2 and the inverting output terminal bar Q of the TFF1 in the previous stage are two inputs of the NOR gate, and the logical output thereof is TFF1 and TFF2 as a reset signal for resetting the TFF1 and TFF2. Reset input terminal R of TFF2
Given to.

Further, the non-inverting output terminal Q of the TFF1 is D
It is connected to the data input terminal D of FF1 and this DF
The non-inverting output terminal Q of F1 is connected to one output terminal 21 of the above-mentioned ternary counter. Furthermore, TFF2
The non-inverting output terminal Q of DFF2 is connected to the data input terminal D of DFF2, and the non-inverting output terminal Q of DFF2 is
It is connected to the other output terminal 22 of the ternary counter.

Clock input terminals C of these DFFs 1 and 2
Are commonly connected to the input terminal 10, so that the DFFs 1 and 2 are driven in synchronization with the input clock CK to be counted.

Here, the counting operation of the ternary counter thus constructed will be described with reference to FIG. FIG. 2 shows the output values of the outputs Q _{1 to} Q ₄ for a given number of input clocks. Note that Q ₁ indicates the output of the non-inverting output terminal Q of the TFF ₁ , and Q ₂ indicates the output of the non-inverting output terminal Q of the TFF ₂ . Q ₃ indicates the output of the non-inverting output terminal Q of DFF 1, and Q ₄ indicates the non-inverting output terminal Q of DFF 2.
Shows the output of.

The initial states of the outputs Q ₁ and Q ₂ are both "0". First, when the first input clock CK arrives at the input terminal 10, the output Q ₁ of the TFF ₁ is “1”.
And its inverted output becomes "0". Therefore, the output Q ₂ of the TFF ₂ to which this “0” is applied maintains the “0” state. At this time, DFF1 and DFF2 are output by clock input CK of the one shot eyes is supplied to each data input D when arriving to the clock input C, that the output Q _1, the initial state of the Q ₂ (Q ₁ , Q ₂ ) ＝
(0, 0) is taken in and this value is given to output terminals 21 and 22 as outputs Q ₃ and Q ₄ . Immediately after this, (Q ₁ , Q
₂ ) = (1,0), and this output is DFF1 and DF
Although it is given to the data input terminal of F2, this data is not taken in until the next input clock is given.

Next, when the second input clock CK arrives at the input terminal 10, the DFF1 and DFF2 receive the data given to the respective data input terminals D at this time, that is, (Q ₁ , Q ₂ ) = (1,0) is taken in, and the values are output to the output terminals 21 and 22 as outputs Q ₃ and Q ₄ . After that, even if the values of the outputs Q ₁ and Q ₂ change, new data is not fetched to the DFF 1 and DFF ₂ until the next input clock is applied. Further, in response to the second input clock CK, the output Q ₁ of TFF1 is inverted to "0", and the inverted output "1" is TF.
Given to F2. Therefore, the output Q ₂ of TFF2 is "1".

Next, when the third input clock CK arrives at the input terminal 10, the DFF1 and DFF2 receive the data given to the respective data input terminals D at this time, that is, (Q ₁ , Q ₂ ) = (0, 1) is taken in and these values are output to the output terminals 21 and 22 as outputs Q ₃ and Q ₄ , respectively. After that, even if the values of the outputs Q ₁ and Q ₂ change, the DFF 1 and DFF 2 are driven by the next input clock C.
No new data will be fetched until K is given. At the same time, receiving the input clock CK of the three-shot eyes, output Q ₁ of the TFF1 is inverted to "1", the inverted output is "0". The inverted output “0” is given to the TFF2, but the output Q ₂ thereof maintains “1”. At this time, the inverted outputs of TFF1 and TFF2 both become "0", and only at this time is the NOR gate 15 turned on.
Output becomes "1". As a result, the above-mentioned reset signal is generated, TFF1 and TFF2 are immediately reset, and (Q ₁ , Q ₂ ) = (0, 0).

Next, when the fourth input clock CK arrives at the input terminal 10, the DFF1 and DFF2 receive the data given to the respective data input terminals D at this time, that is, (Q ₁ , Q ₂ ) = (0,0) is taken in, and this value is output to output terminals 21 and 22 as outputs Q ₃ and Q ₄ , respectively. In other words, it will return to the initial state,
Each of the outputs Q ₃ and Q ₄ returns to the initial state at the third time counting from the first input clock CK. Hereafter, this operation is repeated in sequence every time the input clock CK arrives, and as a result, it functions as a ternary counter.

On the other hand, the TFF1 receives the fourth input clock CK, its output Q ₁ is inverted to "1", and its inverted output "0" is given, and the output Q _{2 of} TFF2 is also "0". Invert. This is the same as the state of the first input clock CK, and thereafter, every time the input clock CK arrives once, this operation is sequentially repeated.

As described above, at the output terminals 21 and 22 of the ternary counter configured as described above, the output (Q ₃ , Q ₄ ) of the input clock arrives at every one arrival.
(0,0), (1,0), (0,1), (0,0) ...
It turns out that it changes in order and it functions as a ternary (1/3) counter.

In the embodiment described above, the input clock C
Although K is exemplified as a clock signal that arrives at a fixed cycle, it may be a pulse signal that arrives irregularly.

[0023]

According to the ternary (1/3) counter described above, the outputs of the first and second trigger type flip-flops are once provided to the first and second delay type flip-flops. Both the first and second delay flip-flops are synchronously driven by a pulse signal applied to the data input terminal.

Therefore, the outputs of the first and second trigger type flip-flops are sequentially provided to the respective output terminals from the first and second delay type flip-flops with a delay of one pulse of the pulse signal. Therefore, even if a signal delay occurs in the logical sum circuit that outputs the reset signal, if the reset signal is generated before the arrival of the next pulse signal, it accurately operates as a ternary counter. It will be. As a result, it is possible to increase the margin of time until the reset signal is generated and improve the operation reliability as the ternary counter.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a ternary counter according to the present embodiment.

FIG. 2 is a truth table showing the operation of the ternary counter shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a conventional ternary counter.

[Explanation of symbols]

TFF1 ... Trigger type flip-flop (first trigger type flip-flop), TFF2 ... Trigger type flip-flop (second trigger type flip-flop), DFF1 ...
Delay type flip-flop (first delay type flip-flop), DFF2 ... Delay type flip-flop (second delay type flip-flop), 15 ... NOR
Gate (logical sum circuit), CK ... input clock (pulse _{signal), Q 1, Q 2,} Q 3, Q 4 ... output, 21, 22 ... output terminal.

Claims (1)

[Claims] 1. A ternary counter that counts a given pulse signal and outputs a binary signal level to first and second output terminals to express a count value, wherein the first pulse signal is given. Trigger flip-flop, a second trigger flip-flop to which the inverted output of the first trigger flip-flop is given, an inverted output of the first trigger flip-flop, and the second trigger flip-flop And a logical sum circuit that outputs a reset signal for resetting the first and second trigger type flip-flops based on the result of the logical OR with the inverted output of the first trigger type flip-flop. The inverted output is fetched in synchronization with the pulse signal, and this output is output to the first
A non-inverted output of the first delay type flip-flop applied to the output terminal of the second trigger type flip-flop and the second trigger type flip-flop of the second trigger type flip-flop in synchronization with the pulse signal,
And a second delay flip-flop provided to the output terminal of the ternary counter.