JPH07106964A - Pulse amplifier and D / A converter - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a pulse amplifier with a short settling time. [Structure] An OP amplifier 5 for amplifying a step voltage e1;
To reduce the settling time of the OP amplifier 5,
A correction pulse generator 6 that generates a correction pulse e4 for superimposing on the step voltage e1 input to the P amplifier 5 is provided, and the correction pulse e4 corresponds to the step voltage e1 and has at least an amplitude, a delay, or a polarity. It is characterized in that one is controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a pulse amplifier and D
The present invention relates to a / A converter, and more particularly to a pulse amplifier and a D / A converter which are effective for an electron beam extractor.

[0002]

2. Description of the Related Art Conventionally, various electron beam methods using an electron beam have been used for forming a fine pattern on a sample such as an IC or an LSI. In order to form an LSI pattern with high dimensional accuracy, it is necessary to form a resist pattern having a substantially vertical sectional shape. When an electron beam with an ordinary accelerating voltage is used, a high beam irradiation amount is required for forming a resist pattern, which is a critical path of drawing speed.

Therefore, in order to solve such a problem, a highly sensitive resist for electron beam has been studied and developed. However, as a result of the increase in the scale of the integrated circuit to be extracted, if such a highly sensitive resist is used, the settling time of the pulse amplifier for deflection of the electron beam drawing apparatus is several 10% of the extraction time. This time, the settling time of the pulse amplifier was a critical path for the extraction speed.

By the way, in the case of the stage continuous movement type electron beam extraction apparatus, a ladder net type D / A converter which is a highly accurate D / A converter is used in a stage control circuit for controlling the stage. There is.

However, in the ladder net type D / A converter, an N-bit digital input signal is converted from 1 bit to N bits.
Since each bit is weighted by N-1 power of 2,
If the dynamic characteristics between the digital input signals (for example, pulse rise, fall, delay, transient waveform) do not match, glitches occur. Therefore, in a stage control circuit using this type of D / A converter, a predetermined pattern may not be extracted at a predetermined position due to the occurrence of a glitch.

[0006]

As described above, due to the development of a highly sensitive resist for electron beams and the large scale of integrated circuits to be extracted, the settling time of the pulse amplifier, which has not been a problem until now, has been solved. There was a problem that was a critical path of drawing speed.

Further, a ladder net type D / A converter, which is a highly accurate D / A converter, is used in the stage control circuit of the conventional electron beam drawing apparatus. This D / A converter As a result, a glitch occurs and it is impossible to extract a predetermined pattern at a predetermined position.

The present invention has been made in view of the above circumstances, and a first object thereof is to provide a pulse amplifier having a short settling time. A second object of the present invention is D / which can prevent glitches from occurring.
It is to provide an A converter.

[0009]

In order to achieve the above first object, a pulse amplifier of the present invention (claim 1) is a pulse amplifier main body for amplifying a pulse signal, and a set ring of the pulse amplifier main body. A correction pulse generator for generating a correction pulse signal to be superimposed on a pulse signal input to the pulse amplifier main body in order to shorten the time, and the correction pulse signal is input to the pulse amplifier main body. It is characterized in that at least one of amplitude, delay, and polarity is controlled corresponding to the pulse signal.

According to another pulse amplifier of the present invention (claim 2), a pulse amplifier body for amplifying a pulse signal and an amplitude at the start of rising or falling of the pulse signal input to the pulse amplifier body The pulse signal is divided into a finite number of levels that change discontinuously at a predetermined time interval until the end of the rising edge or the falling edge, and the finite number of steps have a stepwise shape in time series. And a correction pulse for generating a correction pulse signal to be superimposed on the output of the waveform converter input to the pulse amplifier body in order to shorten the settling time of the pulse amplifier body. A generator, the correction pulse signal having a small amplitude, delay, or polarity corresponding to the output of the waveform converter input to the pulse amplifier body. Wherein the Kutomo one is what is controlled.

The pulse amplifier (claims 1 and 2)
When realizing the above, it is preferable to configure as follows. 1. When the amplitude of the pulse signal input to the pulse amplifier (claim 2) is divided stepwise, the size of each stage is set so as not to exceed the current saturation of the circuit constituting the amplifier body.

2. In the pulse amplifier (claims 1 and 2), the amplitude, width, delay, and polarity data of the correction pulse signal are stored in the storage circuit in advance, and the amplitude and the amplitude are corrected from the storage circuit based on the changing polarity and amplitude of the original pulse signal. width,
Read the delay and polarity data, generate the correction pulse,
Reduce settling time.

3. In the pulse amplifier (claims 1 and 2), the amplitude of the pulse signal is AD-converted, a correction pulse signal is generated based on the changing polarity and amplitude of the pulse signal, and the settling time is shortened.

4. In the pulse amplifier (claims 1 and 2), a correction pulse signal having an amplitude and a polarity such that a target output value of the pulse amplifier main body is reached during the width of the correction pulse signal is synchronized with the pulse signal, and the pulse amplifier main body is synchronized. To enter.

5. In the pulse amplifier (claims 1 and 2), the correction pulse signal is input to the output stage of the pulse amplifier body to shorten the settling time. 6. In the above-mentioned 4, when the digital pulse signal is changed into an analog pulse signal by the digital-analog converter and this pulse signal is input to the pulse amplifier main body, the correction pulse generation input is also a digital signal.

7. In the pulse amplifier (claims 1 and 2), when a digital pulse signal is converted into an analog pulse signal by a digital-analog converter and the pulse signal is input to the pulse amplifier main body, the correction pulse signal is added. Is performed digitally, and the sum of the pulse signal and the correction pulse signal is input to the digital-analog converter to shorten the settling time.

8. In the pulse amplifier (claims 1 and 2), a plurality of correction pulse signals are used. 9. In the pulse amplifier (claims 1 and 2), means for making the characteristics of the pulse amplifier main body dominated by first-order lag,
The settling time is set to the pulse width W by means for inputting the correction pulse signal having the pulse width to the pulse amplifier main body at the same time as the pulse signal and means for changing the amplitude of the correction pulse signal. 10. In the above pulse amplifier (claims 1 and 2), the sum of poles and zeros of the characteristic (transfer function) of the pulse amplifier main body and the number of correction pulse signals are made equal, and the amplitude and polarity are such that each pole and zero are canceled, A correction pulse signal having a delay and a width is input to the pulse amplifier main body to shorten the settling time. 11. In the pulse amplifier (claims 1 and 2), of the amplitude, width, and delay of the correction pulse signal, two items are fixed, one item is not fixed, and the polarity is controlled to shorten the settling time. To do. 12. In the pulse amplifier (claims 1 and 2), one of the amplitude, the width and the delay of the correction pulse signal is fixed and the two items which are not fixed are controlled in polarity to shorten the settling time of the pulse amplifier. 13. In the pulse amplifier (claims 1 and 2), the frequency band of the pulse amplifier body is narrowed by a low-pass filter, and a correction pulse whose amplitude, width, delay, and polarity are controlled is synchronized with the changing pulse signal, and the amplification terminator body is used. To shorten the settling time.

Further, in order to achieve the above second object,
A D / A converter of the present invention (claim 3) is a first D / A converting means for D / A converting a digital signal as an input signal and an output signal by integrating an inputted analog signal. Of the first D / A conversion means, and the output of this integration means and that of the first D / A conversion means are analog-added. An analog adding means for performing A / D conversion of the output of the analog adding means, and an A / D conversion of the output of the A / D converting means, and inputting the result to the integrating means. And two D / A conversion means.

Here, for example, by providing an inverting means for inverting the polarity of the output of the A / D converting means between the A / D converting means and the second D / A converting means,
The polarity of the output of the integrating means is opposite to that of the first D / A converting means (claim 4).

Further, another D / A conversion apparatus of the present invention (claim 5) is a D / A conversion means for D / A converting a digital signal as an input signal and an output of the D / A conversion means. Integrating means for outputting an analog signal as an output signal by integrating, and calibrating means for calibrating the output of the integrating means based on the output of the integrating means and the input signal,
Compensation means for compensating the output of the integration means in response to changes in the input signal.

Here, the calibrating means obtains, for example, an A / D converting means for A / D converting the output of the integrating means and a difference between the output of the A / D converting means and the input signal. And a difference detecting means for inputting the result to the D / A converting means (claim 6).

The compensating means, for example, obtains the difference between the current input signal and the previous input signal, and increases or decreases the output of the integrating means by an amount corresponding to the difference (claim 7). .

[0023]

The settling time of the pulse amplifier is determined by the time for charging / discharging the internal capacity and the capacitive load of the pulse amplifier body. That is, the shorter the charging / discharging time, the shorter the settling time.

Therefore, in order to shorten the settling time, the correction pulse signal may be selected so that the charging / discharging time is shortened by the sum of the original pulse signal and the correction pulse signal. That is, the settling time can be shortened by controlling at least one of the amplitude, delay, and polarity that define the characteristics of the correction pulse signal in accordance with the original pulse signal so that the charging / discharging time is shortened.

Therefore, according to the pulse amplifier of the present invention (claims 1 and 2), in addition to the original pulse signal, the correction pulse signal as described above can be simultaneously input to the pulse amplifier main body, so that the settling time is set. Can be shortened.

According to the present invention (claims 3 to 7),
Since the output of the D / A conversion means is integrated by the integration means to obtain the output signal, the glitch contained in the output of the D / A conversion means is absorbed by the integration means. Therefore,
A glitch-free output signal can be obtained.

Further, in the case of the present invention (claim 3), A / D
Since the output of the second D / A conversion means input to the conversion means and that of the integration circuit have the opposite characteristics, a low level (low bit number) signal is input to the A / D conversion means.
Therefore, in addition to obtaining the glitch-free output signal, the A / D conversion means has a high dynamic range of A.
It is possible to use an inexpensive A / D converter having a high dynamic range (low bit number) as compared with the / D converter.

Further, in the case of the present invention (Claim 5), since the calibrating means and compensating means for calibrating and compensating the output of the integrating means are provided, it becomes possible to perform highly accurate D / A conversion.

[0029]

First, the case of an ideal pulse amplifier will be described. FIG. 1 is a block diagram showing an ideal pulse amplifier. In the figure, reference numeral 1 denotes a digital-analog converter (hereinafter referred to as DAC), and digital data 3 and enable pulse 4 are input to the DAC 1.
The enable pulse 4 is input to the impulse generator 2, and the DAC 1 is synchronized with the enable pulse 4.
Converts the input digital data 3 into analog data and generates a step voltage e1 (assuming that the DAC1 generates an ideal step voltage e1). At this time,
The impulse generator 2 generates an impulse voltage e2.

Step voltage e1 generated by DAC1
Is input to the OP amplifier 5 via the resistor R1. The resistor R3 is a feedback resistor of the OP amplifier 5, and the amplification factor G of the OP amplifier 5 is − (R3 / R1). The OP amplifier 5 has a first-order lag with a time constant T (when the characteristic of the OP amplifier 5 is not a first-order lag system, a capacitor is connected in parallel with the resistor R3 to control the first-order lag system). If the output voltage of the OP amplifier 5 is e3, the transfer function thereof is G / (1 + sT) by the Laplace transform,
The step response of the OP amplifier 5 is e3 = [G / {s * (1 + sT)}] * e1.

When this step response is converted into a function of time t, e3 (t) = [G * {1-exp (-t / T)}] e1 (1)

On the other hand, from the impulse generator 2, the ideal (delta function) impulse voltage e2 (pulse width is zero, amplitude is infinity, 1 when integrated) is the step voltage e1.
Occur at the same time. The impulse response of the OP amplifier 5 with respect to the impulse voltage e2 is e3 = {G '/ (1 + sT)} * e2.

Here, G'is the amplification degree of the OP amplifier 5 when the impulse generator 2 is input and is -R3 / R2. When this impulse response is converted into a function of time t, e3 = {G ′ / T} * exp (−t / T) * e2 (2)

When G'is adjusted so that G '/ T in the equation (2) is equal to G in the equation (1) (R2 is adjusted) and the equations (1) and (2) are added, OP The output voltage e3 of the amplifier 5 is e3 = G * {1-exp (-t / T)} * e1 + {G '/ T} * exp (-t / T) * e2.

If G * e1 = (G '/ T) * e2, then e3 = G * e1. That is, the output voltage e3 of the OP amplifier 5 has no relation to the time t, and the input step voltage e1 is multiplied by G without a transient phenomenon and output from the OP amplifier 5.
The settling time can be shortened.

FIG. 2 shows the waveform of the step voltage e1 of the DAC 1, the waveform of the impulse voltage e2 of the impulse generator 2, and the waveform of the output voltage e3 of the OP amplifier 5. In the figure, the broken line is O when the correction by impulse is not performed.
The waveform of the output voltage e3 of the P amplifier 5 is shown.

However, in reality, it is not possible to generate the impulse voltage e2 whose time is zero and whose area is 1.
There is no amplifier to amplify it. Therefore, in the present invention, the settling time is shortened by using the correction pulse correction instead of the impulse voltage e2. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing a pulse amplifier according to the first embodiment of the present invention. Digital data 3 and enable pulse 4 are input to the DAC 1 as in the pulse amplifier of FIG. The digital data 3 and the enable pulse 4 are also input to the correction pulse generator 6.

The polarity, amplitude, and width of the correction pulse e4 output from the correction pulse generator 6 can be controlled, but the delay is not taken into consideration here for the sake of simplicity.

A correction pulse e having a pulse width a is supplied to the OP amplifier 5.
Output voltage e3 of the OP amplifier 5 when only 4 is input
Becomes e3 = e4 * G '{1-exp (-a * s)} / {s * (1 + s * T)} (3).

The output voltage e3 of the OP amplifier 5 when the step voltage e1 generated by the DAC 1 and the correction pulse e4 are simultaneously input to the OP amplifier 5 is e3 = [G * e1 + e4 * G '{1-exp (-a * s)}] / {s * (1 + s * T)}. When this equation is a function of time t, e3 = (G * e1 + e4 * G ') {1-exp (-t / T)}-e4 * G' [1-exp {-(t-a) / T} ] (4) The time from t = 0 to t = a is the pulse width of the correction pulse.

When the amplitude of the correction pulse e4 satisfies e4 = (G * e1 / G ') * exp (-a / T) / {1-exp (-a / T)} (5) The settling time is the correction pulse width a.

Here, T is the time constant of the OP amplifier 5, G is the amplification degree of the DAC 1 side of the OP amplifier 5 (-R3 / R1),
G'indicates the amplification degree (-R3 / R2) on the side of the correction pulse generator 6 of the OP amplifier 5.

FIG. 4 shows the waveform of the step voltage e1 of the DAC 1 and the waveform of the correction pulse e4 of the correction pulse generator 6.
The waveform of the output voltage e3 of the OP amplifier 5 is shown. In the figure, the broken line shows the waveform of the output voltage e3 of the OP amplifier 5 when the correction by the correction pulse is not performed.

Equation (5) is for the case where the pulse width a of the correction pulse is constant, but the same result can be obtained even if the amplitude of the correction pulse e4 is kept constant and the pulse width a of the correction pulse is changed. . That is, the pulse width a of the correction pulse when the amplitude of the correction pulse e4 is constant is a = T * ln {G * e1 / (G ′ * e4) +1}, and the correction pulse e4 is corrected in place of the amplitude. Pulse e
It is understood that the pulse width of 4 may be changed.

FIG. 5 shows that the gain G on the DAC1 side is -1, the step voltage e1 is 1 [V], the gain G'on the correction pulse generator 6 side is -1, and the correction is normalized by the time constant T. It is the figure which plotted the pulse width a on the horizontal axis and the amplitude of the correction pulse on the vertical axis (the above formula (5)).

When the amplitude of the correction pulse is 0.582 times the amplitude of the DAC1 (point P1 in the figure) when the correction pulse width a is T, the settling time of the OP amplifier 5 becomes T,
When the correction pulse width is T / 2, 1.54 times (point P2 in the figure)
Then, the settling time of the OP amplifier 5 becomes T / 2. The impulse voltage e2 in FIG.
Has a pulse width of zero and an infinite amplitude, which is at the left end of FIG.

Next, FIG. 3 shows that when the OP amplifier 5 is a second-order delay system and there are two poles, the settling time is the sum of the two correction pulse widths due to the two correction pulses.

In this case, the output voltage e3 of the OP amplifier 5
Is e3 = [G * e1 + (1-exp (-a * s)) * G '* e4 + {exp (-a * s) -exp (-2 * a * s)} * G' * e5 ] / [s (1 + T1 * s) (1 + T2 * s)] ... (6).

Here, T1 indicates the first pole of the OP amplifier 5, and T2 indicates the second pole of the OP amplifier 5.
The first term of the numerator represents the input, the second term represents the first correction pulse (pulse width a, zero delay), and the third term represents the second correction pulse (pulse width a, delay a). Converting equation (6) into a function of time, e3 = (G * a1 + G '* (e4) (1-T (t)) + G' * (e5-e4) (1-T (ta)) -G '* e5 * (1-T (t-2a)) (7) where T (t), T (ta), T (t-2a) are as follows T (t) = [T1 * exp (-t / T1)-T2 * exp (-t / T2)] / (T1-T2) T (ta) = [T1 * exp (-(ta) / T1) -T2 * exp (-(ta) / T2)] / (T1-T2) T (t-2a) = [T1 * exp (-(t-2a) / T1)-T2 * exp (-(t-2a ) / T2)] / (T1-T2) where the amplitude e4 of the first correction pulse and the amplitude e5 of the second correction pulse are e4 = [exp (a / T1) (1-exp (a / T1 ) -exp (a / T2) (1-exp (a / T2)] * G * e1 / [{1-exp (a / T1)} {1-exp (a / T2)} {exp (a / T2 ) -exp (a / T1)}] (8) e5 = [exp (a / T1) -exp (a / T2)] * G * e1 / [{1-exp (a / T1)} { 1-exp (a / T
2)} {exp (a / T2) -exp (a / T1)}] (9), the settling time is the sum (a + a) of the first correction pulse width and the second correction pulse. Become.

Here, e1 = 1V, T1 = 1 μs, T2
=. When 5 μs and a = 1 μs, e4 = −0.
At 830 V and e5 = 0.09 V, the settling time of e3 is 2 μs.

FIG. 6 shows the waveform of each part in the second-order delay system in which the characteristic of the OP amplifier 5 calculated by the above equation. D from the top
The step voltage e1 of AC1, the correction pulse e4 of the correction pulse generator 6, and the output voltage e3 of the OP amplifier 5 are shown. In the figure, the broken line shows the output voltage e3 of the OP amplifier 5 when the correction by the correction pulse is not performed.

Next, a pulse amplifier according to the second embodiment of the present invention will be described. Here, a case where a large amplitude signal is input to the pulse amplifier will be described. Generally, when a large-amplitude signal is input to a pulse amplifier, current saturation occurs in a transistor inside the pulse amplifier, and its output changes at a constant slope (slew rate). Therefore, at a large amplitude, even if the amplifier is corrected with the correction pulse as in the above embodiment, a remarkable effect cannot be obtained.

Therefore, when a large amplitude that causes current saturation inside the amplifier is input, the input is divided stepwise by an amplitude (including correction pulse amplitude) at which current saturation does not occur, and each stepwise The correction pulse is input to the step to accelerate the output response of the amplifier.

FIG. 7 shows a concrete configuration example of the pulse amplifier according to this embodiment. The staircase pulse generator 7 generates a staircase wave from the amplitude value of the digital data 3 and the staircase setting number set in the staircase setting 8.

That is, the staircase pulse generator 7 compares the amplitude value with the set number of steps, and when the amplitude value is equal to or smaller than the set number of steps, the amplitude value is given to the DAC 1 as it is, while the amplitude value is If the number of stairs is greater than
The amplitude value is divided by the set number of steps, and a step wave is generated from the quotient N and much M.

The staircase wave generated by the staircase pulse generator 7 is N + 1 stages, and the step size of the last stage is M (N is M stages when M is too small). At each step of the stairs, the settling time is improved by the correction pulse having a fixed amplitude, delay and width depending on the amplitude (including polarity) of the step.

Here, the _settling time T _{lrg in} the case of a large amplitude is the corrected amplitude _settling time T
_{If sr} (the width of the correction pulse is fixed and the amplitude and the delay are changed), then T _lrg = (N + 1) · T _sr (10).

FIG. 8 shows the step voltage e input to the DAC 1.
1a, the correction pulse e4 of the correction pulse generator 6 and the output voltage e3 of the OP amplifier 5 are shown. In the figure, the broken line shows the output voltage e3 of the OP amplifier 5 when the correction by the correction pulse is not performed.

FIG. 9 is a block diagram showing a pulse amplifier according to the third embodiment of the present invention. This is an embodiment where the input is analog, the analog input 14 is introduced into the analog delay 10 and the analog-to-digital converter (ADC) 9. The ADC 9 converts the analog input 14 into digital data, which is introduced into the correction pulse generator 6. This correction pulse generator 6 outputs a correction pulse as in the previous embodiment, and this correction pulse is introduced into the OP amplifier 5 via the resistor R2.

On the other hand, the analog input 14 introduced into the analog delay device 10 is synchronized with the correction pulse by the analog delay device 10 and is input to the OP amplifier 5 together with the correction pulse via the resistor R1. . By thus superimposing the correction pulse on the analog input 14, the settling time becomes the correction pulse width.

FIG. 10 is a block diagram of a pulse amplifier according to the fourth embodiment of the present invention. This is an example for improving the settling time caused by the inductive load R (specifically, for example, a wiring electrode or a transmission cable).

The outputs of the correction pulse generators 6a and 6b are input to the voltage / current converters 27a and 27b, respectively, and the outputs of the correction pulse generators 6a and 6b are converted to the correction pulse currents i1 and i2, respectively. . Correction pulse current i1
Is used to correct the pole of the OP amplifier 5, and the correction pulse current i2 is used to correct the pole due to the capacitive load. With these correction pulse currents, the settling time of the output e becomes a correction pulse.

Next, FIG. 10 shows that the settling time of the output voltage e6 can be made equal to the correction pulse a.
The output voltage e6 is e6 = [G * e1 + (1-exp (-a * s)) * R3 * i1] / [s (1 + T1 * s) (1 + T2 * s)] + (1- exp (-a * s)) * R * i2 / [s (1 + T2 * s)] ... (11)

Here, T1 is the pole of the OP amplifier 5, T
2 is a pole (= CR) of the output voltage e6. The first term of the numerator is the input, the second term is the input correction pulse (pulse width a), and the third term is the output correction pulse (pulse width a).

Converting equation (11) into a function of time, e6 = (G * a1 + R3 * i1) (1-T (t))-R3 * i1 * (1-T (ta)) + R * i
2 * (1-exp (-t / T2))-R * i2 * (1-exp (-(ta) / T2))
(12)

Here, T (t) and T (t-a) are T (t) = [T1 * exp (-t / T1) -T2 * exp (-t / T2)] / (T1-T2) ) T (ta) = [T1 * exp (-(ta) / T1)-T2 * exp (-(ta) / T2)] / (T1-T2).

Here, the amplitude i of the first correction pulse current is
When the amplitude i2 of the first and second correction pulse currents is selected according to the following equation, the settling time becomes the correction pulse width a. i1 = G * e1 / [R3 * {-1 + exp (a / T1)}] ... (13) i2 = [1- {1-exp (a / T2)} / {1-exp (a / T2)}] * G * e1 * T2 / [R * {T1-
T2} {1-exp (a / T2)}] (14) where e1 = 1
V, T1 = 1 μs, T2 =. When 5 μs and a = 1 μs, R3 · i1 is −0.582 V and R · i2 is −
At 0.425 V, the settling time for e3 is 1 μs.

Thus, according to the present embodiment, the settling time can be set to the width of the correction pulse, and in the case of a capacitive load, the settling time is determined by the capacitance, so that the speed of the pulse amplifier, which has been difficult with the prior art, is increased. However, in the case of the present embodiment, there is no limitation from the floating capacity, capacitive load, etc.,
The speed of the pulse amplifier can be easily increased.

FIG. 11 is a block diagram of a pulse amplifier according to the fifth embodiment of the present invention. This is the correction pulse D
It is an example in the case of composition within AC data. The digital data 3 is input to the adder 11 and the correction pulse data generator 12. The correction pulse data generator 12 generates a correction pulse width, an amplitude, and a polarity, adds them together with the digital data 3 by the adder 11, and inputs them to the DAC 1. The value obtained by adding the digital data 3 and the correction pulse data is DA
C1 outputs, and this output is input to the OP amplifier 5 via the resistor 1 and amplified. In this way, the correction pulse is
By being combined in the AC data and introduced into the OP amplifier 5, the settling time is improved.

FIG. 12 is a block diagram of a pulse amplifier according to the sixth embodiment of the present invention. This is provided with a plurality of correction pulse generators 6 (here, three), and the enable pulse delay unit 13 shifts the correction timing, and three correction pulses having different delay times are respectively provided to the resistors R2 and R.
By inputting to OP amplifier 5 via 4, R6,
This is an embodiment for improving the settling time of the OP amplifier 5.

FIG. 13 is a block diagram showing a specific structure of the correction pulse generator 6, and FIG. 14 is a timing chart showing the operation of the correction pulse generator 6. DAC
The current data of the data is stored in the latch A15, and the previous data immediately before the current data is stored in the latch B16. DA
The current data and the previous data of the C data 3 are subtracted by the subtractor 17, and the output of the subtractor 17 causes the amplitude data memory Ma19 regarding the amplitude data of the correction pulse, the delay data memory Md20 regarding the delay data of the correction pulse, and the pulse of the correction pulse. The address of the pulse width data memory Mw21 regarding the width data is designated. The pulse amplitude data memory Ma19, the delay data memory Md20, and the pulse width data memory Mw21 are pre-operated in advance, respectively.
Amplitude (including polarity) data of the correction pulse, delay data, and pulse width data data are set so that the settling time of the amplifier 5 is optimized.

The enable pulse (ENB) 4 is delayed by the programmable delay line Dd22, and the output signal w of this programmable delay line Dd22 is delayed by the programmable delay line Dw23. Programmable delay line D
The delay time of the output signal d of d22 and the output signal w of the programmable delay line Dw23 is determined by the output data of the delay data memory Md20 and the pulse width data memory Mw21.

The output signal d of the programmable delay line Dd22 and the output signal w of the programmable delay line Dw23 are input to the delay / width pulse combination DWC25, and this delay
The width pulse synthesizing DWC 25 synthesizes the output d and the output w, which are input signals, and outputs a correction enable pulse (correction DACENB) to the correction DAC 26.

The selector 24 outputs the output signal d and the output signal w.
In synchronization with the above, the output A of the amplitude data memory Ma19 and the output B of the latch C18 are switched. The information of the output A is the amplitude of the correction pulse, and the information of the output B of the latch C18 is the correction DA.
This is data for making the output of C26 zero. The correction DAC 26 generates a correction pulse based on one of the output A and the output B selected by the selector 24 and the enable pulse combined by the delay / width pulse combination DWC 25.

The correction pulse generator generates only one correction pulse for the enable pulse 4, but the amplitude data memory Ma19 and the delay data memory Md are used.
Two correction pulses can be generated by increasing the number of the pulse width data memory 20, the pulse width data memory Mw21, the programmable delay lines Dd and Dw, and the input of the selector 24 by one set. That is, a plurality of correction pulses can be generated by increasing the inputs of various memories, a set of programmable delay lines, and a selector, and the settling time can be improved even if there are a plurality of poles and zero points. it can.

FIG. 15 is a circuit diagram showing a specific structure of the voltage-current converter. When a pulse having a positive polarity is input to this circuit, the transistor TR1 is turned off and the transistor TR3 is turned on.
The base current of 2 does not flow, but the base current of the transistor TR4 flows. Therefore, the collector current of the transistor TR4 becomes the output current.

On the other hand, when a pulse having a negative polarity is input, the transistor TR1 is turned on and the transistor TR3 is turned off, so that the base current of the transistor TR2 flows but the base current of the transistor TR4 does not flow. Therefore, the collector current of the transistor TR2 becomes the output current. The polarity of the voltage of the input pulse and the polarity of the output current are opposite.

FIG. 16 is a block diagram of a pulse amplifier according to the seventh embodiment of the present invention. This is the inductive load L
(Specifically, this is an embodiment for improving the settling time caused by, for example, the deflection coil of the electron beam extractor), which is the pole T2 of the pulse amplifier of FIG.
It has a configuration in which R is replaced with R / L.

FIG. 17 is a block diagram showing another specific structure of the correction pulse generator. In order to simplify the description, the upper 4 bits of the DAC data will be described here.

N bits to N-3 bits indicate DAC data (N bits are MSB), and these N bits to N-3.
Each bit is a rising / falling detector 4
1 to 44 are input. The rising / falling detectors 41 to 44 are R if the input bit is a rising edge,
If it is a fall, F is set to "1" and this is output. If there is no change in the input bit, "0" is output.

The latches 51 to 58 previously store the corrected DAC data at the rising and falling edges of the bits as CP.
Input by U. For example, N-bit rising correction DAC data is stored in the latch 51, and falling falling correction DAC data is stored in the latch 55.

Rising / falling switching devices 61-68
Selects zero or the contents of latches 51-58 according to the outputs of rising / falling detectors 41-44. The outputs of the rising / falling switches 61, 62 are the adder 71, the outputs of the rising / falling switches 63, 4 are the adder 72, and the rising / falling switches 65, 66.
Is output by the adder 73, and the rising / falling switch 6
The outputs of 7, 68 are added by the adder 74.

The outputs of the adders 71 and 72 are the adder 75,
The outputs of the adders 73 and 74 are added by the adder 76, and the outputs of the adders 75 and 76 are added by the adder 77. Adder 7
1, 72 and 75 add rising data and adder 7
3, 74 and 76 add the falling data.

The addition data switch 78 is configured to add zero and adder 7
The output of 7 is switched and input to the correction DAC 26. A correction pulse is generated by the control pulse 81 by the input of the correction DAC 26 and the correction DACENB.

FIG. 18 is a timing chart of the correction pulse generator of FIG. Switching is performed by the rising / falling detectors 41 to 44 from the DAC data (N to N-3 bits). The addition data switch 78 is a correction D
Switch from zero data to addition data before the first ENB of ACENB, input addition data to the correction DAC 26, switch to zero before the second correction DACENB,
Generate a correction pulse. In addition, the rising / falling reset signal is output to the rising / falling detector 41.
~ 44 prepare for next rising / falling edge detection. The time of the first pulse and the second pulse of the correction DACENB is the width of the correction pulse.

FIG. 20 is a block diagram of a pulse amplifier according to the seventh embodiment of the present invention. This is achieved by connecting the capacitor C in parallel with the resistor R3 that is the feedback resistor of the OP amplifier 5 and narrowing the frequency band of the OP amplifier 5.
The noise of the output of the OP amplifier 5 is reduced.

It is known that noise is proportional to the frequency band of the OP amplifier, and the frequency band B of the OP amplifier 5 has the following relationship with the feedback resistor 3 and the feedback capacitor C. B = 2
・ Π / C ・ R3 As shown in this equation, feedback capacitor C
Since the frequency band B is inversely proportional to the frequency band B, the capacitance of the feedback capacitor C may be increased to reduce the noise of the OP amplifier 5.

However, if the capacitance of the feedback capacitor C is increased, the rise time and fall time of the OP amplifier 5 will be delayed. Therefore, a correction pulse is generated by the correction pulse generator 6 to accelerate charging / discharging of the feedback capacitor C and solve the above problem.

FIG. 21 shows the waveforms of the output voltage e3 of the OP amplifier 5 and the correction pulse e4. The shaded area surrounded by the output voltage e3 before and after the correction indicates the amount of electric charge to charge the feedback capacitor C. Feedback capacitor C shown with diagonal lines
Is charged by the correction pulse via the resistor R2, and the correction pulse is adjusted (for example, the amplitude, width, and delay amount of the correction pulse are adjusted) so that the charge amount becomes equal.
Here, if the capacitance of the feedback capacitor C is increased, noise is reduced, but it is necessary to increase the correction amount of the correction pulse.

FIG. 19 shows the relationship between the number of bits of the DAC and the settling time {t / T = 0.62931 * (N + 1)} normalized (t / T) with the time constant T of the OP amplifier. It is a characteristic view to show.

At the maximum amplitude of 8-bit DAC, the settling time becomes ½ LSB or less, 6.2 times the time constant T (point P3 in the figure), and in the case of the 12-bit DAC, 9 times the time constant T. Double (point P4 in the figure), 20-bit DAC
In this case, 14.6 times the time constant T (point P5 in the figure) is required.

If the influence of the slew rate is ignored (small amplitude), the correction pulse width is 6.2 times in the case of an 8-bit DAC and 9 times in the case of a 12-bit DAC, with a time constant T and an amplitude of 0.582. In the case of 20-bit DAC, it is improved by 14.6 times.

The correction pulse width is 1/2 of the time constant T,
If the amplitude is set to 1.54, it is 12.
In the case of 4 times, 12-bit DAC, 18 times, 20-bit D
It is 29,2 times improved in the case of AC.

The DAC bit number 12 and the correction pulse width are set to O.
Considering the settling time in consideration of the slew rate when the time constant T of the P amplifier, the ratio of the large amplitude to the small amplitude is 64, and the number of steps of the staircase is 64, the settling time is as follows.

Generally, the large amplitude settling time is 20 to 100 times that of the small amplitude due to the slew rate. That is, if the settling time at a small amplitude is 100 nS, the settling time at a large amplitude is 2 μS to 100 μS.
It becomes S.

For example, the settling time of the 20-bit DAC is about 14.5T from FIG. 19 (point P5),
Due to the slew rate, the settling time is about 290
It becomes T-1450T.

Since the correction pulse width T and the number of steps of the staircase are 64, the settling time at the time of the large amplitude is 64T,
The large amplitude settling time is improved to about 4.5 to 22.7 times.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the characteristic (transfer function) of the OP amplifier is a first-order lag and a second-order lag has been described, but the present invention can be applied to the case of a third-order lag or more. In this case, the end of the final correction pulse and the settling time can be made equal by making the sum of the pole and zero of the transfer function equal to the number of correction pulses.

Although the DAC output voltage has a step waveform, the settling time can be shortened by the correction pulse even if the waveform has a delay characteristic such as primary, secondary, ... When the output of the DAC is a current, the settling time can be improved by the correction pulse including the floating capacitance of the output of the DAC. That is, the settling time of the DAC itself can be improved.

Although the correction pulse has been described as an ideal pulse, a pulse having distortion may be used as long as it can charge and discharge the floating capacitance, the feedback capacitance and the like. Further, by applying the correction pulse to the output of the logic element as an application of the correction pulse, the overshoot of the output of the logic element can be improved.

FIG. 22 is a block diagram of an analog comparison type D / A converter according to the eighth embodiment of the present invention.
In the figure, reference numeral 111 denotes a first D / A converter 111, and a digital input signal 110, which is an input signal, is input to the first D / A converter 111. This first D
The A / A converter 111 follows the enable signal 109 according to
The digital input signal 110 is converted into a voltage analog signal (analog voltage signal) at a predetermined timing. This analog voltage signal is input to the amplifier circuit 118 configured by the resistor R20 and the amplifier 117.

In the figure, reference numeral 112 denotes a second D / A converter, and the analog voltage signal output from the second D / A converter 112 is the amplifier 113 and the capacitor C.
It is input to the integrating circuit 119 constituted by 20 and.

The integrating circuit 119 outputs an analog current signal having a reverse polarity to that of the first D / A converter 111, and the analog current signal having a reverse polarity is A / D via the resistor R21b.
It is input to the converter 114.

At this time, the analog current signal output from the amplifier circuit 118 is also input to the A / D converter 114 via the resistor R21a (the value of this resistor R21a is the same as that of the resistor R21b).

That is, the A / D converter 114 has a resistor R
The voltage at the connection point M between 21a and the resistor R21b is converted into a digital value D. Here, the A / D converter 114 is adapted to perform A / D conversion at a predetermined timing in accordance with the enable signal 109 input via the delay circuit 115.

The digital signal output from the A / D converter 114 has its polarity inverted by the polarity inverting circuit 108, and then is input to the second D / A converter 112 and converted into an analog voltage signal. . This second D / A converter 11
The analog voltage signal that is the output of 2 is input to the integrating circuit 119. Here, the second D / A converter 112 performs D / A conversion at a predetermined timing according to the enable signal 109 input via the delay circuits 115 and 116.

The integrating circuit 119 outputs an analog current signal corresponding to the integration (sum) of the current output of the second D / A converter 112 and the previous output of the second D / A converter 112. It has become.

Such a circuit operation causes the voltage VM at the connection point M.
The analog current signal of a predetermined level is output from the integrating circuit 119 by repeating the process until the value of is zero. Here, the condition that the value of the voltage VM becomes zero is as follows.

The output voltage V1 of the amplifier circuit 118 is V1 = -I _ss × R, where I _{ss is} the current value per LSB of the first DA converter 111 and R is the resistance value of the resistor R21a. At this time, assuming that the output of the integrating circuit 119 is zero, the value of the voltage VM at the connection point M is V1 / 2.

[0111] Further, the output current I ₂ of the second D / A converter 112, when the current value I _s per 1LSB of the second DA converter 112, and I ₂ = -D × I _s.

The output voltage V2 of the integrating circuit 119 and the value of the capacitor C20 of the integrating circuit 119 are the same as those of the integrating circuit 11
When the voltage per 1 LSB of the output of 9 is V _s and the time interval of the enable pulse signal 109 is T, V2 = D × I _s × T / C C = I _s × T / V _s .

[0113] At this time, the voltage VM at the connection point M, the _{VM = V1 + V2 = -I ss} × R + D × I s × T / C.

Therefore, the condition that the VM becomes zero is as follows: I _ss × R = D × I _s × T / C.

According to this embodiment, the D / A converters 111,
The glitch 112 is absorbed by the integration circuit 119, and noise such as glitch can be reduced. In addition, the integration circuit 119
Has a large phase margin, and due to its characteristics, overshoot,
It is stable with no transient decrease such as undershoot.

Therefore, if the D / A converter of the present embodiment is used in the stage control circuit of the stage continuous movement type electron beam drawing apparatus, glitches can be eliminated and a predetermined pattern can be reliably extracted at a predetermined position. become able to. Further, by controlling the integration circuit 119 during blanking, noise can be further reduced.

Further, since the polarity of the output of the amplifier circuit 118 is opposite to that of the integrator circuit 119, the level of the signal input to the A / D converter 114 is low. Therefore, an A / D converter having a small dynamic range (number of bits) can be used as the A / D converter 114. That is, an inexpensive A / D converter with good characteristics is sufficient.

FIG. 23 is a block diagram of a pulse integration type D / A converter according to the ninth embodiment of the present invention. Further, FIG. 24 is a timing chart showing the operation of the D / A conversion device of FIG.

The main difference of the D / A converter of this embodiment from that of the eighth embodiment is that the output of the integrating circuit is calibrated,
There is compensation. The calibration of the integrating circuit before using the D / A converter is as follows.

First, the calibration signal 132 is input to the control circuit 126. As a result, the A / D enable pulse signal is sent from the control circuit 126 to the A / D converter 125. A
Upon receiving the A / D enable pulse signal, the / D converter 125 performs A / D conversion on the analog signal output from the resistance integrating circuit 129 including the amplifier 124 and the capacitor 30. The output of the A / D converter 125 is output together with the digital input signal 130, which is an input signal, to the first subtractor 12
8 and the first subtractor 128 outputs the difference between these signals.

At this time, the control circuit 126 sends the SW signal to the switch 122 so that the switch C of the switch 122 is selected. That is, the output (difference signal) of the first subtractor 128 is selectively sent to the D / A converter 123.

Further, the control circuit 126 includes the D / A converter 1
A D / A enable pulse signal is sent to 23 so that the output of the first subtractor 128 is D / A converted by the D / A converter 123.

By repeating the above operation, the first subtractor 12
The output of the integrating circuit 129 is calibrated so that the differential signal of 8 becomes zero. As a result, an accurate analog output signal 133 corresponding to the digital input signal 130 is obtained.

Further, even after the calibration as described above, even if the digital input signal 130 fluctuates, an accurate analog output signal 133 can be obtained by the following compensation. The previous digital input signal is stored in the latch circuit 120, and the previous digital input signal is input to the second subtractor 121 together with the current digital input signal 130. There is. Here, the latch circuit 120 is controlled by the enable signal 131.

The second subtracter 121 sends the difference signal between the previous digital input signal and the current digital input signal 130 to the switch 122. At this time, the control circuit 126
A SW signal is sent to the switch 122 so that the switch A of the switch 122 is selected. That is, the output (difference signal) of the second subtractor 121 selectively outputs the D / A converter 12
To be sent to 3.

Further, the control circuit 126 includes the D / A converter 1
A D / A enable pulse signal is sent to 23 so that the output (difference signal) of the second subtractor 121 is D / A converted by the D / A converter 123.

Next, the control circuit 126 switches the switch 122 to SW.
A signal is sent so that the switch B of the switch 122 is selected. That is, the zero level output (null signal) of the zero output circuit 127 is selectively sent to the D / A converter 123. The operation of inputting a null signal to the D / A converter 123 can be omitted.

After this (after a predetermined time), the control circuit 126
Sends a D / A enable pulse signal to the D / A converter 123. As a result, the D / A conversion 123 performs D / A conversion, and the output of the D / A conversion 123 is input to the integrating circuit 129.

Here, the output voltage of the integrating circuit 129 becomes lower in proportion to the pulse width T of the D / A enable pulse signal as shown in FIG. 24, for example. When the next D / A enable pulse signal is sent to the D / A converter 123, the output voltage of the integrating circuit 129 further decreases in proportion to the pulse width T, as shown in FIG. In this way, the compensation of the integrating circuit 129 is performed.

The reason why the output of the integrating circuit 129 is proportional to the pulse width T is as follows. That is, the time interval T of the D / A enable pulse signal, the difference signal of the subtractor 121 is DIF, the current per 1 LSB of the D / A converter 123 is I _s , and the output voltage of the integrating circuit 124 before integration is V _0. Then, the output voltage V of the integrating circuit 124 can be expressed as V = −DIF × I _s × T + Vo.

Therefore, it can be seen from the above equation that the output voltage V of the integrating circuit 124 is proportional to the pulse width T. In this way, the output of the integrating circuit 129 can be compensated, in other words, the nonlinearity of the integrating circuit 124, the D / A converter 123, etc. can be compensated by adjusting the magnitude of the pulse width T.

The long-term stability such as drift of the integrating circuit 124 is compensated by the A / D converter 125. The rising and falling settling time of the output of the integrating circuit 124 is T, and no transient output such as undershoe or overshoot occurs. Also in this embodiment, D / A
Since the glitch of the converter 123 is absorbed by the integrating circuit 129, the glitch can be prevented from occurring.

[0133]

As described in detail above, according to the pulse amplifier of the present invention, since the correction pulse signal for shortening the charging / discharging time of the internal capacitance and capacitive load of the pulse amplifier main body is given, the settling time can be shortened. . In addition, D of the present invention
According to the / A converter, the output of the D / A converter is integrated to generate the output signal, so that an output signal without glitch can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an ideal pulse amplifier.

FIG. 2 is a diagram showing an input / output relationship of the pulse amplifier of FIG.

FIG. 3 is a schematic diagram showing a pulse amplifier according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an input / output relationship of the pulse amplifier of FIG.

FIG. 5 is a diagram showing a relationship between a correction pulse width and a correction pulse amplitude.

FIG. 6 is a diagram showing an input / output relationship of a pulse amplifier when the OP amplifier is a second-order delay system and there are two poles.

FIG. 7 is a schematic diagram showing a pulse amplifier according to a second embodiment of the present invention.

8 is a diagram showing an input / output relationship of the pulse amplifier of FIG.

FIG. 9 is a schematic diagram showing a pulse amplifier according to a third embodiment of the present invention.

FIG. 10 is a schematic diagram showing a pulse amplifier according to a fourth embodiment of the present invention.

FIG. 11 is a schematic diagram showing a pulse amplifier according to a fifth embodiment of the present invention.

FIG. 12 is a schematic diagram showing a pulse amplifier according to a sixth embodiment of the present invention.

FIG. 13 is a block diagram showing a specific configuration of a correction pulse generator.

FIG. 14 is a timing chart of a correction pulse generator.

FIG. 15 is a circuit diagram showing a specific configuration of a voltage-current converter.

FIG. 16 is a schematic diagram showing a pulse amplifier according to a seventh embodiment of the present invention.

FIG. 17 is a block diagram showing another specific configuration of the correction pulse generator.

FIG. 18 is a timing chart showing the operation of the correction pulse generator shown in FIG.

FIG. 19 is a characteristic diagram showing the relationship between the number of DAC bits and the settling time.

FIG. 20 is a schematic diagram showing a pulse amplifier according to a seventh embodiment of the present invention.

21 is a diagram showing the relationship between the output of the OP amplifier and the output of the correction pulse generator of the pulse amplifier of FIG.

FIG. 22 is a block diagram of a D / A conversion device according to an eighth embodiment of the present invention.

FIG. 23 is a block diagram of a D / A conversion device according to an eighth embodiment of the present invention.

FIG. 24 is a flowchart showing the operation of the D / A conversion device of FIG.

[Explanation of symbols]

 1 ... DAC 2 ... Impulse generator 3 ... Digital data 4 ... Enable pulse 5 ... OP amplifier (pulse amplifier main body) 6, 6a, 6b ... Correction pulse generator 7 ... Stair pulse generator 8 ... Stair setting device 9 ... ADC 10 ... Analog delay device 11 ... Adder 12 ... Correction pulse data generator 13 ... Enable pulse delay device 14 ... Analog input 15 ... Latch A 16 ... Latch B 17 ... Subtractor 18 ... Latch C 19 ... Amplitude data memory Ma 20 ... Delay data Memory Md 21 ... Pulse width data memory Mw 22 ... Programmable delay line Dd 23 ... Programmable delay line Dw 24 ... Selector 25 ... Delay / width pulse synthesis DWC 26 ... Correction DAC 27a, 27b ... Voltage-current converter 41-44 ... Fall detector 51-58 ... Latch 61-68 ... Rising / falling switch 71-77 ... Adder 78 ... Addition data switch e1 ... Step voltage e2 ... Impulse voltage e3 ... Output voltage e4 ... (First) correction pulse e5 ... (Second) correction pulse e6 ... Output Voltage 108 ... Polarity inversion circuit 109 ... Enable signal 110 ... Digital input signal 111 ... First A / D converter 112 ... Second A / D converter 113 ... Amplifier 114 ... A / D converter 115, 116 ... Delay Circuit 117 ... Amplifier 118 ... Amplification circuit 119 ... Integration circuit C20 ... Capacitors R20, R21a, R21b ... Resistance 120 ... Latch circuit 121 ... Second arithmetic unit 122 ... Switch 123 ... D / A converter 125 ... A / D conversion Unit 126 ... Control circuit 127 ... Zero output circuit 128 ... First arithmetic unit 129 ... Integrator circuit 130 ... Digital input signal 13 ... enable signal 132 ... calibration signal

Claims (7)

[Claims] 1. A pulse amplifier main body for amplifying a pulse signal, and a correction pulse signal for superimposing on a pulse signal input to the pulse amplifier main body in order to shorten a settling time of the pulse amplifier main body. A correction pulse generator, wherein the correction pulse signal has at least one of amplitude, delay, and polarity controlled according to the pulse signal input to the pulse amplifier body. And pulse amplifier. 2. A pulse amplifier main body for amplifying a pulse signal, and an amplitude from a rising or falling start of a pulse signal input to the pulse amplifier main body to an ending of the rising or falling of the pulse signal for a predetermined time. A waveform converter for converting the pulse signal into a waveform so that the finite number of levels are discontinuously changed at intervals and the number of the finite levels becomes stepwise when viewed in time series, and a pulse amplifier main body In order to shorten the settling time, a correction pulse generator that generates a correction pulse signal to be superimposed on the output of the waveform converter that is input to the pulse amplifier body is included, and the correction pulse signal is , At least one of amplitude, delay, and polarity is controlled in accordance with the output of the waveform converter input to the pulse amplifier body. Pulse amplifier according to claim. 3. A first D / A conversion means for D / A converting a digital signal as an input signal, and an analog signal as an output signal is output by integrating the inputted analog signal. An integrating means whose polarity is opposite to that of the first D / A converting means, an analog adding means for adding the output of the integrating means and that of the first D / A converting means by analog, and an analog adding means. And A / D conversion means for A / D converting the output of the A / D conversion means, and second D / A conversion means for D / A converting the output of the A / D conversion means and inputting the result to the integrating means. A D / A conversion device characterized by the following. 4. An inversion means for inverting the polarity of the output of the A / D conversion means is provided between the A / D conversion means and the second D / A conversion means, whereby the integration means 4. The D / A converter according to claim 3, wherein the polarity of the output is opposite to that of the first D / A converter. 5. A D / A conversion means for D / A converting a digital signal as an input signal, and an integration means for outputting an analog signal as an output signal by integrating the output of the D / A conversion means, Comprising: calibration means for calibrating the output of the integrating means based on the output of the integrating means and the input signal; and compensating means for compensating the output of the integrating means in response to changes in the input signal. D / characterized by
A converter. 6. The calibration means outputs the output of the integration means as A
A / D conversion means for D / D conversion, and a difference detection means for obtaining a difference between the output of the A / D conversion means and the input signal and inputting the result to the D / A conversion means. The D / A according to claim 5.
Converter. 7. The compensating means obtains the difference between the current input signal and the previous input signal and increases or decreases the output of the integrating means by an amount corresponding to the difference. The D / A conversion device described in 1.