JPH07106980A - Encoding device and serialization device - Google Patents

Abstract

(57) [Summary] [Purpose] Efficiently serialize variable-length codes generated by parallel processing. [Structure] Image data divided into eight phases is input to the input terminals 10A to 10H. The B2 coding circuit 22 of each processing circuit 14A to 14H B2 codes the image data. The generated B2 code is temporarily stored in the FIFO memory 30. The counter 20 counts the number of input image data, the decoder 32 detects the end of the image data to be processed, and outputs a B2 encoding processing completion signal to the FIFO memory 3
4 is applied. Initially, the switches 50 and 52 are the processing circuit 1
The data stored in the memory 30 is transferred to the FIFO memory 54 by connecting to the outputs of the 4A FIFO memories 30 and 34. When the B2 coding completion signal is detected in the memory 34, the counter 58 counts up, whereby
The switch control circuit 60 switches the switches 50 and 52 to the next processing circuit 14B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
For example, the present invention relates to a coding device for variable-length coding an image signal and outputting it on a single-phase transmission path. The present invention also relates to a serialization device that serializes processed data in a parallel processing device that may have different data amounts.

[0002]

2. Description of the Related Art Conventionally, when processing a video signal in real time, a configuration is known in which a parallel processing system is adopted in consideration of processing speed.

FIG. 1 shows a schematic block diagram of a conventional example. In this conventional example, the image information is divided into eight phases, which are subjected to variable length coding in parallel by a processing circuit having the same configuration, and then combined into one phase.

That is, each image signal divided into eight phases A to H is input to the eight input terminals 110 (110A to 110H), and the input terminal 112 is a clock synchronized with the image data input to the input terminal 110. Signal is input. The eight parallel processing circuits 114 (114A to 114H) have exactly the same circuit configuration, and the details of the internal circuit are shown only for the processing circuit 114A.

In the processing circuit 114A, 120 is a counter for counting the number of input image data, 122 is a B2 coding circuit, 124 is a 3-bit adder, 126 is a latch for storing the addition value of the previous clock, and 128 is a bit. A shifter, 130 is a FIFO memory for temporarily storing the B2 code, 132 is a decoder for detecting the end of the input image data from the output value of the counter 120, 134 is a counter for counting the number of times of writing data to the FIFO memory 130,
Reference numeral 136 is a logic circuit for controlling the counter 134, 138 is a down counter for counting down the total number of data writes to the FIFO memory 130, and 140 is counter 1.
38 is a logic circuit for controlling 38, and 142 is a decoder for producing a FIFO0 read completion signal from the output value of the counter 138.

When the processing circuits 114A to 114H and their internal circuits are distinguished from each other or particularly, the codes A to H for identifying the phase are added to the respective codes. Other than that, each circuit is described without adding AH.

A switch 150 selects an output of the FIFO memory 130 of each processing circuit 114A to 114H, and a switch 15
2 is a switch for selecting the output of the decoder 142 of each processing circuit 114A to 114H, 154 is a FIFO memory for temporarily storing the data from the switch 150 for output, 15
6 is an output terminal for outputting encoded image data to the outside, 15
8 is a decoder 142 selected by the switch 152
A switch control circuit that switches the switches 150 and 152 according to the outputs of A to 142H.

The switches 150 and 152 are interlocked with each other. That is, the switch 150 is the processing circuit 114A.
When (the FIFO memory 130A of) is selected, the switch 152 selects the same processing circuit 114A (the output of the decoder 142A of the same), and when the switch 150 selects (the FIFO memory 130C of) the processing circuit 114C. , The switch 152 has the same processing circuit 114
C (the output of the decoder 142C) is selected.

The switch control circuit 158 controls the switch 15
0 and 152, the signal processing circuits 114A, 114B, 11
4C, ..., 114H are sequentially selected. That is, when the switch control circuit 158 detects the read completion signal from the decoder 142A of the signal processing circuit 114A, it switches the signal processing circuit 114B to the switches 150 and 152, and upon detecting the read completion signal from the decoder 142B of the signal processing circuit 114B, The switches 150 and 152 are switched to the signal processing circuit 114C.

Next, the data flow in the conventional example will be described. As shown in FIG. 2, the image signal to be encoded is separated into eight phases as viewed on the monitor screen and input to the input terminals 110A to 110H, respectively. Each signal processing circuit 1
14 (114A to 114H), the B2 encoding circuit 1
22 converts the image data from the input terminal 110 (110A to 110H) into B2 code. The B2 coding circuit 122 outputs the 16-bit B2 code itself and the 3-bit code length data. The B2 code itself is input to the bit shifter 128 while being aligned on a 16-bit wide bus according to the accumulated value of the bit length of the B2 code. Therefore, the B2 code having a bit length shorter than 16 bits is output by stacking the B2 codes output later until it becomes 16 bits inside the bit shifter 128. The cumulative value of the bit length for adjusting the shift amount of the bit shifter 128 is calculated by the adder 124 and the latch 126.

The data output from the bit shifter 128 is packed into a 16-bit width in the form of FIFO01.
Written in 30. The timing of writing to the FIFO0130 is the time when the bit shifter 128 is packed into 16 bits, and therefore the time when the carry of the accumulated value of the bit length is output from the latch 126.
It is used as a write signal for IF0130.

In parallel with the above operation, the counter 120 counts the input image data, the decoder 132 detects the end of the input image data from the count value of the counter 120, and outputs the detection result to the logic circuit 136. Output.
The logic circuit 136 is a logic circuit for controlling the count-up of the counter 134 for counting the number of times of writing data to the FIFO 0130, and every time the write signal of the FIFO 0130 is output until the end of the input image data is detected. It is configured to count up. Therefore, the counter 134 counts the number of writings to the FIFO 0130, that is, the number of writings until the end of the input image data is reached. This write count is loaded into the down counter 138, and the logic circuit 140 is set to F
When the writing to the IF0130 is completed, the down count for the number of writings is started. When the result of the down count becomes 0, the decoder 142 outputs the FIFO0 read completion signal.

Next, the operation of the switches 150 and 152 and thereafter will be described. The data output from the FIFO0130A to 130H is transmitted through the switch 150 to the FIFO0154.
To the FIF output from the decoders 142A to 142H.
The 0 read completion signal is input to the switch control circuit 158 via the switch 152 for each phase.
The switch control circuit 158 includes decoders 142A to 142A.
1 in response to the FIFO memory read completion signal from H
Switch 1 each time a read completion signal of one phase is detected
50 and 152 are switched to the next phase.

[0014]

In the conventional example, the variable-length code storage FIFO memories 130A to 130H are classified into phases.
The number of writes to the variable length code storage FIFO memory 130A-1
Since the reading of 30H is controlled, there are the following problems. That is, first, the FIFs connected on the single-phase transmission path
The time required for writing to the O memory 154 becomes long, and it becomes impossible to follow it when the data rate on the single-phase transmission path side is high. Secondly, the circuit configuration of the logic circuit part including the counter for counting the number of times of writing becomes very large.

An object of the present invention is to provide an encoding device and a serialization device that solve such a problem.

[0016]

An encoding device according to the present invention is an encoding device for performing variable length encoding of information which has been polyphase-divided and outputting it on a single path. For each phase, variable length coding means, code buffer means for temporarily storing the code output of the variable length coding means, and control information storage means for storing control information indicating the coding completion of the variable length coding means. A processing means having Further, there is provided selection means for referencing the control information stored in the control information storage means of the processing means of each phase to time-series the storage code of the code buffer means of the processing means of the respective phase.

The serializing apparatus according to the present invention comprises N (N is 2 or more) parallel processing means, selecting means for selecting processed data of the N parallel processing means, and control for controlling the selecting means. And a processing completion storing means for storing a processing completion signal indicating the end of the parallel processing, wherein each of the N parallel processing means includes a buffer means for temporarily storing processed data. It is equipped with. Further, the control means sequentially refers to the processing completion storage means in each of the N parallel processing means, and selects the processed data of the next parallel processing means to the selection means in response to the detection of the processing completion signal. Let

[0018]

By the above means, the parallel-processed variable length codes of the respective phases can be put together on the single-phase transmission line without a time gap.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 3 shows a schematic block diagram of an embodiment of the present invention. Also in this embodiment, similarly to the conventional example (FIG. 1),
The image information is divided into eight phases, which are subjected to variable length coding in parallel by a processing circuit having the same configuration, and then combined into one phase.

That is, each image signal divided into eight phases A to H is input to eight input terminals 10 (10A to 10H),
A clock signal synchronized with the image data input to the input terminal 10 is input to the input terminal 12. The eight parallel processing circuits 14 (14A to 14H) have exactly the same circuit configuration,
The details of the internal circuit are shown only for the processing circuit 14A.

In the processing circuit 14A, 20 is a counter for counting the number of input image data, 22 is a B2 coding circuit, 24 is a 3-bit adder, 26 is a latch for storing the addition value of the previous clock, and 28 is a bit. Shifter, 30 is B
2 is a FIFO memory for temporarily storing two codes, 32 is a decoder for detecting the end of the input image data from the output value of the counter 20, and 34 is a FIFO memory for temporarily storing the detection output (1 bit) of the decoder 32.

Similar to the conventional example, each processing circuit 14A to 14A
When H and its internal circuit are distinguished from each other or in particular, the symbols A to H for identifying the phase are added to each symbol. Other than that, each circuit is described without adding AH.

50 is the FI of each processing circuit 14A-114H.
A switch that selects the output of the FO memory 30, a switch 52 that selects the output of the FIFO memory 34 of each processing circuit 14A to 14H, a 54 FIFO memory that temporarily stores the data from the switch 50 for output, and a 56 An output terminal for outputting image data to the outside, 58 is a switch 5
A 3-bit counter activated by the output of 2 and 60 is a switch control circuit for switching the switches 50 and 52 according to the count value of the counter 58.

The switches 50 and 52 are interlocked with each other. That is, the switch 50 is the processing circuit 14A (FIFO of the processing circuit 14A).
When memory 30A) is selected, switch 52
Selects the same processing circuit 14A (the output of the FIFO memory 34A), and the switch 50 (the FI of the processing circuit 14C).
When the FO memory 30C) is selected, the switch 52 controls the same processing circuit 14C (the FIFO memory 42C of the same processing circuit 14C).
Output) is selected.

FIG. 4 is a block diagram showing the overall schematic configuration of an image coding apparatus incorporating this embodiment shown in FIG. An analog luminance signal (or an analog G signal in RGB format) is input to the input terminal 210, an analog Pb signal (or an analog B signal) is input to the input terminal 212, and the input terminal 2
An analog Pr signal (or analog R signal) is input to 14. The A / D converters 216, 218, 220 convert the analog signals from the input terminals 210, 212, 214 into digital signals, respectively. The encoding circuit 222 is A
It consists of eight similar circuits that encode the outputs of the / D converters 216, 218, 220 in parallel in eight phases, with a discrete cosine transform (DCT) circuit 224, a B2 coding circuit 226 and a FIFO memory 228 for each phase. It is equipped with. The 8-phase outputs of the encoding circuit 222 are serialized by the buffer 230 and output from the output terminal 232.

The B2 encoding circuit 226 corresponds to the B2 encoding circuit 22 of FIG. 3, the FIFO memory 228 corresponds to the FIFO memory 30 of FIG. 3, and the buffer 230 corresponds to the FIFO memory 54 of FIG.

The operation of this embodiment will be described.

Next, the flow of data in this embodiment will be described with reference to FIG. A / D converters 216, 218, 220
Converts the analog signals from the input terminals 210, 212 and 214 into digital signals, and the digital data is divided into eight phases as shown in FIG. 2 and applied to the encoding circuit 222 of each phase. It

In each coding circuit 222, the DCT circuit 224 first performs a discrete cosine transform on the image data. The outputs of the 8-phase DCT circuit 224 are input to the input terminals 10A to 10H of FIG. 3, respectively. Each signal processing circuit 14 of FIG.
In (14A to 14H), the B2 encoding circuit 22 outputs the image data from the input terminal 10 (10A to 10H) to B2.
Convert to code. The B2 coding circuit 22 outputs a 16-bit B2 code itself and 3-bit code length data. The B2 code itself is input to the bit shifter 28 while being aligned on the 16-bit wide bus by the accumulated value of the bit length of the B2 code. Therefore, the B2 code having a bit length shorter than 16 bits is output by stacking the B2 codes output later until it becomes 16 bits inside the bit shifter 28. The cumulative value of the bit length for adjusting the shift amount of the bit shifter 28 is the adder 2
4 and latch 26.

The data output from the bit shifter 28 is packed in a 16-bit width in the form of the FIFO030.
Written in. The timing of writing to the FIFO 030 is the time when the bit shifter 28 is filled with 16 bits, and therefore the time when the carry of the accumulated value of the bit length is output from the latch 26.
Used as a 0 write signal.

In parallel with the above operation, the counter 20 counts the input image data, the decoder 32 detects the end of the input image data from the count value of the counter 20, and the detection result is stored in the FIFO memory 34. Output.
The detection result of the decoder 32 indicates the completion of the B2 encoding process.

At the stage of input to the input terminal 10, each data has a fixed length, but becomes a variable length by the B2 code conversion, and a data vacancy occurs at some clocks. Therefore, if the switch 50 is simply switched when data is transferred from the FIFO memories 30A to 30H to the FIFO memory 54, an unnecessary data portion due to a vacancy of data is also transmitted, and the entire data transmission amount is increased. It will increase.

In order to prevent this phenomenon, in this embodiment,
The B2 encoding process completion signal is stored in the FIFO memory 34, and thereby the switching of the switch 50 is controlled.

FIG. 5 shows each of the phases # 0 to # 7 (the above-mentioned phases A to H).
Corresponding to. 2) shows an example of a code and a B2 encoding processing completion signal for each of the above). The code is shown as CODE, B
The 2-coding process complete signal is shown as EOR.

In this embodiment, B2-encoded digital image data data is expressed in a 16-bit width, and a 1-bit B2-encoding processing completion signal is generated in parallel with this data. As shown in FIG. 5, the B2 encoding process completion signal is a positive signal delayed by one clock from the time when the last valid B2 code is output to the data bus. That is, the shaded data is invalid data and is output at the start timing of this invalid data.

The bit shifter 28 outputs the B2 code at the timing shown in FIG.
Stores the same amount of data, except that the basic data length is 16 bits and 1 bit, so that the B2 coded signal of the same phase and the B2 coded processing completion signal can be processed at the same timing in the processing after 52. Available FIFO memory 3
0 and 34 are used, and the write and read timings are aligned.

The B2 code output from the FIFO memory 30 is transferred to the FIFO memory 54 by a switch 50
The B2 coding completion signal output from the IFO memory 34 is input to the counter 58 via the switch 52 in order of each phase.

The switching of the switches 50 and 52 will be described in detail. In FIG. 5, the B2 code stored in the FIFO memory 30 is illustrated as CODE in time series. # 0 to # 7 in FIG. 5 indicate eight divided phases.
For example, the B2 code illustrated as the CODE of the phase # 0 is stored in the FIFO memory 30A. Similarly, phase #
The B2 code shown as a CODE of 1 is stored in the FIFO memory 30B.

In FIG. 5, EOR is a B2 coding processing completion signal and is stored in the FIFO memories 34A to 34H of FIG. For example, a B2 coding completion signal, shown as EOR for phase # 0, is stored in the FIFO memory 34A. Similarly, B illustrated as EOR for Phase # 1
The 2-coding completion signal is stored in the FIFO memory 34B.

FIG. 6 shows the B2 code of each phase shown in FIG. 5 after being serialized according to this embodiment. B in this order
Two codes are stored in the FIFO memory 54. The reference numeral attached to each data corresponds to the reference numeral attached in FIG. For example, a number identifying a phase and a serial number of the data within the phase are added to each data.

The switches 50 and 52 are first connected to the signal processing circuit 14A, and the FIFO memories 30A and 34, respectively.
A is selected. B2 code for phase # 0 is switch 50
Are sequentially written in the FIFO memory 54 via the switch, and in parallel with this, the B2 encoding process completion signal of the phase # 0 is applied to the enable terminal of the counter 58 via the switch 52. As indicated by EOR in FIG. 5, since the B2 code is valid until the B2 coding completion signal becomes positive, the switches 50 and 52 continue to be connected to the same phase. When the B2 encoding processing completion signal becomes a positive signal, the force counter 58 counts up by 1.

The switch control circuit 60 includes the signal processing circuits 14A, ... Or 1 for the phase corresponding to the value held by the counter 58.
The switches 50 and 52 are switched so as to select 4H. In this embodiment, the switches 50 and 52 are switched to the next phase. The counter 58 has 3 bits because the number of phase divisions is 8. The counter 58 becomes a loop counter in order from phase # 0 to phase # 1, phase # 1 to phase # 2, phase # 2 to phase # 3, ..., Phase # 7 to phase #.
Cycles to zero.

Therefore, after the B2 code of phase # 0 is written in the FIFO memory 54, the B2 code of phase # 1 is FI.
The B2 code of the phase # 2 is written into the FO memory 54 by the positive B2 encoding processing completion signal of the phase # 1 and is transferred to the FIFO.
It is written in the memory 54. Thereafter, in the same manner, the B2 code of the phase # 7 is written in the FIFO memory 54 and the phase # 7 is written.
B of the next phase # 0 by the positive B2 encoding completion signal of
The two codes are written in the FIFO memory 54.

With the above logic, the switch 50 of FIG.
By operating 52, the unnecessary data portion indicated by the hatched portion in FIG. 5 is prevented from being applied to the FIFO memory 54. As a result, the valid B from the FIFO memory 54 is
Only two code strings are output.

In this embodiment, since the number of divided phases of the image signal is a power of 2, the counter 58 and the switch control circuit 60 may be configured as a loop counter, so that the control becomes very simple. Therefore, the peripheral circuit configuration can be realized with a very simple structure. Further, since the B2 encoding processing completion signal is delayed by one clock from the time when the last valid B2 code is output to the data bus,
The output serial data string can be completely filled with a valid B2 code without a gap of one clock.

Although the B2 code is used as an example of the variable length code in the above embodiment, all variable length codes capable of detecting completion of variable length coding from the code length of the variable length code regardless of the maximum code length of the variable length code. With respect to, the present invention can be applied.

In the above embodiment, an example in which the image signal is divided into eight phases has been described, but it is clear that the present invention is not limited to this number of divided phases.

[0049]

As can be easily understood from the above description, according to the present invention, the variable length codes of the phases divided in parallel can be efficiently serialized in one line without a gap. The time required for the control can be short. Further, since it can be realized by a very simple circuit, it is very effective in terms of cost and circuit scale.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a conventional example.

FIG. 2 is a diagram showing a division example in which an image signal is divided into eight phases when viewed on a monitor screen.

FIG. 3 is a schematic block diagram of an embodiment of the present invention.

FIG. 4 is a schematic configuration block diagram of an image encoding device incorporating this embodiment.

FIG. 5 is a timing chart of a B2 code string and a B2 coding processing completion signal in the present embodiment.

FIG. 6 is a B2 code string after serialization in this embodiment.

[Explanation of symbols]

10A to 10H: image input terminal 12: clock input terminal 14A to 14H: processing circuit 20: counter 2
2: B2 coding circuit 24: 3-bit adder 26:
Latch 28: Bit shifter 30: FIFO memory 32: Decoder 34: FIFO memory 50: Switch 52: Switch 54: FIFO memory 56: Output terminal 58: 3
Bit counter 60: Switch control circuit 110A to 110H: Image input terminal 112: Clock input terminal 114A to 114H: Processing circuit 120: Counter 122: B2 coding circuit 124: 3-bit adder 126: Latch 128: Bit shifter 1
30: FIFO memory 132: Decoder 134: Counter 136: Logic circuit 138: Down counter 140: Logic circuit 142: Decoder 150, 15
2: Switch 154: FIFO memory 156: Output terminal 158: Switch control circuit 210, 212, 214: Input terminal 216, 218,
220: A / D converter 222: Encoding circuit 224: Discrete cosine conversion circuit
226: B2 encoding circuit 228: FIFO memory
230: buffer 232: output terminal

Claims (2)

[Claims] 1. A variable-length code for polyphase-divided information,
A coding device for outputting to a single path, comprising: variable length coding means, code buffer means for temporarily storing the code output of the variable length coding means, and control for indicating the coding completion of the variable length coding means. By referring to the processing means of each phase having control information storage means for storing information and the control information stored in the control information storage means of the processing means of each phase, the code of the processing means of each phase
An encoding device comprising: a selection unit for time-sequencing the storage code of the buffer unit. 2. A serialization device comprising N (N is 2 or more) parallel processing means, selection means for selecting processed data of the N parallel processing means, and control means for controlling the selection means. Wherein each of the N parallel processing means comprises a buffer means for temporarily storing processed data and a processing completion storage means for storing a processing completion signal indicating the end of the parallel processing. Is to sequentially refer to the processing completion storing means in each of the N parallel processing means, and to cause the selecting means to select the processed data of the next parallel processing means in response to the detection of the processing completion signal. Serializer.