JPH07106985A - Error correcting device - Google Patents

Abstract

PURPOSE:To shorten the product sum calculating time for correction of syndromes, erasures, errors, etc. CONSTITUTION:An adder 12 adds together the data which are selected by the latches 9 and 11 and outputs these data to the RAM 14a and 14b. These RAM 14a and 14b function to temporarily store the data under calculation and to output them to both latches 9 and 11 when various types of product sum calculations are periodically carried out for correction of syndromes, erasures, errors, etc. Thus the writing and reading addresses of both RAM 14a and 14b are independently controlled by a RAM controller 14c. Then two data to be added together and stored in the RAM 14a and 14b are read out by the reading addresses independent from the writing addresses under the control of the RAM controller 14c and latched by the latches 9 and 11. These latched data are sent to the adder 12 at a time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device for error correcting a Reed-Solomon code, and particularly an error suitable for reproducing an audio signal recorded on a DCC (digital compact cassette) or an MD (mini disk). Correction device

[0002]

2. Description of the Related Art Generally, a DCC main track or MD
A Reed-Solomon (RS) code in the product code format of a C1 series mainly for random error correction and a C2 series mainly for burst error correction is recorded in the. Also, D
In CC, an auxiliary track is provided in addition to the main track, and a single Reed-Solomon code of only the C1 series is recorded on this auxiliary track.

In this type of error correction device, various product-sum operations are periodically performed in order to perform syndrome correction, erasure correction, error correction, etc. Further, for example, in the case of syndrome data product operation, It is performed by once converting into an exponent and adding this exponent.

FIG. 7 shows a product-sum operation circuit in a conventional error correction device, and FIG. 8 is a timing chart for explaining its operation. In FIG. 7, data to be added is latched in the latch (A) 9 and the latch (B) 11,
The data read from the latches 9 and 11 are added by the adder 12. The result of addition during the product-sum operation is register 1
4 and the data stored in the register 14 are selectively latched by the latches 9 and 11 for the next multiply-accumulate operation. Further, the product-sum operation result by the adder 12 is restored from the exponent by the i-α conversion circuit 15 in the correction circuit and stored in the register 19 for the correction operation.

The operation timing of this circuit will be described with reference to FIG. 8. Since two data to be added cannot be read from the register 14, for example, the latch read signal rises (time tp1) and falls (time tp1). At tp2), the data is read from the latches 9 and 11, respectively, and is stored in the register 19 at the time point tq when the processing of the adder 12 and the i-α conversion circuit 15 is performed.

[0006]

However, in the conventional error correction device, the two data to be added cannot be read from the register 14 and different from the latches 9 and 11 in which the data to be added is latched. Time point tp1, t
Since the reading is performed at p2, there is a problem that the calculation time for syndrome correction, erasure correction, error correction, etc. becomes long.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide an error correction device capable of reducing the product-sum operation time for performing syndrome correction, erasure correction, error correction and the like.

[0008]

In order to achieve the above object, the present invention is provided with first and second storage means for respectively storing two pieces of data to be added in the next product-sum operation. Two pieces of data to be added are simultaneously read from the second storage means to perform the next product-sum operation. That is, according to the present invention, first and second latch means for respectively latching two pieces of data to be added when various product-sum operations for performing syndrome correction, erasure correction, error correction, etc. are periodically performed. And the first
And an addition means for adding each data read from the second latch means, and first and second storages for respectively storing two addition target data in the next product-sum operation added by the addition means. Means and a control means for simultaneously reading out two pieces of data to be added from the first and second storage means, causing the first and second latch means to respectively latch, and causing the addition means to output at the same time. A correction device is provided.

[0009]

In the present invention, the first and second storage means 2
Data of one addition target are simultaneously read and latched by the first and second latch means, respectively, and simultaneously read from the first and second latch means and output to the adder. Therefore, unlike the conventional example, the reading from the first and second latch means is not performed at different points in time, so that the product-sum operation time for performing syndrome correction, erasure correction, error correction, etc. can be shortened. .

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of the error correction device according to the present invention, FIG. 2 is a timing chart for explaining the operation of sum of products operation of the error correction device of FIG. 1, and FIG.
Is a flow chart for explaining a routine for correcting the C1 sequence of the Reed-Solomon code, FIG. 4 is a flow chart for explaining a routine for correcting the C2 sequence of the Reed-Solomon code, and FIG. 5 is a flow chart of the C2 sequence correction routine of FIG. 6 is a flowchart for explaining the erasure routine, and FIG. 6 is a flowchart for explaining the syndrome correction routine of the erasure routine of FIG.

First, the circuit shown in FIG. 1 will be briefly described. The circuits 2 to 20 are configured to correct the error of the signal on the data bus 1. In particular, the circuits 2 to 7 calculate the syndrome, the circuits 9 to 13 and 14a to 14c perform the sum of products operation, and the circuits 15 to 20 performs a correction operation and outputs the corrected data onto the data bus 1. In addition, this error correction circuit 2
20 is controlled by a RAM address output circuit 24 and an instruction circuit 25.

The flag location setting circuit 2 is a circuit for evaluating a C1 error flag for erasure correction at the time of reproduction. The flag location setting circuit 2 reads the C1 error flag once for 24 series of C2, and detects the 2-word error and 3-word error of C1. Detect position and number. The circuit 2 also generates and outputs a RAM address for reading the error flag.

The parity location setting circuit 3 outputs the parity position to the location selection circuit 4 according to each of the main track series C1 and C2 and the auxiliary track series AUXC1 in order to calculate the parity by using erasure correction during recording. To do. The location selection circuit 4 is
The error position from the flag location setting circuit 2 is selected in the reproduction mode, and the parity position from the parity location setting circuit 3 is selected in the recording mode and output to the data latches 9 and 11. RAM for the latch 9
(A) The data stored in 14a is latched.

The syndrome check circuit 5 is a RAM
The data from (not shown) is received, and four syndromes S0 to S3 are calculated in the C1 series as described later,
In the C2 series, six syndromes S0 to S5 are calculated and output to the syndrome selection circuit 6. The syndrome selection circuit 6 is a table for selecting the syndrome from the syndrome check circuit 5 and the output from the register 19 or 16 and converting it into an exponent α-i (AI) conversion R
Output to OM7.

The syndrome which has been α-i converted by the α-i conversion ROM 7 is latched in the latch 11, and the latch 11
Further, the data stored in the RAM (B) 14b is latched. The latches 9 and 11 are the syndromes converted into exponents by the α-i conversion ROM 7, the data selected by the location selection circuit 4, and the RAMs 14a and 14b.
The data stored in 1 is selectively latched and output to the adder 12, and the corrected data symbol address latch circuit 10 stores the error position obtained by the operation when executing the error correction, and the RAM address Output to the output circuit 24.

The adder 12 adds the data selected by the latches 9 and 11, but the instruction in the case of the addition of the exponent part of α is multiplication. The register input / output selection circuit 13 outputs α-i by the output of the adder 12 or the ROM 7.
Select the converted syndrome and RAM14 in the latter stage
a and 14b. The RAMs 14a and 14b are used to temporarily store data in the middle of calculation and output it to the latches 9 and 11 when various product-sum calculations for performing syndrome correction, erasure correction, error correction, etc. are periodically performed. The write and read addresses are independently controlled by the RAM controller 14c.

The i-α (IA) conversion circuit 15 includes an adder 12
I-α conversion is performed on the output of the above, and this data is added to the data stored in the register 19 by the exclusive OR circuit 17 and stored again in the register 19. Register 16
When the value of "X" is input in order to obtain the solution "Z" of Z2 + Z + X = 0 at the time of correcting two words, it is converted into the value of "Z", stored and output. The corrected data output circuit 20 outputs corrected data obtained by the exclusive OR circuit 18 from the data from the IA conversion circuit 15 and the error data on the data bus 1 onto the data bus 1.

The RAM address output circuit 24 is, for example, D
In the case of CC, an IO controller (IOCONT.V) that generates and outputs a main data C1 series RAM address, a main data C1 series error flag RAM address, a main data C2 series RAM address, and the like.
And a buffer (ERRFGBUF.V) for generating and outputting error flag data of each series.

Next, the instruction circuit 25 will be described in detail. First, the clock generator (CLOCK
GEN) generates various clocks used inside the device from each input signal. Instruction counter (INSTCNT) is C1, C2, AUXC1 (DCC
Is a 10-bit counter for syndrome calculation of the auxiliary track), C1 error flag evaluation, and C1BNG flag write instruction, and the output of this counter is the address of the instruction ROM (INSTROM). One step of this instruction is from the rising edge of the clock to the falling edge,
Count up by the clock. Further, the jump of this instruction is performed by loading the following jump destination address.

The instruction ROM outputs 16-bit data with the count value output from the instruction counter (INSTCNT) as an address, and this data determines the processing operation in each step of the instruction. Instruction selector (IN
STSEL is a type of processing (syndrome operation, 16-bit data output from the instruction ROM).
Output destinations are sorted according to error flag processing and BNG flag writing), and this output is output at clock timing. Further, this selector outputs a signal for stopping the instruction when accessing the RAM.

The load address generator (LOADAD) reads the data in which the count value output from the instruction counter (INSTCNT) is latched, and when this data is an address for jumping, determines the jump destination address according to each input condition. Output to the instruction counter (INSTCNT).

Here, although the instruction of the syndrome calculation and the instruction of the correction process are in progress at the same time, since the RAM cannot be accessed at the same time, the instruction controller (INSTCONT) monitors the address so that the RAM access does not collide. It controls the instruction counter (INSTCNT). Further, although the syndrome calculation and the correction process are performed at the same time, since the sequence being corrected is the syndrome one sequence before the syndrome calculation that is performed at the same time, the flag controller (FLGCONT) stores information and flags related to the syndrome calculation. , This information and flags are used in the correction process.

Next, referring to FIG. 2, the product-sum operation circuits 9 to 1
The operations of 3 and 14a to 14c will be described. RAM14a,
The two pieces of data to be added stored in 14b are RAM
Under the control of the controller 14c, the read address independent of the write address is read, latched by the latches 9 and 11, respectively, and simultaneously read at the rising edge of the latch read signal (time point tp).
Is added by. Note that the addition result during the product-sum calculation by the adder 12 is stored in the RAM 14a, 1 for the next product-sum calculation.
4b, and the product-sum operation result of the adder 12 is stored in the register 19 at the time point tq when the processing of the i-α conversion circuit 15 and the like is performed. Therefore, since the latches 9 and 11 in which the data to be added are latched are read out at the same time (time point tp), it is possible to shorten the product-sum operation time for performing syndrome correction, erasure correction, error correction, and the like. it can.

Next, the C1 correction process will be described with reference to FIG. In the case of DCC, this C1 correction process is performed during reproduction from the main track and the auxiliary track. Further, in the flowcharts of FIG. 2 and subsequent figures, Err
Indicates an error, and 1W and 2W indicate 1 word and 2 words, respectively. When the C1 correction process is started (step 101), first, the syndromes S0 to S3 are checked by the expression [C1] shown in the upper part of the following expression (expression 1) (step 102), and then the expression (expression 2) is given. The syndromes S0 to S3 are converted from α to i and stored in the latch 11 (step 103).

[0025]

## EQU1 ## [C1] S0 = W0 + W1 + W2 + ... + W23 S1 = α23W0 + α22W1 + α21W2 + ・ ・ ・ ・ ・ + W23 S2 = α46W0 + α44W1 + α42W2 + ・ ・ ・ ・ ・ + W23 S3 = α69W0 + α66W1 + α63W2 + ... + W23 + 2 W0 + W1 + W2 + ... + W31 S1 = α31 W0 + α30 W1 + α29 W2 + ・ ・ ・ ・ ・ + W31 S2 = α62 W0 + α60 W1 + α58 W2 + ・ ・ ・ ・ ・ + W31 S3 = α93 W0 + α90 W1 + α87 W2 + = + 124 W31 + 4 W2 + ... + W31 S5 = α155 W0 + α150 W1 + α145 W2 + ... + W31

[0026]

## EQU00002 ## C1: S0 S1 S2 S3 C2: S0 S1 S2 S3 S4 S5

Next, it is judged whether or not all the syndromes S0 to S3 are "0" (step 104). If YES, all of the C1 error flags F0, F1 and F2 are "0".
Is written (step 105), the block address is incremented by 1 (step 106), and if all blocks are not completed, the process returns to step 102, and if completed, the process proceeds to the C2 correction process shown in FIG. 4 (step 107). ).

On the other hand, if all of the syndromes S0 to S3 are not "0" in step 104, first, the modified syndromes σ1 to σ3 for detecting the one-word error are calculated based on the following equation (Equation 3) ( Step 10
8) Then, it is determined by the following equation (Equation 4) whether or not there is a one-word error (step 109).

[0029]

Σ1 = S12 + S0 * S2 σ2 = S22 + S1 * S3 σ3 = S1 * S2 + S0 * S3

[0030]

Σ1 + σ2 + σ3 = 0 1 word error σ1 + σ2 + σ3 ≠ 0 1 word error or more

In the case of a 1-word error, 1-word correction is performed based on the following equation (Equation 5) and the corrected data is written (step 110). Then, based on Table 1, the C1 error flag F0 is set to "1". Write "(Step 1
11). Next, the block address is incremented by 1 (step 112) and the process proceeds to step 107.

[0032]

[Equation 5] [1 word correction] Error position: Xi = S1 / S0 Error value: Ei = S0 correction: Wi = S0 + Di (Di ... error data)

[0033]

[Table 1]

On the other hand, if the one-word error is not found in step 109, X1, X2, ψ1 to ψ3 for detecting the two-word error are calculated by the following equation (Equation 6) (step 113), and then the following equation It is determined by (Equation 7) whether or not there is a 2-word error (step 114).

[0035]

[Equation 6]

[0036]

Ψ1 + ψ2 + ψ3 = 0 2 word error ψ1 + ψ2 + ψ3 ≠ 0 2 word error or more

In the case of a 2-word error, 2-word correction is performed based on the following equation (Equation 8) (step 1
15) Corrected data Wi, W by the following equation (Equation 9)
j is written (step 116), and then "1" is written in the C1 error flags F0 and F1 as shown in Table 1 (step 117). Next, the block address is incremented by 1 (step 118), and step 107
Proceed to.

[0038]

[Equation 8]

[0039]

[Expression 9] [Wi, Wj correction] From S0 = Ei + Ej S1 = Xi * Ei + Xj * Ej Xj * S0 + S1 = (Xi + Xj) * Ej Ej = (Xj * S0 + S1) / C1 Ej = S0 + Ei Wi = Ei + DjDj

If no 2-word error occurs in step 114, "1" is written in both C1 error flags F0, F1, and F2 as shown in Table 1 (step 1
19), then the block address is incremented by 1 (step 120) and the routine proceeds to step 107.

Next, the C2 correction process will be described with reference to FIGS. The C2 correction process starts after the C1 correction is performed for all blocks (step 121),
First, the syndromes S0 to S5 are checked by the lower stage [C2] of the above equation (Equation 1) (step 122), and then
The syndromes S0 to S5 shown in the lower part of the above equation (Formula 2) are set to
→ i-convert and store in register 8 (step 12
3). Next, the C1 error flag is read and the number N (E) of error flags and the error position X are calculated by the following equation (Equation 10).
i is detected (step 124), and the following equation (Equation 11)
Perform the pre-calculation as shown in.

[0042]

[Formula 10] [C1 Flag Calculate] Read: C1 Flag Location Count: C1 Flag Number Resist: C1 Flag Location X1, X2, X3, X
4, X5, X6

[0043]

X1 + X2 = B1 X1 * X2 = B2 B1 + X3 = C1 B1 * X3 + B2 = C2 B2 * X3 = C3 C1 + X4 = D1 C1 * X4 + C2 = D2 C2 * X4 + C3 = D3 C3 * X1 * D4 = D4 = D4 X5 + D2 = E2 D2 * X5 + D3 = E3 D3 * X5 + D4 = E4 D4 * X5 = E5 (X1 + X6) × (X2 + X6) (X3 + X6) (X4 + X6) (X5 + X6) = X3 + X5) (X3 + X5) (X2 + X5) (X3 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X1 + X4) (X2 + X4) (X3 + X4) = I4 (X1 + X3) (X2 + X3) = I3 (X1 + X2) = I2

Then, it is determined whether the number of errors is "0" by determining whether all the syndromes S0 to S5 are "0" (step 126).
2 “0” is written to the error flags F0 and F1 (step 127), the block address is incremented by 1 (step 128), and if all blocks (BLK) are not completed, the process returns to step 122, and if completed, Ends the C2 correction process (step 129).

On the other hand, when all the syndromes S0 to S5 are not "0" in step 126, the modified syndromes σ1 to σ3 for detecting the one-word error are calculated based on the above equation (Equation 3) (step 131). ), And then it is determined by the above equation (Equation 4) whether or not there is a one-word error (step 132). Then, in the case of a 1-word error, 1-word correction is performed based on the above equation (Equation 5) to write the corrected data (step 133), and then "0" is written to the C2 error flags F0 and F1 (step 1).
34). Then, the block address is incremented by 1 (step 135) and the process proceeds to step 129.

On the other hand, if the one-word error is not found in step 132, the modified syndromes X1, X2, ψ1 for detecting the two-word error by the above equation (Equation 6).
˜ψ3 is calculated (step 136), and then it is determined by the above equation (Equation 7) whether or not there is a 2-word error (step 137).

In the case of a 2-word error, 2-word correction is performed based on the above equation (Equation 8) (step 1
38) Write the correction data Wi according to the above equation (Equation 9) (step 139), and then write C2 error flags F0, F
Write "0" in 1 (step 140). Then, the block address is incremented by 1 (step 14
1), the process proceeds to step 129. If it is determined in step 137 that there is no two-word error, the process proceeds to the erasure routine shown in FIG.

Next, the erasure routine will be described. First, it is determined whether or not the number of C1 error flags F1 is "0" (step 144), and if NO, it is determined whether or not the number of C1 error flags F1 is 5 or less (step 14).
5) If 5 or less, it is determined whether or not 5 (step 146). If the number of C1 error flags F1 is not 5, the syndrome correction routine shown in detail in FIG. 6 is executed. On the other hand, if the number of C1 error flags F1 is 5, the erasure of N = 5-1 is performed by the following equation (Equations 12-15). Execute (Step 14
7) Then, the block address is incremented by 1 (step 148) and the process returns to step 121.

[0049]

[5 Erasure, Y5] T4 = S4 + D1 * S3 + D2 * S2 + D3 * S1 + D4 * S0 Y5 = T4 / I5 [Syndrome correction] S0 + Y5 → S0 S1 + Y5 * X5 → S1 S2 + Y5 * X52 → S3X5 + S3S5 + S3

[0050]

[4 Erasure, Y4] T3 = S3 + C1 * S2 + C2 * S1 + C3 * S0 Y4 = T3 / I4 [Syndrome correction] S0 + Y4 → S0 S1 + Y4 * X4 → S1 S2 + Y4 * X42 → S2

[0051]

[3 Erasure, Y3] T2 = S2 + B1 * S1 + B2 * S0 Y3 = T2 / I3 [Syndrome correction] S0 + Y3 → S0 S1 + Y3 * X3 → S1

[0052]

[Equation 15] [2Erasure, Y2] [1Erasure, Y1] T1 = S1 + X1 * S0 Y2 = T1 / I2 Y1 = S0 + Y2

If the number of C1 error flags F1 is "0" in step 144, "1" is written in the C2 error flag F0 (step 149), and then the block address is incremented by 1 (step 14).
7) and returns to step 121. If the number of C1 error flags F1 is not 5 or less in step 145, the process branches to step 152 and below.

If the number of C1 error flags F2 is "0" in step 152, "1" is written in the C2 error flag F1 (step 153), and then the block address is incremented by 1 (step 154).
Return to step 121. If the number of C1 error flags F2 is 3 or less in step 152, the syndrome correction routine shown in detail in FIG. 6 is executed, and if the number of C2 error flags F2 is 5 or less in step 156, N = The N erasure of 5 to 1 is executed, the block address is incremented by 1 (step 158), and the process returns to step 121.

If the number of C2 error flags F2 is not 6 in step 159, the C2 error flag F2
"1" is written in 1 (step 160), and then the block address is incremented by 1 (step 16).
1) and returns to step 121. If the number of C2 error flags F2 is 6 in step 162, then
~ N (15) and N (6) are used to execute N erasure of N = 6 to 1 (step 163), the block address is incremented by 1 (step 164), and the process returns to step 121.

[0056]

[6 Erasure, Y6] T5 = S5 + E1 * S4 + E2 * S3 + E3 * S2 + E4 * S1 + E5 * S0 Y6 = T5 / I6 [Syndrome modification] S0 + Y6 → S0 S1 + Y6 * S6 → S1 S2 + Y6 * S6 → S2 + Y6 * S6 S4 + Y6 * X64-> S4 (Similarly, the erasures of N = 5, 4, 3, 2, 1 are executed in the following.)

Next, the syndrome correction routine will be described with reference to FIG. First, the syndrome correction is performed on, for example, six locations i = 0 to 5 (step 300), and then the correction syndrome Sm is "0".
It is determined whether or not (step 301), and if Sm = 0, the erasure process is performed N times (step 302).
That is, in this embodiment, when the syndrome is corrected, it is determined whether or not the corrected syndrome Sm is "0" to increase the number of error position checks and reduce the erroneous correction.

On the other hand, when i = 1 or 2, the modified syndromes σ1 to σ3 for detecting a 1-word error are calculated based on the equation 3 (step 303 → 305), and then the 1-word error is obtained by the equation 4. It is determined whether or not (step 306), the process proceeds to step 307 and below if YES, and branches to step 320 and below if NO.
Further, it is determined whether i = 3, 4 or 5 (step 3
04), in the case of YES, the process returns to step 300, and NO
In the case of, the process proceeds to step 307 and thereafter.

In steps 307 and below, one word is corrected and the corrected data is written (steps 307, 30).
8) then correct the syndrome (step 30
9), erasure processing is performed N times (step 31
0), "0" is written in the C1 error flags F0 and F1 based on Table 1 (step 311), and then the block address is incremented by 1 (step 31).
2) Return to step 300.

In step 320 and subsequent steps, X1, X2, ψ1 to ψ for detecting a two-word error according to the equation (6).
3 is calculated (step 320), then it is discriminated whether or not there is a 2-word error by the equation 7 (step 321), and in the case of 2-word error, 2-word correction is performed (step 32).
2) Write the correction data Wi and Wj according to equation 9 (step 323). Next, Y1 and Y2 are calculated (step 324), W1 and W2 are corrected (step 325), "0" is written in the C1 error flags F0 and F1 as shown in Table 1 (step 326), and then the block address. Is incremented by 1 (step 327) and the process returns to step 300.

[0061]

As described above, according to the present invention, two pieces of data to be added are simultaneously read from the first and second storage means and latched by the first and second latch means, respectively. Since it is simultaneously read from the first and second latching means and output to the adder, the reading from the first and second latching means is not performed at a different time as in the conventional example, and therefore, the syndrome correction, It is possible to reduce the product-sum operation time for performing erasure correction, error correction, and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error correction device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of sum of products calculation of the error correction device of FIG.

FIG. 3 is a flowchart for explaining a routine for correcting a C1 sequence of Reed-Solomon code.

FIG. 4 is a flowchart for explaining a routine for correcting a C2 sequence of Reed-Solomon code.

FIG. 5 is a flowchart for explaining an erasure routine of the C2 series correction routine of FIG.

6 is a flowchart for explaining a syndrome correction routine of the erasure routine of FIG.

FIG. 7 is a block diagram showing a product-sum operation circuit of a conventional error correction device.

8 is a timing chart for explaining the operation of the sum of products operation of FIG.

[Explanation of symbols]

2 Flag location setting circuit 3 Parity location setting circuit 4 Location selection circuit 5 Syndrome check circuit 6 Syndrome selection circuit 7 α-i conversion ROM 16, 19 Register 9, 10, 11 Latch (9 and 11 constitute a latch means) 12 , 17 and 18 Adder (12 constitutes adding means) 13 Selection circuits 14a and 14b RAM (random access memory)
(14a and 14b constitute storage means) 14c RAM controller (constitutes control means together with instruction circuit 25) 15 i-α conversion circuit 24 RAM address output circuit 25 instruction circuit

Claims (1)

[Claims] 1. A first latch for latching two pieces of data to be added when various product-sum operations for performing syndrome correction, erasure correction, error correction, etc. are carried out periodically.
And a second latching means, an adding means for adding the respective data read from the first and second latching means, and 2 in the next product-sum operation added by the adding means.
First and second storage means for respectively storing data to be added, and two data to be added are simultaneously read out from the first and second storage means and respectively stored in the first and second latch means. An error correction device having a control means for latching and outputting to the adding means at the same time.