JPH07107983B2 - D / A converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a system D for requantizing an input digital signal at a sampling frequency higher than the sampling frequency and compressing the number of bits of the input digital signal to a binary level. / A
The present invention relates to a converter, and more particularly to a D / A converter when a plurality of sampling frequencies of an input digital signal exist.

[0002]

2. Description of the Related Art Due to recent advances in digital technology, D / A converters, which are digital / analog interfaces, are becoming more and more important. Particularly, recently, quantizers capable of high performance D / A conversion. Using D /
The number of A-converters is increasing.

A conventional D / A converter is shown in FIG. 7 and will be described (for example, "Radio Technology", May 1988, Issue 1).
40-143).

In this conventional example, the input signal having the sampling frequency fs is once converted into a 4-bit oversampling 17-bit signal by the digital filter unit 100, and the signal is input to the quantizer 110. . In the digital filter unit 100, an input signal is attenuated by using a digital attenuator 101, and then four times oversampling is performed through FIR digital filters 102 and 103 for two times oversampling.

The 4fs obtained as described above, that is, the number of oversampling = 4 and the signal of 17 bits is 3
It is input to the quantizer 110 operating at 2fs. In the quantizer 110, the input signal is given to the single integral type noise shaper 111, and noise shaping is performed. The quantization noise Vq1 generated by the single integral type noise shaper 111 is the double integral type noise shaper 112.
To the output of the single integral type noise shaper 111 by the adder 115 via the differentiator 113 and output. As a result, 4f input to the quantizer 110
The s, 17-bit signal is bit-compressed into 32 fs, 11-valued signals, that is, 11 signals of -5 to +5. The obtained 11-valued signal is pulse-width modulated by the PWM converter 2, and 11 kinds of pulse waves as shown in FIG. 8 are output according to the input value.

In this conventional example, in order to obtain the resolution of the pulse width from the PWM section, the oscillator 116 generates a master clock signal by using a crystal oscillator 32 × 24 = 768 times the sampling frequency fs of the input signal. There is.

[0007]

However, with the above-mentioned structure, high performance is exhibited without problems when the sampling frequency fs of the input digital signal is fixed. For example, DAT, that is, digital audio tape. The sampling frequency fs of the music signal being recorded is as follows: 48kHz, 44.1kHz, 32kHz
When the sampling frequency fs of the music signal input to the D / A converter is 48 kHz, the master clock frequency of the D / A converter is 48 kHz × 32 × 24 36. Although it becomes 864 MHz, in the case of the same fs = 44.1 kHz, the master clock frequency has to be 34.1688 MHz at 44.1 kHz × 32 × 24, and there is a problem that a peripheral circuit for this is required. .

In view of the above problems, the present invention does not require changing the sampling frequency at which the D / A converter operates even when the sampling frequency of the input digital signal changes. Is provided.

[0009]

To achieve this object, a D / A converter according to the present invention operates an input digital signal at a sampling frequency higher than the sampling frequency of the digital signal. And a converter for converting the output of the quantizer into a binary level signal having a predetermined period, and a sampling frequency of a digital signal that can be input to the quantizer is F, the oversampling number at which the quantizer operates at this time, and the oversampling number at which the quantizer operates so that the value of F × N × T is always constant, where N is the predetermined period. N and the predetermined period T are changed.

[0010]

As described above, the number N of oversamplings in which the quantizer operates and the period T of the binary signal are changed according to the sampling frequency F of the input digital signal, and F × N × Since the value of T is kept constant, it is not necessary to change the sampling frequency at which the D / A converter operates according to the sampling frequency of the input digital signal, and the peripheral circuit can be greatly simplified. .

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram of a D / A converter according to the present invention. Here, a case is shown in which digital signals at three sampling frequencies used in DAT are input. Explaining this figure, the quantizer 1 and the PWM
The converter 2 has 48, 44.1, 3 as a master clock.
28.224 MHz, which is a common multiple of 2, is given, and the quantizer 1 and P are used by using the clock select signal CSEL according to the sampling frequency of the input digital signal.
It controls the operation of the WM converter 2.

The quantizer 1 has a sampling frequency of 48 kHz.
When a digital signal of z is input, it operates with 42 times oversampling and outputs 13 values. When a digital signal with a sampling frequency of 44.1 kHz is input, it operates with 40 times oversampling and outputs 15 values. When a digital signal with a sampling frequency of 32 kHz is input, it operates with 63 times oversampling and outputs 13 values.

The PWM converter 2 has a sampling frequency of 4
Converts a digital signal into a pulse wave with a conversion period of 16 cycles (Fig. 2B) of the master clock (Fig. 2A) at 4.1kHz and 14 cycles of the master clock (Fig. 2C) at sampling frequencies of 48kHz and 32kHz. .

Thus, the sampling frequency fs of the digital signal input to the D / A converter, the oversampling number N at which the quantizer 1 operates, and the period T of the digital data input to the PWM converter 2 _The number N of oversamplings of the quantizer 1 and the period T _{N of the} digital data input to the PWM converter 2 are set according to the sampling frequency so that the product of _N , that is, the value of fs × N × T _N becomes constant. Since it is changed, it is possible to cope with each sampling frequency without changing the frequency of the master clock.

FIG. 3 is a block diagram showing a concrete embodiment of the D / A converter according to the present invention. Explaining this figure, 11 is a register, which latches the input 16-bit data by the clock signal WCK operating at the cycle of the sampling frequency fs. 12 is an adder. Reference numeral 13 is a feedback circuit having a transfer function H (z), which operates according to the sampling clock input to the terminal CK. The transfer function H (z) is as shown in equation (1).

H (z) = − 3z ⁻¹ + 3z ⁻² −z ⁻³ (1) 15 is a subtractor, which is a difference V between the input and output of the local quantizer 14.
Take out q and output it. Reference numeral 20 denotes a frequency divider, which controls a frequency division ratio by the clock select signal CSEL, divides a given master clock (here, 28.224 MHz), and generates a sampling clock for the feedback circuit 13. The clock select signal CSEL is "1" when the sampling frequency fs = 44.1 kHz and "0" when the sampling frequency fs = 48 kHz and 32 kHz. Therefore, when the clock select signal CSEL = 1, the division ratio is 16: 1 and the clock select signal CSEL =
When it is 0, the division ratio is 14: 1. A local quantizer 14 requantizes the input signal as shown in (Table 1). The output is 716 each.
The value standardized by 8,8192 is shown.

[0017]

[Table 1]

With this configuration, the adder 1
2, the local quantizer 14, the subtractor 15, and the feedback circuit 13 have the input / output relationship as shown in the equation (2) 3
The following noise shaping quantizer is constructed.

Y = X + (1-z ⁻¹ ) ⁻³ × Vq (2) Further, since the frequency division ratio is controlled by the clock select signal CSEL according to the sampling frequency fs of the input data, fs = 44.1kHz, the master clock is divided by 1/16, so the divider output is 1.76.
It becomes 4MHz, operates with 40 times oversampling against the input data, and when fs = 48kHz, 32kHz divides the master clock by 1/14, so the divider output is 2.
The frequency is 016 MHz, and the operation is performed with 42 times and 63 times oversampling, respectively.

FIG. 4 is a block diagram showing the PWM converter 2 more specifically. Reference numeral 41 is a pulse width modulator, which has a clock select signal C at the resolution of the master clock.
The pulse width modulation of the digital data N input based on SEL is performed. When the clock select signal CSEL = 1, the input digital data N shown in FIG.
It produces an output as shown at P2. In other words, the period is (8 + N) × T _M of "1" of the pulse output P1 the period of the master clock as T _M, a period of "0" of the pulse output P2 becomes _{(8-N) × T M} . Clock select signal CSEL
= 0, the cycle of inputting digital data N = 1
4 has a × T ^M, the period of "0" period of "1" of the pulse output P1 is ^{(7 + N) × T M} , the pulse output P2 becomes ^{(7-N) × T M} . A mixer 42 performs analog addition of the two input signals and outputs the result. therefore,
As shown in FIG. 5, the output of the mixer 42 has a plus side pulse waveform when the digital data N is positive and a minus side pulse waveform when the digital data N is negative. In FIG. 6, the clock select signal CSEL =
An analog output waveform corresponding to each digital data N when 1 is shown.

As described above, according to the sampling frequency of the digital data input to the D / A converter, the operation clock of the quantizer 1 and the output gradation (or the output cycle).
The frequency of the master clock can be fixed by changing the value of, for example, when this master clock is generated using a crystal oscillator, one crystal oscillator
Since it is possible to cope with the same sampling frequency, it becomes possible to greatly simplify the peripheral circuit.

The number of oversamplings, the output gray scales, or the sampling frequency of the input digital data of the quantizer 1 in the above embodiment is not limited to these values, for example, fs = 32 kHz.
Needless to say, in this case, 49 times oversampling and 17-value output may be used. Also, as the quantizer 1, the third-order noise shaping type quantizer is used in the above embodiment, but it is not limited to this, and may be, for example, a second-order or fourth-order quantizer. is there. The point is how to operate the quantizer at what frequency and how to set the output gradation.

[0023]

As described above, according to the present invention, a quantizer for bit-compressing an input digital signal by operating the input digital signal at a sampling frequency higher than the sampling frequency of the digital signal; A converter for converting a quantizer output into a binary level signal having a predetermined period, and a sampling frequency of a digital signal which can be input to the quantizer is F. At this time, the quantizer operates. When the number of oversamplings is N and the predetermined period is T, the number N of oversamplings in which the quantizer operates and the predetermined period T are changed so that the value of F × N × T is always constant. By doing so, the sampling frequency at which the D / A converter operates varies depending on the sampling frequency of the input digital signal. It has an excellent effect that the peripheral circuit can be greatly simplified, because it is not necessary.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a D / A conversion device according to the present invention.

FIG. 2 is a timing chart showing a relationship between an input of a PWM unit and a master clock.

FIG. 3 is a block diagram showing a specific example of a D / A conversion device according to the present invention.

FIG. 4 is a block diagram showing a configuration of a PWM converter 2.

FIG. 5 is a waveform diagram output from the PWM unit.

FIG. 6 is a waveform diagram output from the PWM unit.

FIG. 7 is a block diagram showing a conventional D / A conversion device.

FIG. 8 is a waveform diagram of a PWM waveform output by the PWM unit in the conventional example.

[Explanation of symbols]

 1 Quantizer 2 PWM Converter 11 Register 12 Adder 13 Feedback Circuit 14 Local Quantizer 15 Subtractor

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-2-277308 (JP, A) JP-A-2-270420 (JP, A) JP-A 63-299511 (JP, A) JP-A 64- 86706 (JP, A) JP 62-30422 (JP, A) JP 4-222110 (JP, A)

Claims (1)

[Claims] 1. A quantizer for bit-compressing an input digital signal at a sampling frequency higher than the sampling frequency of the digital signal and an output of the quantizer is converted into a binary level signal having a predetermined period. F is the sampling frequency of the digital signal input to the quantizer, and N is the oversampling number at which the quantizer operates at this time, and T is the predetermined period. A D / A converter adapted to change the predetermined period T and the oversampling number N in which the quantizer operates so that the value of × N × T is always constant.