JPH04219009A - D/A converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a method for requantizing an input digital signal at a sampling frequency higher than its sampling frequency and compressing the number of bits of the input digital signal to a binary level. /A
The present invention relates to a conversion device, and particularly relates to a D/A conversion device when there are a plurality of sampling frequencies of an input digital signal.

0002

[Background Art] With the recent advances in digital technology, D/A converters, which serve as digital/analog interfaces, have become increasingly important, and in particular, quantizers have recently become capable of high-performance D/A conversion. D/ using
The number of A conversion devices is increasing.

[0003] A conventional D/A converter is shown in FIG.
40-143).

In this conventional example, an input signal having a sampling frequency fs is first converted into a 4-times oversampled 17-bit signal by a digital filter section 100, and this signal is input to a quantizer 110. . In the digital filter section 100, an input signal is attenuated using a digital attenuator 101, and then four times oversampled is performed via FIR digital filters 102 and 103 for two times oversampling.

The 4fs signal obtained as above, that is, the number of oversampling=4, and the 17-bit signal is 3
The signal is input to a quantizer 110 operating at 2 fs. In the quantizer 110, the input signal is given to a single integral type noise shaper 111 to perform noise shaping. The quantization noise Vq1 generated by the single integral noise shaper 111 is transferred to the double integral noise shaper 112.
The signal is input to , is added to the output of the single integral noise shaper 111 by an adder 115 via a differentiator 113, and is output. As a result, the 4f input to the quantizer 110
A 17-bit signal is compressed into 32 fs, 11 values, that is, 11 signals from −5 to +5. The obtained 11-value signal is pulse width modulated by the PWM converter 2, and 11 pulse waves as shown in FIG. 8 are outputted according to the input value.

In this conventional example, in order to obtain resolution of the pulse width from the PWM section, the oscillator 116 generates a master clock signal using a crystal oscillator with a frequency 32×24=768 times the sampling frequency fs of the input signal. There is.

[0007]

[Problems to be Solved by the Invention] However, with the above configuration, if the sampling frequency fs of the input digital signal is fixed, high performance can be achieved without any problem. The sampling frequency fs of the recorded music signal is 48kHz, 44.1kHz, 3
In a case where three values of 2kHz can be taken, for example, if the sampling frequency fs of the music signal input to the D/A converter is 48kHz, the master clock frequency of the D/A converter is 48kHz x 32 x 24. So 36.
864MHz, but in the case of the same fs = 44.1kHz, the master clock frequency is 44.1kHz x 32 x 2
4 had to be set to 33.8688 MHz, which posed a problem in that a peripheral circuit was required for this purpose.

In view of the above problems, the present invention provides a D/A converter that does not require changing the sampling frequency at which the D/A converter operates even if the sampling frequency of the input digital signal changes. It provides:

[0009]

[Means for Solving the Problems] In order to achieve this object, the D/A converter according to the present invention converts an input digital signal into a digital signal by operating the input digital signal at a sampling frequency higher than the sampling frequency of the digital signal. a quantizer that performs bit compression of the quantizer, and a converter that converts the output of the quantizer into a binary level signal having a predetermined period, and a sampling frequency of the digital signal that can be input to the quantizer. F, the number of oversamplings at which the quantizer operates so that the value of F x N x T is always constant, where N is the number of oversamples that the quantizer operates at this time, and T is the predetermined period; N and the predetermined period T are changed.

0010

[Operation] As described above, the number of oversamplings N at which the quantizer operates and the period T of the binary level signal are changed according to the sampling frequency F of the input digital signal, and moreover, Since the value of T is made constant, there is no need to change the sampling frequency at which the D/A converter operates depending on the sampling frequency of the input digital signal, and the peripheral circuitry can be greatly simplified. .

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. FIG. 1 is a conceptual diagram of a D/A converter according to the present invention. Here, a case is shown in which digital signals with three different sampling frequencies used in DAT are input. To explain this diagram, quantizer 1 and PWM
Converter 2 has a master clock of 48, 44.1, 3.
28.224 MHz, which is a common multiple of 2, is given, and the quantizer 1 uses the clock select signal CSEL according to the sampling frequency of the input digital signal.
and controls the operation of the PWM converter 2.

The quantizer 1 has a sampling frequency of 48k.
When a Hz digital signal is input, it operates with 42 times oversampling and outputs 13 values. When a digital signal with a sampling frequency of 44.1 kHz is input, it operates with 40 times oversampling and outputs 15 values. When a digital signal with a sampling frequency of 32 kHz is input, it operates with 63 times oversampling and outputs 13 values.

[0013] In the PWM converter 2, the sampling frequency is 4.
At 4.1kHz, 16 cycles (Figure 2B) of the master clock (Figure 2A), sampling frequency 48kHz, 32kHz
At time z, the input digital signal is converted into a pulse wave with a conversion period of 14 periods of the master clock (FIG. 2C).

As described above, the sampling frequency fs of the digital signal input to the D/A converter, the oversampling number N at which the quantizer 1 operates, and the period TN of the digital data input to the PWM converter 2 The oversampling number N of the quantizer 1 and the period TN of the digital data input to the PWM converter 2 are changed according to the sampling frequency so that the product of fs×N×TN is constant. Therefore, it is possible to correspond to each sampling frequency without changing the frequency of the master clock.

FIG. 3 is a block diagram showing a specific embodiment of the D/A converter according to the present invention. To explain this figure, numeral 11 is a register which latches input 16-bit data in response to a clock signal WCK operating at a cycle of sampling frequency fs. 12 is an adder. 13 is a feedback circuit having a transfer function H(z), and is operated by a sampling clock inputted to a terminal CK. The transfer function H(z) is as shown in equation (1).

H(z)=-3z-1+3z-2-z-3

(1) 15 is a subtracter, which extracts and outputs the difference Vq between the input and output of the local quantizer 14. 20 is a frequency divider, which controls the frequency division ratio by the clock select signal CSEL, and uses the supplied master clock (here, 28.224
MHz) to generate a sampling clock for the feedback circuit 13. When the sampling frequency fs=44.1kHz, the clock select signal CSEL is “
1”, sampling frequency fs=48kHz, 32kHz
When z, it is set to "0". Therefore, when the clock select signal CSEL=1, the frequency division ratio is 16:1, and when the clock select signal CSEL=0, the frequency division ratio is 14:1.
becomes. 14 is a local quantizer, here (Table 1)
Requantize the input signal as shown in . Note that the output values are shown as normalized values of 7168 and 8192, respectively.

[0017]

[Table 1]

With this configuration, the adder 1
2, the local quantizer 14, the subtracter 15, and the feedback circuit 13 have the input-output relationship as shown in equation (2).
The following noise shaping type quantizer is constructed.

Y=X+(1-z-1)-3×Vq

...(2) Also, since the frequency division ratio is controlled by the clock select signal CSEL according to the input data sampling frequency fs, when fs = 44.1kHz, the master clock is divided by 1/16. The frequency divider output is 1.764MHz, which is 40MHz for the input data.
Operates with double oversampling, fs=48kHz,
When the frequency is 32kHz, the master clock is divided by 1/14, so the frequency divider output is 2.016MHz, and each frequency is 4.
Operates with 2x and 63x oversampling.

FIG. 4 is a block diagram showing the PWM converter 2 in more detail. 41 is a pulse width modulator which outputs a clock select signal CS with the resolution of the master clock.
Pulse width modulation of input digital data N is performed based on EL. When the clock select signal CSEL=1, the input digital data N is
It generates an output as shown in 2. That is, when the period of the master clock is TM, the period of "1" of pulse output P1 is (8+N)×TM, and the period of "0" of pulse output P2 is (8-N)×TM. Clock select signal CSE
When L=0, the period at which digital data N is input =
14×TM, the “1” period of the pulse output P1 is (7+N)×TM, and the “0” period of the pulse output P2 is (7−N)×TM. A mixer 42 performs analog addition of two input signals and outputs the result. Therefore, as shown in FIG. 5, the output of the mixer 42 has a positive pulse waveform when the digital data N is positive, and a negative pulse waveform when the digital data N is negative. Figure 6 shows the clock select signal CSE.
The analog output waveform corresponding to each digital data N when L=1 is shown.

As described above, the operating clock and output gradation (or output cycle) of the quantizer 1 are adjusted according to the sampling frequency of digital data input to the D/A converter.
The frequency of the master clock can be fixed by changing the frequency of the master clock. For example, when this master clock is generated using a crystal oscillator, one crystal oscillator can generate 3
Since it can support any sampling frequency, it is possible to significantly simplify the peripheral circuitry.

[0022] Note that the number of oversampling of the quantizer 1, the output gradation, or the sampling frequency of the input digital data in the above embodiments are not limited to these, for example, fs = 32kHz.
It goes without saying that when z, 49 times oversampling and 17-value output may be used. Also, quantizer 1
Although a third-order noise shaping type quantizer was used in the above embodiment, it is of course not limited to this.
For example, it may be of second order or fourth order. The key is at what frequency the quantizer should be operated and what gradation should be output.

[0023]

As described above, the present invention provides a quantizer that compresses bits of an input digital signal by operating at a sampling frequency higher than the sampling frequency of the digital signal; a converter that converts the output of the quantizer into a binary level signal having a predetermined period, and the sampling frequency of the digital signal that can be input to the quantizer is set to F, at which time the quantizer operates. Set the number of oversampling to N
, when the predetermined period is T, the oversampling number N at which the quantizer operates and the predetermined period T are changed so that the value of F×N×T is always constant. This eliminates the need to change the sampling frequency at which the D/A converter operates depending on the sampling frequency of the input digital signal, and has the excellent effect of greatly simplifying the peripheral circuitry.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram showing a D/A conversion device according to the present invention.

FIG. 2 is a timing diagram showing the relationship between the input of the PWM section and the master clock.

FIG. 3 is a block diagram showing a specific example of a D/A conversion device according to the present invention.

FIG. 4 is a block diagram showing the configuration of the PWM converter 2.

FIG. 5 is a waveform diagram output from the PWM section.

FIG. 6 is a waveform diagram output from the PWM section.

FIG. 7 is a block diagram showing a conventional D/A conversion device.

FIG. 8 is a waveform diagram of a PWM waveform output by a PWM section in a conventional example.

[Explanation of symbols] 1 Quantizer 2 PWM converter 11 Register 12 Adder 13 Feedback circuit 14 Local quantizer 15 Subtractor

Claims (1)

[Claims] 1. A quantizer that compresses bits of an input digital signal at a sampling frequency higher than the sampling frequency of the digital signal, and converts the output of the quantizer into a binary level signal having a predetermined period. Converter, where F is the sampling frequency of the digital signal input to the quantizer, N is the number of oversamplings at which the quantizer operates at this time, and T is the predetermined period. A D/A conversion device in which an oversampling number N at which the quantizer operates and the predetermined period T are changed so that the value of ×N×T is always constant.