JPH0710941U - Pressure contact type semiconductor device - Google Patents

Abstract

(57) [Summary] [Objective] By forming pressure contact structures of the same shape on both sides of a semiconductor substrate, distortion of the semiconductor substrate can be prevented and high performance and high reliability of the pressure contact type semiconductor device are obtained. [Structure] At least four semiconductor layers 5 having different conductivity types
First, on the semiconductor substrate 1 formed by alternately stacking 6, 7, and 8
In pressing the semiconductor element provided with the cathode electrode 10 as the main electrode, the anode electrode 11 as the second main electrode, and the gate electrode 12, the metal pressure welding is performed between the first electrode post 18 and the gate electrode 12. A gate electrode 20 is provided, and a metal pressure contact anode electrode 24 is provided between the second electrode post 19 and the anode electrode 11.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a pressure contact type semiconductor device, and more particularly to an alloy free structure pressure contact electrode structure.

[0002]

[Prior art]

 2. Description of the Related Art Conventional pressure contact type semiconductor devices, in particular pressure contact high power semiconductor devices such as a gate turn-off thyristor (GTO), have been subjected to various improvements in order to apply a uniform pressure to the gate portion.

As a pressure contact type semiconductor device of this type, for example, as disclosed in Japanese Patent Laid-Open No. 3-201543, one side or both sides of a silicon substrate having a junction called a so-called alloy-free structure for the purpose of performance improvement and cost reduction. For all of these, materials that do not alloy with a thermal compensator such as tungsten have been adopted.

In summary, the pressure contact type semiconductor device according to the above-mentioned Japanese Patent Laid-Open No. 3-201543 is formed by a semiconductor substrate in which at least four semiconductor layers having different conductivity types are alternately stacked, and a semiconductor substrate protruding from the surface of the semiconductor substrate. A plurality of semiconductor layers of the first conductivity type, a semiconductor layer of the first conductivity type which is in contact with and continuous with the semiconductor layer and whose surface is exposed, and a second conductivity type which is exposed on the other surface which is the bottom of the semiconductor substrate. The semiconductor layer, the first and second main electrodes formed on the surface and the other surface of the semiconductor substrate, the first and second electrode members formed facing and connected to the first and second main electrodes, First and second electrode posts provided adjacent to the first and second electrode members, and a second electrode adjacent to the plurality of semiconductor layers of the first conductivity type that are installed and protrude in the step portion formed in the first electrode member. Metallic pressure that electrically connects to the conductive semiconductor layer The contact gate electrode, the cylindrical insulator that accommodates the semiconductor substrate with a part of the surfaces of the first and second electrode posts exposed, and the cylindrical insulator with the metal pressure contact gate electrode as the starting point. It is composed of a metal pressure welding gate electrode end portion which is led out to the outside and a metal buffer member formed between the metal pressure welding gate electrode and the extension portion.

[0005]

[Problems to be solved by the device]

 In the above-mentioned conventional pressure contact type semiconductor device, it is necessary that the current drawn from the gate electrode is large, and the pressure contact force of the spring that presses it is strong. Also, when assembling the device, the gate terminal is projected from the surface, and when pressure is applied from both sides of the copper post, both sides of the semiconductor substrate are pressed by the auxiliary electrode and the gate electrode, and then the cathode side auxiliary. The electrodes are pressed, and the respective electrodes are pressed against the semiconductor substrate. In this process, the gate electrode first hits the semiconductor substrate, so that spot-like pressure concentration occurs in this portion and a strain force is applied to the semiconductor substrate. In particular, in the case of GTO, the pressure of the gate spring was strong, so that a large amount of strain was generated, which was a cause of damage.

The present invention has been made in view of the above conventional problems, and an object thereof is to prevent distortion of the semiconductor substrate and improve performance by forming pressure contact structures of the same shape on both surfaces of the semiconductor substrate. An object is to provide a highly reliable pressure contact type semiconductor device.

[0007]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention provides a semiconductor substrate in which at least four semiconductor layers having different conductivity types are alternately stacked, and a plurality of first conductivity type semiconductor layers protruding from the surface of the semiconductor substrate. A second conductive type semiconductor layer which is in contact with and continuous with the semiconductor layer and a part of the surface of which is exposed; a second conductive type semiconductor layer which is exposed on the other surface which is the bottom of the semiconductor substrate; Adjacent to the first and second electrode members, the first and second main electrodes formed on the surface and the other surface, the first and second electrode members formed by facing and connecting the first and second main electrodes, Electrically connected to the first and second electrode posts provided as a second conductive layer and the second conductive type semiconductor layer adjacent to the plurality of semiconductor layers of the first conductive type that are installed and protrude in the step portion formed in the first electrode post. Formed on the metal pressure contact gate electrode and the second electrode post A metal anode electrode that is installed in the difference portion and electrically connected to the first and second semiconductor layers, and a semiconductor substrate with part of the surfaces of the first and second electrode posts exposed It is characterized in that it is constituted by a tubular insulator that

[0008]

[Action]

 By providing the metal pressure contact gate electrode between the first electrode post and the gate electrode and the metal pressure contact anode electrode between the second electrode post and the anode electrode, a uniform pressure contact force is applied to the semiconductor substrate. It

[0009]

【Example】

 An embodiment of the present invention will be described with reference to FIG. 1, which is a cross-sectional view of an anode-short type alloy-free GTO. The present invention can be applied not only to this model but also to other GTOs, such as the Alloy type and Darlington Transistor, and a so-called Center Gate type model will be described. That is, for example, a ceramic cylindrical insulator 2 incorporating a silicon semiconductor substrate 1 in which an element that operates as an envelope and functions as an alloy-free GTO is incorporated has a linear portion 3 and a pleated portion 4. It is configured. The length of each is determined by the rating of the GTO, and as is clear from the figure, the length of the folds 4 is generally larger than that of the straight portions 3, and the folds 4 are Since the length depends on the dielectric strength required for the envelope, it varies depending on the model.

Briefly explaining the details of the alloy-free GTO mounted in the cylindrical insulator 2, at least four silicon semiconductor layers having different conductivity types are alternately stacked to form the silicon semiconductor substrate 1. On the surface, a plurality of semiconductor layers 5 having the first conductivity type, that is, N type and functioning as cathode regions are formed in a protruding manner. A second conductivity type semiconductor layer 6 that operates as a gate region is continuously formed in the plurality of semiconductor layers 5 and the first conductivity type semiconductor layer 5 with a part thereof protruding. … Exposed on the bottom.

On the other hand, a semiconductor layer 7 of a first conductivity type and a semiconductor layer 8 of a second conductivity type are continuously formed on the P-type semiconductor layer 6 so that semiconductor layers of different conductivity types are alternately stacked. A semiconductor substrate 1 is provided. An N-type semiconductor layer 7 is selectively formed on the P-type semiconductor layer 8 which is exposed at the bottom and functions as an anode of the element, and both layers 8 and 6 are exposed, and a common conductive metal is used as described later. A layer, for example, an Al—Si layer is welded at 700 ° C. to form the second main electrode 11 having a short circuit structure.

A conductive metal layer such as Al is deposited on the protruding N-type semiconductor layer 5 to install the first main electrode 10, and the exposed second conductivity-type semiconductor layer 6 is also the same. The electrode 12 is formed by depositing a conductive metal such as Al.

The first and second electrode members 13, 14 are installed adjacent to and opposed to the first and second main electrodes 10, 11 without using solder or the like, that is, alloy-free. As the member 13, a soft metal plate 16 made of Al, Ag, Cu or the like is arranged in addition to the first temperature compensating plate 15 made of refractory metal W, M _o or the like. The soft metal plate 16 may be composed of a plurality of cylindrical metals. Since the attachment of these parts and the electrode post described below is performed in the alloy-free state as described above, a problem of warpage occurs, and the first and second electrode members 13 and 14 are installed in order to install the pressure welding electrode. The structure and the structure of the electrode post are also different.

Therefore, the second electrode member 14 is composed of only the second temperature compensating plate 16, and the first and second electrode posts 18 and 19 are in contact with and opposed to the two electrode members 11 and 14, respectively. Installed in the state. A step portion 21 is formed on the first electrode post 18 in order to install a metal pressure contact gate electrode 20 made of copper or a copper alloy in order to obtain a uniform pressing state. The metal pressure contact gate electrode 20 is brought into contact with the exposed gate electrode 12 in a pressed state.

In order to create this state, an insulating layer 22a such as mica is provided on the step portion 21a corresponding to the metal pressure welding gate electrode 20 so that the metal pressure welding gate electrode 20 is surrounded by substantially insulating material. In addition to the above, a first elastic member 23a such as a coil spring is installed between the two so that a uniform pressing force of 20 to 60 kg is applied.

The most feature of the present invention is that, as shown in FIG. 1, in addition to the first elastic member 20, a second elastic member such as a coil spring is provided to the second electrode post 19 and the second temperature member. That is, it is provided between the degree compensation plates 15. That is, a step 21b is formed on the second electrode post 19, and an insulator 22b such as mica is placed on the step 21b corresponding to the metal pressure contact anode electrode 24 to form a metal pressure contact. Around the anode electrode 25, insulation is ensured, and a second elastic member 23b such as a coil spring is installed between the two so that a uniform pressing force is applied.

To mount the GTO in the tubular insulator 21, the flanges 25 and 26 attached to the ends of the first and second electrode posts 18 and 19 and the straight portion 3 of the tubular insulator 2 are to be mounted. The pressure contact type semiconductor device is completed as an integrated unit by means of bonding.

Although the center gate type semiconductor device has been described in the above embodiments, in the present invention, when the gates are provided in a plurality of places, for example, in the central portion and the peripheral portion of the element, the same pressure is applied to each of them. This can be solved by providing a shape.

[0019]

[Effect of device]

 The present invention is as described above, and in a power semiconductor device having a structure in which electrodes are connected and heat is radiated by mechanically pressure-bonding a heat compensator to both sides of a silicon wafer, the pressure-contact is applied to both sides of the element. Since both pressurizing structures of the pressurizing body are the same, concentrated pressurization on one side does not occur at the time of assembling the element, so that there is no distortion left in the bonding of the semiconductor substrate and deterioration of the element performance. It is possible to obtain a high-performance and high-reliability pressure contact type semiconductor device without the risk of causing it.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a pressure contact type semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Cylindrical insulator 5 ... Cathode area 6 ... Gate area 7 ... 1st conductivity type semiconductor layer 8 ... 2nd conductivity type semiconductor layer 10 ... 1st main electrode 11 ... 2nd main electrode 12 ... Cathode electrode 13 ... 1st electrode member 14 ... 2nd electrode member 15, 16 ... 1st and 2nd temperature compensating plate 18 ... 1st electrode post 19 ... 2nd electrode post 20 ... Metal pressure welding Gate electrodes 23a, 23b ... Coil spring 24 ... Metal pressure contact anode electrode

Claims (1)

[Scope of utility model registration request] 1. A semiconductor substrate formed by alternately stacking at least four semiconductor layers having different conductivity types, a plurality of semiconductor layers of a first conductivity type formed so as to project on a surface of the semiconductor substrate, and contacting the semiconductor layers. A second conductive type semiconductor layer which is continuous and has a part of the surface exposed, a second conductive type semiconductor layer which is exposed at the other surface which is the bottom of the semiconductor substrate, and a second conductive type semiconductor layer which is formed on the surface and the other surface of the semiconductor substrate. 1st and 2nd main electrode, 1st and 2nd
First and second electrode members that are formed so as to be opposed to the main electrode, and first and second electrodes that are provided adjacent to the first and second electrode members.
Electrode post, and a metal pressure contact gate electrode electrically connected to a second conductivity type semiconductor layer adjacent to a plurality of first conductivity type semiconductor layers that are installed in a stepped portion formed in the first electrode post and project. Exposing a part of the surface of the first and second electrode posts, and a metal anode electrode which is installed in the step portion formed in the second electrode post and electrically connected to the first and second semiconductor layers. A pressure contact type semiconductor device, characterized in that the pressure contact type semiconductor device is configured by a cylindrical insulator that accommodates the semiconductor substrate in the above state.