JPH07114479A - Interrupt control method - Google Patents

Abstract

(57) [Summary] [Structure] A command read request from the processing unit (PU) is sent from the signal line 121-124 to the counter 201.
To 204 and are counted. This counting operation is performed at intervals of the clock signal from the clock 200. This counter value is compared with the comparators 211-213, AND
The gates 241-244 compare the magnitude. The gate 241-244 outputs the value of the input port as it is from the output port o3 when the value of the input port i4 is true, and does not output the signal from o3 when it is false; the signals of the gates 241-244 correspond to each other. PU101-
The signal is output to the interrupt request signal reception unit 103. [Effect] It is possible to suppress the generation of an interrupt to a PU that has a high hit rate on the instruction cache and suppress an increase in cache misses due to interrupt processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system including a processing unit (hereinafter referred to as PU) having a built-in cache memory, and more particularly to a system which responds to an interrupt request from its input / output device at high speed. .

[0002]

2. Description of the Related Art In a multiprocessor system, when an interrupt request occurs, it is a problem in which processor unit the interrupt request is processed. Conventionally, a method has been considered in which a process having the lowest priority among the processor units is executed and the process is executed there.

For example, pp. 89-
There is a description in 96 "Comparison of device access methods in MP UNIX".

[0004]

In the prior art, no consideration is given to the state of the PU at the time of generation of an interrupt factor. For example, most instructions hit the cache and can be processed efficiently. May cause an interrupt to the processor. In that case, there is a problem in that the cache of the process that is being efficiently executed for executing the interrupt process is lost and the processing efficiency is deteriorated.

A first object of the present invention is to suppress the generation of an interrupt to a PU that has a high hit rate on the instruction cache and suppress an increase in cache misses due to interrupt processing.

A second object of the present invention is to, under the same conditions, when software can predict that the hit ratio to the cache for a specific part executed by itself will improve.
Based on this information, it is necessary to give the software a means that makes it difficult for interrupt requests to occur only in a specific part of the software. However, this is different from mere interrupt prohibition, and an interrupt must be generated in any of the PUs for which interrupts are not prohibited.

[0007]

In order to achieve the first object, the following means are provided. That is, a counter for measuring the number of fetch requests is provided for each PU. A timer that outputs a signal at fixed time intervals is provided, and the output signal is connected to the input port of the reset signal of the counter. A comparison circuit is provided to obtain the maximum value of each counter. This circuit outputs a signal for each PU, only the signal for the PU that outputs the maximum counter value is true, and the others are false.
se). Next, each PU is provided with a gate that outputs an input signal according to the control signal, and the signal from the above-mentioned comparison circuit is input to the control signal of this gate. An interrupt signal is input to the input port of this gate. The output signal is used as an interrupt signal for each PU.

The following means are provided to achieve the second object. A storage device is provided for each PU. This storage device is
Make it visible from U to the same address. A comparison circuit is provided to obtain the maximum value stored in this storage device. This circuit outputs a signal for each PU, and only the signal for the PU that is outputting the maximum counter value is true.
, And the others are false. Next, each PU is provided with a gate that outputs an input signal according to a control signal. The content is the same as the gate provided for the first task.

[0009]

The means provided for the first object operates as follows. During normal processing execution, a signal of an instruction read request (fetch) among memory requests from the PU to the main memory is measured by the counter. A signal from a timer is supplied to this counter, and the number of recent fetches is stored. The count value of each PU is compared through the comparison circuit, and only the signal for the PU corresponding to the maximum value is set to true.
e, false signals are output to other PUs. These signals are used as control signals for the gates corresponding to each PU. An interrupt signal from the input / output device is input to this gate. If the control signal is false when the interrupt signal is input, the interrupt signal is not output from this gate and is not input to the PU. If the control signal is true, an interrupt signal is output from this gate, input to the corresponding PU, and an interrupt request is made.

Among PUs, P has a high cache hit rate
For U, the fetch count value is reduced, and the occurrence of interrupts is suppressed.

The means provided for the second task operate as follows. If the program does not want to be interrupted if the part of the program to be executed can be done (for example, if the cache hit rate is predicted to be high), then according to the degree, for each PU in the above means, Put a small number in the provided storage device. If not, enter a large number. This number is input to the comparison circuit, and thereafter the same operation as the means provided for the first problem is performed. As a result, it is possible to suppress the generation of an interrupt to the PU that specifies the smallest value among the PUs. That is, when the program is executing the part that you do not want to be interrupted and other PU can interrupt,
Interrupts to the PU executing the part that is least likely to be interrupted are suppressed.

[0012]

EXAMPLE A first example will be described with reference to FIGS. Figure 1
2 is a block diagram of a computer system according to the present invention, and FIG. 2 is a block diagram of the interrupt control circuit in FIG.
This system has 101-104 processing units (hereinafter referred to as PUs), and signal lines 111-114, respectively.
To the bus 110 via. Main memory 10
5 is connected to the bus 110 via the signal line 115 and the input / output device 107 is connected to the bus 110 via the signal line 117. The interrupt control circuit 106 connects a part of the signal lines 111-114 connecting each PU and the bus 110 to the signal line 121-1.
You are entering by 24. It is also assumed that the interrupt request signal on the bus is input to the interrupt control circuit 106 via the signal line 116. Further, it is assumed that the signal lines 121 to 124 also include an interrupt signal sent from the interrupt control circuit 106 to each PU.

Next, FIG. 2 will be described. Signal line 121
-124 includes the fetch signal fetch output from the PU as an input signal. Further, 121-124 include the interrupt signal intr as a signal that is being output. Further, the interrupt request signals from the input device 107 are 117,1
It is input to the interrupt control circuit via 19, 116.
The fetch counters 201-204 count the number of fetch requests at designated time intervals while receiving the signal from the clock 200. It is assumed that each of the comparators 211 to 213 has the following functions. The magnitudes of the data values input from i1 and i2 are compared. If i1 is large, true is output, and if not, false is output from the output port o1. The larger value of i1 and i2 is output from o2. The output o2 from the comparator 213 is not used in this configuration. The output from o1 of each comparator is inverted if necessary and AND gates 231-23
It is entered in 4. The output signal from the AND gates 231-234 is supplied to the gate 2 together with the interrupt request signal 116.
41-244. The operation of the gates 241-244 is as follows. An input signal comes in from i3 and i4, and an output signal comes out from o3. When the information arrives at i3, if i4 is true, the information input from i3 is o3.
Is output from. If i4 is false, the information of i3 is ignored and it is not output from o3.

Next, the operation of each part will be described.

During normal processing execution, the PU 101-10
Reference numeral 4 reads / writes information from / to the main memory 105 via the bus 110. A read request (hereinafter referred to as a fetch request) for reading an instruction is issued through the signal lines 111-114, 110, 1
At the same time as being sent to the main memory via
The signal is branched from 1-114 and transmitted to the interrupt control circuit 106 via signal lines 121-124. The interrupt control circuit 106 performs the following processing.

The fetch signal is measured by counters 211-204. A signal from the timer 200 is supplied to this counter so that the number of recent fetches is stored. The count value for each PU is processed by the comparators 211-213 and the AND gates 231-234, and from the AND gates 213-234, the AN corresponding to the maximum value in the fetch counters 201-204 is processed.
True from D gate, fa from other AND gates
lse is output. For example, the operation when the counter 201 has the maximum value is as follows. Since the modulus of the input of i1 is larger than i2 (since 201 is the maximum), true is output from the output port o1 of the comparator 211. The information input from i1 (that is, the maximum count value) is output from o2 and input to i1 of the comparator 213. i1
Since the value input to is the maximum value, true is output from the comparator 213 regardless of the output from the comparator 212. All the outputs from o1 of the comparator 213 are inverted (that is, become false) and then the gates 233 and 234 are output.
Sent to. The output from o1 of the comparator 211 is inverted and sent to the gate 232.
Is output. Since the inputs to the gate 231 are all true, the gate 231 outputs true.

When an interrupt factor occurs in the input / output device 107, the signal line 117, the bus 110, and the signal line 116.
An interrupt request is sent to the interrupt control circuit via.
The signal 116 is input to i3 of the gates 241-244. At this time, tr in AND gates 241-244
The gate receives an input from the AND gate outputting ue, and sends an interrupt signal from its output port o3, but no interrupt request signal is output from the other gates. For example, when the value of the fetch counter 202 is the maximum, true is returned from the AND gate 232 to 23
False is output from 1,233,234 and the gate 242
An interrupt signal is output from 241, 243, 24
No interrupt signal is output from No. 4. The interrupt signal from the gate 242 is the intr of the signal line 122 and the signal line 112.
Is sent to the pu 102, and the interrupt operation is started.

According to this embodiment, an interrupt is preferentially generated for a processor having a short fetch interval, and an interrupt to a PU having a high cache hit rate and a long fetch interval is suppressed.

A second embodiment will be described with reference to FIGS. FIG. 1 is a block diagram of a computer system according to the present invention,
FIG. 3 is a block diagram of the interrupt control circuit in FIG. In the first embodiment, the signal lines 121-124 are the instruction read signal (fetch signal) and the interrupt request signal, but in this example, it is assumed that the entire signal for accessing the main memory is input. When there is a memory request for a specific address from the memory access from the PU, the request is not sent to the main memory 105, but to the storage devices 301-304 via the signal lines 121-124. In this embodiment, it is assumed that the word access to the address 0x10000000 is not the main memory but the storage devices 301 to 304 provided for each PU. The difference between FIG. 2 and FIG. 3 is that the fetch counters 201-204 and the timer 200 are the storage device 3.
It replaces 01-304.

When a request for access to address 0x10000000 is issued from each PU in the same procedure as a normal main memory access, the processing request is an access to the corresponding storage device. For example,
When the PU 103 issues an instruction to write the numerical value 0x1234 to the address 0x10000000, 0x1234 is stored in the storage device 303. In this way, each PU 101-104
Writes data to the corresponding storage device 301-304 by accessing the address 0x10000000.

By performing exactly the same operation as in the first embodiment, true is given from the AND gate corresponding to the storage device holding the maximum value in the storage devices 301-304, but from the other AND gates. false is output.

When an interrupt factor is generated in the input / output device 107, the storage device 3 is operated by the same operation as that of the first embodiment.
The interrupt request signal is output from the gate corresponding to the storage device holding the maximum value of 01-304, and the interrupt request is not output from the other gates.

Consider the following operation of the software shown in FIG. 4 under such an environment.

This is a program for transferring the data in the designated area to the designated area by the designated size. In this example, it is assumed that the main storage device 105 and the bus 110 are sufficiently fast, and memory access from each PU can be executed in parallel. The data transfer amount in the PU 101, 102, 103, 104 is 1 MB, 2 MB, 4 MB, 8 MB, respectively.
And

In steps 401 and 402, each PU reads the information from each storage device 301-304, stores it in the temporary variable s on each context, and stores it in each storage device.
0x1000000, −0x2000000, −0x4000000, −0x8000000 are recorded. Steps 403-403 are normal memory transfers. It is assumed that an interrupt request is output from the input / output device 107 during execution of these. As described above, the interrupt signal is output to the PU 101 corresponding to the storage device 301 holding the maximum value among the storage devices 301 to 304, and the interrupt start processing is executed.

As described above, according to the present embodiment, interruption of a program that attempts to transfer more information is suppressed,
Prevent the cache hit rate from decreasing in the PU,
The throughput of the entire system can be improved.

[0027]

As described above, according to the present invention, it is possible to suppress the generation of an interrupt to a PU having a high hit rate on the instruction cache and to suppress the increase of cache misses due to the interrupt processing.

When the software can predict that the hit ratio to the cache for the specific part executed by itself will be improved, it becomes difficult for the specific part of the software to generate an interrupt request based on the information. Means will be available to software.

[Brief description of drawings]

FIG. 1 is a system block diagram in a first embodiment and a second embodiment.

FIG. 2 is a block diagram of an interrupt control circuit according to the first embodiment.

FIG. 3 is a detailed block diagram of an interrupt control circuit according to a second embodiment.

FIG. 4 is a flowchart of a program that executes a second embodiment.

[Explanation of symbols]

101-104 ... PU, 105 ... Main storage device, 107 ...
I / O device, 106 ... Interrupt control device, 200 ... Clock, 201-204 ... Fetch counter, 211-
213 ... Comparator, 231-234 ... AND gate, 24
1-244 ... Gate of interrupt signal, 301-304 ...
Storage device.

Claims (2)

[Claims] 1. A multiprocessor system comprising a processing unit containing a cache memory, wherein means for measuring the frequency of an instruction read request signal output from each processing unit is provided, and an interrupt request from each input / output device is provided. An interrupt control method characterized in that a processing unit to be interrupted is determined according to a frequency of an instruction read signal from each processing unit when the processing unit occurs. 2. A multiprocessor system comprising a processing unit having a built-in cache memory, wherein a one-word storage device is provided for each processing unit, and the software stores a value in the cache memory in accordance with the operating status of the software. An interrupt control method, wherein a processing unit to be substituted is determined according to the magnitude of a value stored in the cache memory when an interrupt request is issued from each input / output device.