JPH0712054B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0712054B2 JPH0712054B2 JP61293817A JP29381786A JPH0712054B2 JP H0712054 B2 JPH0712054 B2 JP H0712054B2 JP 61293817 A JP61293817 A JP 61293817A JP 29381786 A JP29381786 A JP 29381786A JP H0712054 B2 JPH0712054 B2 JP H0712054B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- layer
- type
- conductivity
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Landscapes
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置およびその製造方法に関し、特に
素子間の絶縁分離として側壁に絶縁物を有する溝を用い
た半導体装置およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device using a groove having an insulator on a side wall as insulation isolation between elements and a method for manufacturing the same. .
従来、絶縁物と多結晶シリコンが埋設された溝によって
素子間の絶縁分離を行っているバイポーラトランジスタ
を有する半導体装置では、第３図に示す様に、溝壁に形
成されたシリコン酸化膜15界面での導電層の導電型の反
転を防ぐ為に、溝形成後にイオン注入によって溝の底部
の広い領域にわたって高濃度のチャンネルストッパー層
14A（以下CS層と呼ぶ）を形成していた。尚第３図にお
いて11はＰ型シリコン基板、12はN+型埋込層、13はＮ型
エピタキシャル層である。Conventionally, in a semiconductor device having a bipolar transistor in which insulation is isolated between elements by a groove in which an insulator and polycrystalline silicon are buried, as shown in FIG. 3, an interface of a silicon oxide film 15 formed on a groove wall is used. In order to prevent the reversal of the conductivity type of the conductive layer in the channel, a high concentration channel stopper layer is formed over the wide area at the bottom of the groove by ion implantation after forming the groove
14A (hereinafter referred to as CS layer) was formed. In FIG. 3, 11 is a P-type silicon substrate, 12 is an N + -type buried layer, and 13 is an N-type epitaxial layer.
上述した従来の半導体装置の構造では、CS層14Aが溝壁
に沿って溝の浅い所まで形成されている為、CS層14Aが
サブコレクターとなるN+型埋込層12と接してしまう。そ
の結果コレクターと基板間の容量（以下Ccsと記す）が
増し、素子の動作速度の遅延をもたらすという問題点が
あった。In the structure of the conventional semiconductor device described above, the CS layer 14A is formed along the groove wall up to the shallow portion of the groove, so that the CS layer 14A comes into contact with the N + type buried layer 12 serving as the subcollector. As a result, there is a problem that the capacitance between the collector and the substrate (hereinafter referred to as C cs ) increases and the operation speed of the device is delayed.
本発明の目的はCcsの増大を防ぎ、動作速度の速い半導
体装置およびその製造方法を提供することにある。It is an object of the present invention to provide a semiconductor device which prevents an increase in C cs and has a high operating speed, and a manufacturing method thereof.
第１の発明の半導体装置は、第１導電型半導体基板の全
面上に形成された高濃度の第２導電型埋込層と、該埋込
層上に形成された低濃度の第２導電型エピタキシャル層
と、該エピタキシャル層表面から前記埋込層を貫通し前
記半導体基板の内部に達する第１の溝と、該第１の溝表
面に形成された絶縁膜と、前記第１の溝の底面中央部の
前記絶縁膜に形成された第２の溝と、該第２の溝下部の
前記半導体基板に形成され前記第１の溝の底面の幅より
狭い高濃度の第１導電型拡散層と、前記第１および第２
の溝を埋設する多結晶シリコン層とを含むものである。A semiconductor device according to a first aspect of the present invention is a high-concentration second-conductivity-type buried layer formed on the entire surface of a first-conductivity-type semiconductor substrate, and a low-concentration second-conductivity-type buried layer formed on the buried layer. An epitaxial layer, a first groove penetrating the buried layer from the surface of the epitaxial layer to reach the inside of the semiconductor substrate, an insulating film formed on the surface of the first groove, and a bottom surface of the first groove. A second groove formed in the insulating film in the central portion, and a high-concentration first conductivity type diffusion layer formed in the semiconductor substrate below the second groove and having a narrower width than the bottom surface of the first groove; , The first and second
And a polycrystalline silicon layer for burying the trench.
第２の発明の半導体装置の製造方法は、第１導電型半導
体基板上に高濃度の第２導電型押込層と低濃度の第２導
電型エピタキシャル層とを順次形成する工程と、前記エ
ピタキシャル層表面から前記半導体基板の内部に達する
第１の溝を形成したのち該第１の溝表面に絶縁膜を形成
する工程と、全面に多結晶シリコン層を形成したのちエ
ッチングし前記第１の溝の側壁部にのみ残し底面の前記
絶縁膜を露出させる工程と、側壁部に残した前記多結晶
シリコン層をマスクとして露出した前記絶縁膜をエッチ
ングし第２の溝を形成する工程と、不純物を導入し前記
第２の溝下の前記半導体基板に前記第１の溝の底面の幅
より狭い高濃度の第１導電型拡散層を形成したのち前記
第１および第２の溝を多結晶シリコン層で埋める工程と
を含むものである。A method of manufacturing a semiconductor device according to a second aspect of the present invention comprises a step of sequentially forming a high-concentration second conductivity-type indented layer and a low-concentration second conductivity-type epitaxial layer on a first conductivity-type semiconductor substrate, and the epitaxial layer. A step of forming a first groove extending from the surface to the inside of the semiconductor substrate and then forming an insulating film on the surface of the first groove; and a step of forming a polycrystalline silicon layer on the entire surface and etching the first groove. A step of exposing the insulating film on the bottom surface which is left only on the side wall portion, a step of etching the exposed insulating film using the polycrystalline silicon layer left on the side wall portion as a mask to form a second groove, and introducing impurities Then, a high-concentration first-conductivity-type diffusion layer narrower than the width of the bottom surface of the first groove is formed on the semiconductor substrate under the second groove, and then the first and second grooves are formed of a polycrystalline silicon layer. And the process of filling
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of the first embodiment of the present invention.
第１図において、Ｐ型シリコン基板11上にはN+型埋込層
12,N型エピタキシャル層13が形成されている。そしてこ
のＮ型エピタキシャル層13表面からＰ型シリコン基板11
に達する第１の溝10が形成されており、この溝10の表面
にはシリコン酸化膜15が形成されている。更に、第１の
溝10の底面中央部のシリコン酸化膜には底面の幅より狭
い第２の溝20が形成されその下のシリコン基板11にはP+
型CS層14が形成されている。尚第１図において、16は溝
中に埋込まれた多結晶シリコンである。In FIG. 1, an N + type buried layer is formed on the P type silicon substrate 11.
12, N-type epitaxial layer 13 is formed. Then, from the surface of the N-type epitaxial layer 13 to the P-type silicon substrate 11
A first groove 10 is formed, and a silicon oxide film 15 is formed on the surface of the first groove 10. Further, a second groove 20 narrower than the width of the bottom surface is formed in the silicon oxide film at the center of the bottom surface of the first groove 10, and P + is formed in the silicon substrate 11 thereunder.
The mold CS layer 14 is formed. In FIG. 1, 16 is polycrystalline silicon embedded in the groove.
このように構成された第１の実施例においては、P+型CS
層14は第１の溝底面部のほぼ中心部にのみ形成されてい
るためにN+型埋込層12と接触することはないため、Ccs
の増大は抑制される。またP+型CS層14が、シリコン酸化
膜15に形成された第２の溝20を介して、第１の溝10中に
埋設された多結晶シリコン層16と電気的に接続している
ため、この多結晶シリコン層16を基板電位の取り出し用
電極として用いることができる。In the first embodiment configured as described above, the P + type CS
Since the layer 14 does not come into contact with the N + -type buried layer 12 because it is formed only substantially in the center of the bottom surface of the first groove, C cs
Is suppressed. Further, the P + -type CS layer 14 is electrically connected to the polycrystalline silicon layer 16 embedded in the first groove 10 through the second groove 20 formed in the silicon oxide film 15. The polycrystalline silicon layer 16 can be used as an electrode for extracting the substrate potential.
次に、第２の実施例の製造方法について説明する。Next, the manufacturing method of the second embodiment will be described.
第２図（ａ）〜（ｅ）は本発明の第２の実施例の製造方
法を説明するための工程順に示した半導体チップの断面
図である。2 (a) to 2 (e) are sectional views of the semiconductor chip in the order of steps for explaining the manufacturing method according to the second embodiment of the present invention.
まず第２図（ａ）に示すように、Ｐ型シリコン基板11上
に厚さ２μｍのN+型埋込層12,厚さ１μｍのＮ型エピタ
キシャル層13を形成したのち、厚さ約50nmのシリコン酸
化膜15及び厚さ約120nmのシリコン窒化膜26をその上に
成長させる。次でフォトレジストからなるマスク27を用
いて、異方性エッチングを行ないシリコン窒化膜26から
Ｐ型シリコン基板11に達する第１の溝10を選択的に形成
する。First, as shown in FIG. 2A, an N + type buried layer 12 having a thickness of 2 μm and an N type epitaxial layer 13 having a thickness of 1 μm are formed on a P type silicon substrate 11, and then a thickness of about 50 nm is formed. A silicon oxide film 15 and a silicon nitride film 26 having a thickness of about 120 nm are grown thereon. Next, using a mask 27 made of photoresist, anisotropic etching is performed to selectively form the first trench 10 extending from the silicon nitride film 26 to the P-type silicon substrate 11.
次に第２図（ｂ）に示すように、第１の溝10の内壁を酸
化して厚さ約200nmのシリコン酸化膜15Aを形成し、更に
厚さ約0.5μｍの多結晶シリコン層16Aを成長させる。Then, as shown in FIG. 2B, the inner wall of the first groove 10 is oxidized to form a silicon oxide film 15A having a thickness of about 200 nm, and a polycrystalline silicon layer 16A having a thickness of about 0.5 μm is further formed. Grow.
次に第２図（Ｃ）に示すように、多結晶シリコン層16A
を異方性エッチングし、第１の溝10の側壁のみに多結晶
シリコン層16Aを残す。Next, as shown in FIG. 2C, the polycrystalline silicon layer 16A
Is anisotropically etched to leave the polycrystalline silicon layer 16A only on the side wall of the first groove 10.
次に第２図（ｄ）に示すように、溝側壁に残した多結晶
シリコン層16Aをマスクに第１の溝10の底部のシリコン
酸化膜15Aを除去して第２の溝20を形成したのち、ボロ
ン拡散を行ってP+型CS層14を形成する。Next, as shown in FIG. 2 (d), the second trench 20 is formed by removing the silicon oxide film 15A at the bottom of the first trench 10 by using the polycrystalline silicon layer 16A left on the sidewall of the trench as a mask. After that, boron diffusion is performed to form the P + -type CS layer 14.
次に第２図（ｅ）に示すように、多結晶シリコン層16B
を埋設したのち第１図に示したようにその表面を酸化す
る。以下常法に従ってエピタキシャル層13にベース、エ
ミッタ等を形成しバイポーラトランジスタを完成させ
る。Next, as shown in FIG. 2 (e), the polycrystalline silicon layer 16B is formed.
After burying, the surface is oxidized as shown in FIG. Thereafter, a base, an emitter, etc. are formed on the epitaxial layer 13 according to a conventional method to complete a bipolar transistor.
以上説明したように本発明は、チャンネルストッパー層
を溝底部の中心部のみに形成し、このチャンネルストッ
パー層が高濃度の埋込層と接触するのを防ぐ事によって
コレクターと基板間の容量の増大を抑制できる効果があ
る。従って動作速度の速い半導体装置が得られる。As described above, the present invention increases the capacitance between the collector and the substrate by forming the channel stopper layer only in the central portion of the groove bottom and preventing the channel stopper layer from coming into contact with the high-concentration buried layer. There is an effect that can suppress. Therefore, a semiconductor device having a high operation speed can be obtained.
【図面の簡単な説明】 第１図は本発明の第１の実施例の断面図、第２図（ａ）
〜（ｅ）は本発明の第２の実施例の製造方法を説明する
ための工程順に示した半導体チップの断面図、第３図は
従来の半導体装置の一例の断面図である。 10……第１の溝、11……Ｐ型シリコン基板、12……N+型
埋込層、13……Ｎ型エピタキシャル層、14,14A……P+型
CS層、15,15A……シリコン酸化膜、16,16A,16B……多結
晶シリコン層、20……第２の溝、26……シリコン窒化
膜、27……マスク。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a first embodiment of the present invention, and FIG. 2 (a).
3A to 3E are sectional views of the semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention, and FIG. 3 is a sectional view of an example of a conventional semiconductor device. 10 …… First groove, 11 …… P type silicon substrate, 12 …… N + type buried layer, 13 …… N type epitaxial layer, 14,14A …… P + type
CS layer, 15,15A ... silicon oxide film, 16,16A, 16B ... polycrystalline silicon layer, 20 ... second groove, 26 ... silicon nitride film, 27 ... mask.
Claims (2)
た高濃度の第２導電型埋込層と、該埋込層上に形成され
た低濃度の第２導電型エピタキシャル層と、該エピタキ
シャル層表面から前記埋込層を貫通し前記半導体基板の
内部に達する第１の溝と、該第１の溝表面に形成された
絶縁膜と、前記第１の溝の底面中央部の前記絶縁膜に形
成された第２の溝と、該第２の溝下部の前記半導体基板
に形成され前記第１の溝の底面の幅より狭い高濃度の第
１導電型拡散層と、前記第１および第２の溝を埋設する
多結晶シリコン層とを含むことを特徴とする半導体装
置。1. A high-concentration second-conductivity-type buried layer formed on the entire surface of a first-conductivity-type semiconductor substrate, and a low-concentration second-conductivity-type epitaxial layer formed on the buried layer. A first groove penetrating the buried layer from the surface of the epitaxial layer to reach the inside of the semiconductor substrate; an insulating film formed on the surface of the first groove; and a central portion of a bottom surface of the first groove. A second groove formed in the insulating film; a high-concentration first conductivity type diffusion layer formed in the semiconductor substrate below the second groove and having a width narrower than the bottom surface of the first groove; And a polycrystalline silicon layer filling the second trench.
電型埋込層と低濃度の第２導電型エピタキシャル層とを
順次形成する工程と、前記エピタキシャル層表面から前
記半導体基板の内部に達する第１の溝を形成したのち該
第１の溝表面に絶縁膜を形成する工程と、全面に多結晶
シリコン層を形成したのちエッチングし前記第１の溝の
側壁部にのみ残し底面の前記絶縁膜を露出させる工程
と、側壁部に残した前記多結晶シリコン層をマスクとし
て露出した前記絶縁膜をエッチングし第２の溝を形成す
る工程と、不純物を導入し前記第２の溝下の前記半導体
基板に前記第１の溝の底面の幅より狭い高濃度の第１導
電型拡散層を形成したのち前記第１および第２の溝を多
結晶シリコン層で埋める工程とを含むことを特徴とする
半導体装置の製造方法。2. A step of sequentially forming a high-concentration second-conductivity-type buried layer and a low-concentration second-conductivity-type epitaxial layer on a first-conductivity-type semiconductor substrate, and a step of forming the semiconductor substrate from the surface of the epitaxial layer. A step of forming a first groove reaching the inside and then forming an insulating film on the surface of the first groove; and a step of forming a polycrystalline silicon layer on the entire surface and then etching, leaving only the sidewall of the first groove and leaving the bottom surface. Exposing the insulating film, forming a second groove by etching the exposed insulating film using the polycrystalline silicon layer left on the side wall as a mask, and introducing impurities into the second groove. Forming a high-concentration first-conductivity-type diffusion layer narrower in width than the bottom surface of the first groove on the lower semiconductor substrate, and then filling the first and second grooves with a polycrystalline silicon layer. For manufacturing semiconductor devices characterized by .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61293817A JPH0712054B2 (en) | 1986-12-09 | 1986-12-09 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61293817A JPH0712054B2 (en) | 1986-12-09 | 1986-12-09 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63144541A JPS63144541A (en) | 1988-06-16 |
| JPH0712054B2 true JPH0712054B2 (en) | 1995-02-08 |
Family
ID=17799534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61293817A Expired - Lifetime JPH0712054B2 (en) | 1986-12-09 | 1986-12-09 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0712054B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58134443A (en) * | 1982-02-04 | 1983-08-10 | Toshiba Corp | Manufacture of semiconductor device |
| JPS59124141A (en) * | 1982-12-28 | 1984-07-18 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-12-09 JP JP61293817A patent/JPH0712054B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63144541A (en) | 1988-06-16 |
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