JPH07120636B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH07120636B2 JPH07120636B2 JP61299436A JP29943686A JPH07120636B2 JP H07120636 B2 JPH07120636 B2 JP H07120636B2 JP 61299436 A JP61299436 A JP 61299436A JP 29943686 A JP29943686 A JP 29943686A JP H07120636 B2 JPH07120636 B2 JP H07120636B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor thin
- atoms
- conductivity type
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Recrystallisation Techniques (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するもので、特に集
積回路等の熱拡散工程における不純物拡散源の不純物含
有の均一性を改良した製造方法に係るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having improved uniformity of impurity content in an impurity diffusion source in a thermal diffusion process such as an integrated circuit. Is.
従来の技術 半導体装置において高性能な素子を得るためには、浅い
不順物拡散による接合の形成を必要とする。たとえば、
半導体基板上に多結晶半導体薄膜を堆積し、この薄膜中
に不純物をイオン注入後、熱処理して不純物を半導体基
板内に拡散し、所望の浅い不純物拡散領域を形成するこ
とが一般的手法になってきている。2. Description of the Related Art In order to obtain a high-performance element in a semiconductor device, it is necessary to form a junction by shallow irregular substance diffusion. For example,
It is a general method to deposit a polycrystalline semiconductor thin film on a semiconductor substrate, ion-implant impurities into the thin film, and heat-treat to diffuse the impurities into the semiconductor substrate to form a desired shallow impurity diffusion region. Is coming.
発明が解決しようとする問題点 一般的に、多結晶半導体薄膜を堆積する時、反応部の温
度分布の不均一性や、半導体基板面での赤外線反射等の
原因により、堆積した多結晶半導体薄膜の結晶粒の大き
さが半導体基板面内で不均一となりやすい。このような
多結晶半導体薄膜に注入された不純物原子の一部は、注
入後の熱処理によって結晶粒と結晶粒との境界、すなわ
ち結晶粒界に取り込まれ不活性化する。結晶粒の小さい
部分では結晶粒界が大きく、多くの不純物原子が不活性
化し、結晶粒の大きい部分では結晶粒界が小さく、多く
の不純物原子が結晶粒内で活性化する。従って、多結晶
半導体薄膜の結晶粒の大きさが不均一であると、この膜
から半導体基板内に拡散される不純物の濃度分布に不均
一を生じる。すなわち、均質性の悪い接合が形成され
る。このことが製造上のの歩留と製品の品質を低下させ
ていた。例えば、導電型を決める原子のイオン注入の前
に多結晶半導体薄膜を熱処理して結晶粒の大きさを均一
化するプリアニール法が、1984年、ジャーナル オブエ
レクトロケミカル ソサエティー(Journal of Electro
chemical Society)、第131巻、1号、216〜217頁に記
載されているが、充分な均一性を得るためには1000℃以
上の高温での熱処理が必要であり、実際の半導体素子の
製造工程に応用することは必ずしも好ましくない。ま
た、熱処理した多結晶半導体薄膜において、表面に近い
部分ほど結晶粒の大きさは大きくなり、均一化すること
が、1984年、ジャーナル オブ バキューム サイエン
ス テクノロジー(Journal of Vacuum Science Techno
logy)、B、第2巻、第4号、698〜706頁に記載されて
いる。もし、このような結晶状態を想定するならば、イ
オン注入によって多結晶半導体薄膜表非晶質化すると、
その後の熱処理で多結晶半導体薄膜表面下層部の小さな
結晶粒が種となって表面が再結晶化するために、結晶粒
の大きさは不均一となり、従って高均一性の拡散源を形
成しにくいと考えられる。Problems to be Solved by the Invention Generally, when depositing a polycrystalline semiconductor thin film, the deposited polycrystalline semiconductor thin film is caused by non-uniformity of temperature distribution in a reaction part, infrared reflection on a semiconductor substrate surface, or the like. The size of the crystal grains is likely to be nonuniform in the plane of the semiconductor substrate. A part of the impurity atoms implanted into such a polycrystalline semiconductor thin film is taken into a boundary between crystal grains, that is, a grain boundary, and inactivated by a heat treatment after implantation. The crystal grain boundary is large in the small crystal grain portion and many impurity atoms are inactivated, and the crystal grain boundary is small in the large crystal grain portion and many impurity atoms are activated in the crystal grain. Therefore, if the crystal grain size of the polycrystalline semiconductor thin film is not uniform, the concentration distribution of the impurities diffused from this film into the semiconductor substrate will be uneven. That is, a bond with poor homogeneity is formed. This has reduced manufacturing yield and product quality. For example, in 1984, the pre-annealing method, in which a polycrystalline semiconductor thin film is heat-treated to uniformize the crystal grain size before ion implantation of atoms that determine the conductivity type, is described in the Journal of Electrochemical Society.
Chemical Society), Vol. 131, No. 1, pp. 216-217, but in order to obtain sufficient uniformity, heat treatment at a high temperature of 1000 ° C. or higher is required, and the actual manufacturing of semiconductor devices. It is not always preferable to apply it to the process. In addition, in the heat-treated polycrystalline semiconductor thin film, the size of the crystal grains becomes larger toward the portion closer to the surface, and it can be seen in 1984 that the Journal of Vacuum Science Technology (Journal of Vacuum Science Technology
logy), B, Vol. 2, No. 4, pages 698-706. If such a crystalline state is assumed, if the polycrystalline semiconductor thin film surface is made amorphous by ion implantation,
In the subsequent heat treatment, small crystal grains in the lower layer of the polycrystalline semiconductor thin film serve as seeds and the surface is recrystallized, resulting in non-uniform crystal grain size, making it difficult to form a highly uniform diffusion source. it is conceivable that.
本発明はこのような問題点を解決するもので、多結晶半
導体の結晶粒の大きさの不均一を緩和することで多結晶
半導体内の不純物濃度分布の均一性を高め熱拡散工程に
おける不純物拡散領域の不純物濃度分布の均一性の改良
と品質の改善をめざした半導体装置の製造方法を提供す
るものである。The present invention solves such a problem by alleviating the nonuniformity of the crystal grain size of the polycrystalline semiconductor to improve the uniformity of the impurity concentration distribution in the polycrystalline semiconductor and to improve the impurity diffusion in the thermal diffusion process. The present invention provides a method for manufacturing a semiconductor device aiming at improving the uniformity of the impurity concentration distribution in a region and improving the quality.
問題点を解決するための手段 この問題点を解決するために本発明は、半導体基板主面
上に多結晶半導体薄膜を堆積する工程と、多結晶半導体
薄膜中に、表面を非晶質化せずに導電型を決めない原子
をイオン注入する工程と、導電型を決めない原子を含む
半導体薄膜を熱処理する工程と、熱処理された半導体薄
膜中に、導電型を決める原子をイオン注入する工程と、
導電型を決める原子を含む半導体薄膜を熱処理する工程
を有し、半導体薄膜を拡散源として使用し、かつ多結晶
半導体薄膜を構成する原子と導電型を決めない原子とを
同一の原子とする構成となっている。Means for Solving the Problems In order to solve this problem, the present invention provides a step of depositing a polycrystalline semiconductor thin film on the main surface of a semiconductor substrate, and amorphizing the surface in the polycrystalline semiconductor thin film. A step of ion-implanting atoms whose conductivity type is not determined, a step of heat-treating a semiconductor thin film containing atoms whose conductivity type is not determined, and a step of ion-implanting atoms that determine a conductivity type into the heat-treated semiconductor thin film. ,
A structure having a step of heat-treating a semiconductor thin film containing atoms that determine the conductivity type, using the semiconductor thin film as a diffusion source, and making the atoms forming the polycrystalline semiconductor thin film and the atoms not defining the conductivity type the same atom Has become.
作用 本発明の方法により、多結晶半導体の結晶粒の大きさの
不均一性を緩和するために、多結晶半導体薄膜堆積後、
表面を非晶質化せずに導電型を決めない電子をイオン注
入して下層部を非晶質化してから熱処理を行った後、導
電型を決める原子をイオン注入し、再度熱処理すること
によって多結晶半導体薄膜全体の結晶粒を表面の大きな
結晶粒に統一化することで、多結晶半導体内の不純物濃
度分布の均一性を高め熱拡散工程における不純物拡散領
域の不順物濃度分布の良好な均一性を実現した、高歩留
高品質の半導体装置の提供が可能となった。さらには、
表面を非晶質化せずに導電型を決める原子をイオン注入
することにより、より高い均一性を得ることが可能とな
った。By the method of the present invention, in order to reduce the non-uniformity of the crystal grain size of the polycrystalline semiconductor, after the polycrystalline semiconductor thin film deposition,
By ion-implanting electrons that do not determine the conductivity type without making the surface amorphous and making the lower layer amorphous, and then performing heat treatment, ion-implanting atoms that determine the conductivity type and performing heat treatment again By unifying the crystal grains of the whole polycrystalline semiconductor thin film with large crystal grains on the surface, the uniformity of the impurity concentration distribution in the polycrystalline semiconductor is enhanced, and the irregular distribution of impurity concentration in the impurity diffusion region in the thermal diffusion process is excellent and uniform. It has become possible to provide semiconductor devices with high yield and high quality that have realized high reliability. Furthermore,
By implanting atoms that determine the conductivity type without amorphizing the surface, higher uniformity can be obtained.
実施例 以下、本発明の製造方法を多結晶シリコンによる実施例
を参照して詳細に説明する。Examples Hereinafter, the manufacturing method of the present invention will be described in detail with reference to examples using polycrystalline silicon.
半導体基板上に反応温度610℃の減圧CVD法により約3000
Åの多結晶シリコン薄膜を堆積し、この多結晶シリコン
薄膜に加速電圧70kVで1×1015cm-2のシリコンをイオン
注入した。次いでシリコンをイオン注入した多結晶シリ
コン薄膜を窒素雰囲気中で800℃〜1000℃の温度で30分
間熱処理(プリアニール)した。次いでこの多結晶シリ
コン薄膜に加速電圧40kVで1×1015cm-2のボロン、ある
いは加速電圧160kVで1×1016cm-2のヒ素を注入した。
以上の一連の工程によって、所望する不純物拡散源が形
成された。しかる後窒素雰囲気中950℃の温度で30分間
熱処理した。以上の一連の工程によって、所望する不純
物拡散領域が形成された。Approximately 3000 on a semiconductor substrate by the low pressure CVD method with a reaction temperature of 610 ℃
A Å polycrystalline silicon thin film was deposited, and 1 × 10 15 cm -2 of silicon was ion-implanted into the polycrystalline silicon thin film at an acceleration voltage of 70 kV. Then, the polycrystalline silicon thin film in which silicon was ion-implanted was heat-treated (pre-annealed) at a temperature of 800 ° C. to 1000 ° C. for 30 minutes in a nitrogen atmosphere. Next, 1 × 10 15 cm -2 boron was accelerated at an acceleration voltage of 40 kV or 1 × 10 16 cm -2 arsenic was injected at an acceleration voltage of 160 kV into this polycrystalline silicon thin film.
A desired impurity diffusion source was formed by the above series of steps. Then, heat treatment was performed for 30 minutes at a temperature of 950 ° C. in a nitrogen atmosphere. A desired impurity diffusion region was formed by the above series of steps.
一方従来例を示す試料として、半導体基板上に反応温度
610℃の減圧CVD法により約3000Åの多結晶シリコン薄膜
を堆積した後ただちに、この多結晶シリコン薄膜に加速
電圧25kVで1×1015cm-2のボロン、あるいは加速電圧60
kVで1×1016cm-2のヒ素を注入し、しかる後窒素雰囲気
中で950℃の温度で30分間熱処理した。On the other hand, as a sample showing the conventional example, the reaction temperature on the semiconductor substrate
Immediately after depositing a polycrystalline silicon thin film of about 3000 Å by the low pressure CVD method at 610 ° C., immediately after this, the polycrystalline silicon thin film is boron of 1 × 10 15 cm -2 at an accelerating voltage of 25 kV or an accelerating voltage of 60
Arsenic of 1 × 10 16 cm -2 was injected at kV, and then heat treatment was performed for 30 minutes at a temperature of 950 ° C. in a nitrogen atmosphere.
前記試料の不純物濃度分布の均一性を、多結晶シリコン
薄膜上の45点のシート抵抗を測定しその分布の偏差によ
って評価した。第1図に、ボロン注入した試料におけ
る、従来例と本発明の実施例との多結晶シリコン薄膜内
での抵抗値分布の偏差を示す。また第2図にヒ素注入し
た試料における、従来例と本発明の実施例との多結晶シ
リコン薄膜内での抵抗値分布の偏差を示す。何れの場合
においても抵抗値の基板面内での偏差の減少は明らかで
ある。特に1000℃のプリアニールを行ったものは、偏差
が約2分の1から3分の1となっている。The uniformity of the impurity concentration distribution of the sample was evaluated by measuring the sheet resistance at 45 points on the polycrystalline silicon thin film and measuring the deviation of the distribution. FIG. 1 shows the deviation of the resistance value distribution in the polycrystalline silicon thin film between the conventional example and the example of the present invention in the sample implanted with boron. Further, FIG. 2 shows the deviation of the resistance value distribution in the polycrystalline silicon thin film between the conventional example and the example of the present invention in the arsenic-implanted sample. In either case, it is clear that the deviation of the resistance value in the plane of the substrate is reduced. Especially, the deviation after pre-annealing at 1000 ° C is about 1/2 to 1/3.
発明の効果 本発明による製造方法によって、多結晶半導体薄膜の粒
径の不均一性が緩和され、イオン注入した多結晶半導体
薄膜による熱拡散工程における不純物拡散領域の不純物
濃度分布の均一性が改良でき、高歩留高信頼の半導体装
置の提供が可能となる。EFFECTS OF THE INVENTION The manufacturing method according to the present invention can alleviate the non-uniformity of the grain size of the polycrystalline semiconductor thin film and improve the uniformity of the impurity concentration distribution in the impurity diffusion region in the thermal diffusion process by the ion-implanted polycrystalline semiconductor thin film. It is possible to provide a semiconductor device with high yield and high reliability.
第1図は、ボロン注入した試料における、従来例と本発
明の実施例との多結晶シリコン薄膜内での抵抗値分布の
偏差を示す曲線図、第2図は、ヒ素注入した試料におけ
る、従来例と本発明の実施例との多結晶シリコン薄膜内
での抵抗値分布の偏差を示す曲線図である。FIG. 1 is a curve diagram showing a deviation of a resistance value distribution in a polycrystalline silicon thin film between a conventional example and an example of the present invention in a boron-implanted sample, and FIG. 2 is a conventional diagram in an arsenic-implanted sample. It is a curve figure which shows the deviation of the resistance value distribution in a polycrystalline silicon thin film between an example and the Example of this invention.
Claims (2)
積する工程と、前記多結晶半導体薄膜中に、表面を非晶
質化せずに導電型を決めない原子をイオン注入する工程
と、前記導電型を決めない原子を含む半導体薄膜を熱処
理する工程と、前記熱処理された半導体薄膜中に、導電
型を決める原子をイオン注入する工程と、前記導電型を
決める原子を含む半導体薄膜を熱処理する工程を有し、
前記半導体薄膜を拡散源として使用し、かつ前記多結晶
半導体薄膜を構成する原子と前記導電型を決めない原子
とを同一の原子とすることを特徴とする半導体装置の製
造方法。1. A step of depositing a polycrystalline semiconductor thin film on a main surface of a semiconductor substrate, and a step of ion-implanting atoms whose conductivity type is not determined without amorphizing the surface into the polycrystalline semiconductor thin film. A step of heat-treating the semiconductor thin film containing atoms that do not determine the conductivity type; a step of ion-implanting atoms that determine the conductivity type into the heat-treated semiconductor thin film; Has a step of heat treatment,
A method of manufacturing a semiconductor device, wherein the semiconductor thin film is used as a diffusion source, and the atoms constituting the polycrystalline semiconductor thin film and the atoms whose conductivity types are not determined are the same.
て、表面を非晶質化せずにイオン注入することを特徴と
する特許請求の範囲第1項記載の半導体装置の製造方
法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation of atoms that determine the conductivity type is performed without amorphizing the surface.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299436A JPH07120636B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
| US07/374,608 US4954454A (en) | 1986-12-16 | 1989-06-30 | Method for fabricating a polycrystalline silicon resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299436A JPH07120636B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63151018A JPS63151018A (en) | 1988-06-23 |
| JPH07120636B2 true JPH07120636B2 (en) | 1995-12-20 |
Family
ID=17872550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61299436A Expired - Lifetime JPH07120636B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120636B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009123077A (en) * | 2007-11-16 | 2009-06-04 | Nyk Systems Inc | 3D CG object interference check program |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003009534A (en) * | 2001-06-25 | 2003-01-10 | Diamond Electric Mfg Co Ltd | Power factor improvement circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63124520A (en) * | 1986-11-14 | 1988-05-28 | Nec Corp | Manufacture of semiconductor device |
-
1986
- 1986-12-16 JP JP61299436A patent/JPH07120636B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009123077A (en) * | 2007-11-16 | 2009-06-04 | Nyk Systems Inc | 3D CG object interference check program |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63151018A (en) | 1988-06-23 |
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