JPH07120706B2 - Wiring structure of semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a wiring structure of a semiconductor integrated circuit, and more particularly to a transmission wiring with reduced delay and crosstalk in a high density and high speed semiconductor integrated circuit. .

[Conventional technology]

In semiconductor integrated circuits, progress in high density and high speed is remarkable. Recently, as a problem that limits the performance of LSI, the problem of wiring rather than device has been closed up. There are two major problems. The first point is a problem regarding the delay time determined by the product of the wiring resistance and the wiring capacitance. For example, A. Gay Shiina (AKSinha “Speed Limitations due to Intercon
nect Time Constants in VLSI Integrated Circuits. "I
EEE vol.EDL-3, NO.4.Apr.1982.pp90-92.) And others determine the electrical characteristics of wiring by numerical calculation using the two-dimensional Laplace equation. It is reported that the delay time due to the wiring is longer than that of the wiring. Also, KCS Saraswat
swat “Effect of Scaling of Interconnections on the
Time Delay of VLSI Circuits. "IEEE vol.ED−29.No.
4.Apr.1982.pp645-650) also report that the performance of LSI under the 0.50 μm rule is determined by the wiring technology. In order to reduce the delay time due to wiring, studies have been conducted on low-resistance wiring metal materials and low dielectric constant insulating films. However, as a material satisfying the above conditions, from the viewpoint of affinity with the LSI process, that is, adhesion, processability, heat resistance, insulation, reliability, etc.
Materials beyond Al and SiO ₂ films have not yet been developed.
A polyimide film is well known as an insulating film replacing the SiO ₂ film, but the relative dielectric constant of the polyimide film is as high as 3 to 4 depending on its composition. The second point is the problem of crosstalk.
The reason why the crosstalk occurs is that, in the wiring structure formed on the semiconductor substrate 3 as shown in FIG. 5 as an example of the conventional wiring structure, the density is increased and the film thickness c of the wiring 2 and the insulating layer thereunder. When the film thickness a of No. 1 and the film thickness b between the wirings are almost the same, it is particularly likely to occur. The reason is that the inter-wiring capacitance becomes equal to or larger than the ground capacitance of the wiring. A measure of the amount of crosstalk is given by the following equation, as is well known.

C _M / (C _S + C _M ), where C _S is the capacitance to ground and C _M is the inter-wiring capacitance. From this equation, when C _S = C _M , 1/2 of the potential of the induction wire
It can be seen that the electric potential of is induced. One way to reduce the amount of leakage is to reduce the film thickness a of the insulating layer and increase C _S. However, this method is not preferable because it increases the wiring delay. Another method is to reduce the film thickness c of the wiring 2. However, this method is not preferable because the wiring resistance increases and the wiring delay increases. Furthermore, as another method of reducing the crosstalk amount, as in another example of the conventional wiring structure shown in FIG. 6, a method of providing a ground plane 9 made of a metal material on an insulating film covering the wiring is known. is there. The greatest feature of this method is that crosstalk between different wiring layers can be prevented when the wiring is multi-layered. However, this method also increases the wiring capacitance.

[Problems to be solved by the invention]

The conventional wiring structure has a drawback in that it cannot suppress wiring delay and crosstalk that increase with increasing density. Therefore, it is necessary to take measures to reduce the amount of crosstalk while suppressing the wiring delay without lowering the reliability of the wiring due to the higher density.

[Means for solving problems]

The present invention solves the conventional problems, while securing the reliability of wiring equivalent to that of the conventional wiring structure, that is, the adhesiveness with the substrate,
Provided is a transmission wiring structure in which delay and crosstalk amount, which are major problems in a high-density and high-speed semiconductor integrated circuit, are reduced, and in a wiring structure including a plurality of wirings arranged on a semiconductor substrate forming a semiconductor integrated circuit. A convex portion formed of the first insulating layer on the semiconductor substrate, a wiring formed on the convex portion for each convex portion, and at least a side surface of the wiring and a side surface of the convex portion between the wiring. A second insulating layer having a relative permittivity smaller than that of the first insulating layer and partially covering the first insulating layer.

[Action]

The conventional wiring structure uses an insulating layer having a single dielectric constant. On the other hand, the present invention is characterized mainly in that the first insulating layer below the wiring and the second insulating layer embedded between the wirings have different relative dielectric constants. By making the relative permittivity of the insulating layer between the wirings smaller than the relative permittivity of the insulating layer, the capacitance between the wirings is reduced, the delay time is reduced, and the ratio of the capacitance between the wirings to the ground capacitance is reduced to cause crosstalk. It is significantly different from the conventional technology in that it is difficult. In the present invention, since the adhesiveness between the wiring layer and the substrate is ensured by the insulating material of the insulating layer below the wiring layer, the requirements for the adhesiveness between the insulating material embedded between the wiring layers and the wiring layer are It is relaxed, allowing the selection of low dielectric constant materials from a wider range of materials. Embodiments will be described below with reference to the drawings.

〔Example〕

A first embodiment of the wiring structure of the present invention is shown in FIG. First
The figure shows a wiring structure in which the periphery of the wiring 6 on the semiconductor substrate 4 is formed of insulating layers 5 and 7. The dielectric constant of the insulating layer 7 is equal to that of the insulating layer 5.
Is smaller than the relative dielectric constant of. In the present invention, an Al wiring is used as the wiring 6, a proven SiO ₂ layer as the insulating layer 5, and a low dielectric constant such as polytetrafluoroethylene (-[CF ₂ CF ₂ ]-) or polyethylene as the insulating layer 7. Apply high polymer material. As insulating layer 5
The relative permittivity of the SiO ₂ layer is 3.9, and the relative permittivities of polytetrafluoroethylene and polyethylene as the insulating layer 7 are about 2.1 and 2.2, respectively. Therefore, even if the film thickness of the insulating layer 5 under the wiring and the dimension between the wirings are equal or the dimension between the wirings is smaller, the capacitance between the wirings is made smaller than the ground capacitance of the wirings. be able to. That is, the present wiring structure has the same adhesiveness between the wiring layer and the substrate as that of the conventional wiring structure, and is a structure in which crosstalk is unlikely to occur even when the wiring is mounted at a high density. In the structure of FIG. 1, when the present invention is applied to the case where the insulating film thickness a, the wiring layer distance b, and the wiring layer thickness c under the wiring are the same, when compared with the case where only SiO ₂ is used as the insulating layer, Both capacity and crosstalk are reduced by 25% to 33%.

Next, a second embodiment of the wiring structure of the present invention is shown in FIG. In the second embodiment, as shown in FIG. 2, a wiring structure in which insulating layers 5, 7, 8 are formed around the wiring 6 and a ground plane 9 made of a metal material is further formed on the insulating layers 7, 8. Is. The relative dielectric constant of the insulating layer 7 is smaller than that of the insulating layers 5 and 8. Compared with the structure having the conventional ground plane, this structure not only reduces the total wiring capacitance, but also reduces the ratio of the capacitance between the wirings to the ground capacitance and reduces the crosstalk between the wirings.

Hereinafter, some specific examples provided with the wiring structure of the present invention will be described by illustrating the manufacturing method. First, some specific examples provided with the wiring structure of the first embodiment are shown in FIGS. 3 (a) to 3 (c). FIG. 3A shows the material of the wiring 6 deposited on the insulating film 5 formed on the semiconductor substrate 4. In this embodiment, as the insulating film 5, a SiO ₂ film of 0.5 μm is deposited by the CVD method. As a method of depositing this insulating film, C
In addition to the VD method, there are spattering methods, plasma CVD methods, spin-on methods, etc., and it goes without saying that any of them can be realized. As a wiring material, the specific resistance is 2.9 x 10
^{We used} Al, which has a small size of ^-6 Ω-cm and is compatible with the LSI process. Al is 0.5μ by the sputtering method
m deposited. As a method of depositing the wiring material, there are a vapor deposition method, a CVD method, a plasma CVD method and the like other than the sputtering method, but it goes without saying that any of them can be realized. Third
FIG. 2B shows that the resist pattern is formed by the lithographic process, and then the materials of the insulating layer 5 and the wiring 6 are simultaneously etched by dry etching.
In the present invention, a two-layer resist of SNR (silicone negative resist) / AZ resist is used as a resist for forming a fine pattern. Resist film thickness is 0.15 SNR
μm, AZ resist is 1.0 μm. Lithographies EB
By drawing method, after pattern formation, develop SNR,
Then etch the AZ resist using O ₂ plasma,
Next, dry etch Al with CCl ₄ , and then add CF ₄ and H ₂
To etch SiO ₂ . In the embodiment of FIG. 3 (b), the insulating layer 5 is completely removed by etching by the film thickness, but the etching may be stopped halfway. In FIG. 3 (c), an insulating layer 7 having a relative dielectric constant smaller than that of the insulating layer 5 is buried. As a method of burying the insulating layer,
There are plasma polymerization method, spin-on method, and vapor deposition method. In this example, polytetrafluoroethylene (-
[CF ₂ CF ₂ ]-) was applied by a spin-on method and baked to be embedded. Polytetrafluoroethylene (-[CF ₂ CF ₂ ]-) has a relative dielectric constant of 2.1 (1MH
z), heat resistance of 300 ℃, polyethylene heat resistance (200
It is higher than that of the material of the present invention and is more suitable for the purpose of the present invention.

Next, FIGS. 4A to 4D show some specific examples provided with the wiring structure of the second embodiment of the present invention. FIG. 4A shows that the insulating layer 5 is deposited on the semiconductor substrate 4, and then the material of the wiring 6 and the insulating layer 8 are successively deposited.
In this embodiment, the insulating layers 5 and 8 have a film thickness of 0.5 μm formed by the CVD method.
m of SiO ₂ film, and Al of 0.5 μm in film thickness by the sputtering method was used as the wiring material. FIG. 4 (b) shows the SN pattern of the SNR / Az two-layer resist similar to that of the first embodiment.
After R development, the Az resist is etched by O ₂ plasma to form a pattern, and then the upper SiO ₂ layer is exposed in CF ₄ and H ₂ atmosphere.
Etching the insulating layer 8 consisting of, then etching the wiring layer 6 consisting of Al with CCl ₄ , then etching the underlying insulating layer 5 consisting of SiO _{2 in an} atmosphere of CF ₄ and H ₂ , and then two layers. The resist is removed. FIG. 4 (c) shows that the insulating layer 7 is embedded between the lines in the same manner as in the first embodiment. FIG. 4 (d) shows a structure in which the surface is flat by performing etching using Ar sputtering.
FIG. 4 (e) shows a deposited ground plane 9 made of a metallic material. In this embodiment, Al is deposited by 0.2 μm by the sputtering method.

〔The invention's effect〕

When the wiring structure of the present invention is applied when the thickness of wiring layers, the distance between wirings, and the distance between wirings and the substrate are all equal, polytetrafluoroethylene having a relative dielectric constant of 2.1 is used as the insulating layer 7.
By using SiO ₂ having a relative dielectric constant of 3.9 as the insulating layer 5, while securing the adhesiveness to the same substrate as the conventional structure, compared to the conventional structure in which all the insulating layers are SiO ₂ , both the total wiring capacitance and the crosstalk amount are It can be reduced by about 30%.

In addition, in a structure in which a ground plane for preventing crosstalk between upper and lower wiring layers is present when the wiring is a wiring structure of one embodiment of the present invention, polytetrafluoro with a relative permittivity of 2.1 is used as the insulating layer 7. By using ethylene as the insulating layers 5 and 8 and SiO ₂ to reduce the relative permittivity of the insulating layer 7 to about 1/2 of the relative permittivity of the insulating layers 5 and 8, the Al ground plane is made the upper layer. Since the wiring capacitance increased due to the provision is reduced, the ratio of the inter-wiring capacitance to the ground capacitance can be further reduced, and the crosstalk amount can be further reduced.

As described above, the present invention solves the problems of delay and crosstalk in wiring that affect the performance of VLSIs according to the submicron rule.

[Brief description of drawings]

FIG. 1 is a first embodiment of the wiring structure of the present invention, FIG. 2 is a second embodiment of the wiring structure of the present invention, and FIGS. 3 (a) to (c) are the first embodiment of the present invention. A specific example having the wiring structure of the example, FIGS. 4A to 4E are specific examples having the wiring structure of the second embodiment of the present invention, and FIG. 5 is an example of a conventional wiring structure. FIG. 6 shows another example of the conventional wiring structure. 1 ... Insulating layer 2 ... Wiring 3 ... Semiconductor substrate 4 ... Semiconductor substrate 5 ... Insulating layer (large relative permittivity) 6 ... Wiring 7 ... Insulating layer (small relative permittivity) 8 ... Insulating layer (Large relative permittivity) 9 …… Ground plane

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 58-123753 (JP, A) JP 60-224229 (JP, A) JP 60-51262 (JP, B1)

Claims (1)

[Claims] 1. A wiring structure including a plurality of wirings arranged on a semiconductor substrate forming a semiconductor integrated circuit, wherein a convex portion formed of a first insulating layer formed on the semiconductor substrate, and a convex portion on the convex portion. , A wiring formed for each convex portion, and a relative dielectric constant smaller than that of the first insulating layer with a shape that covers at least a side surface of the wiring and a part of a side surface of the convex portion between the wirings. A wiring structure of a semiconductor integrated circuit, comprising: a second insulating layer having the same.