JPH07121402A - Tracing device for program - Google Patents

Abstract

PURPOSE:To provide a program tracing device which can deal even with the cases where the operating ferquencies of a microcomputer and the like are different. CONSTITUTION:The tracing device 1 is provided with a first buffer 11 and a second buffer 12, which store data, a tracing memory 2 storing data stored in the selected buffer, a counter 3 indicating an address and a signal control part 4 generating a selection signal, a write signal and a count control signal based on a basic timing signal 10. The signal control part 4 is provided with a delay circuit 41 generating plural delay signals with the input of one basic timing signal 10 as a trigger and a control circuit 42 generating the selection signal, the write signal and the count control signal by using the delay signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program trace device for tracing and checking the execution state of a program incorporated in a microcomputer.

[0002]

2. Description of the Related Art A debugging device for verifying whether a program incorporated in a microcomputer or the like is executed correctly includes a function for displaying / changing the contents of memory and a so-called trace for tracing the history of execution of the program. Functions are provided. Of these, the trace device for performing the trace function has a configuration as shown in the block diagram of FIG.

That is, the trace device 1 mainly stores a trace memory 2 for storing data (for example, data I and data II) from a microcomputer that executes a program, and an address of the trace memory 2 for storing the data. A counter 3 for designating whether or not to execute, and a buffer for storing data (first buffer 1 in the figure)
1 buffer and a second buffer 12) and a signal controller 4 for controlling these. By using the trace device 1 as described above, the data of each instruction is written to the designated address of the trace memory 2 during the execution of the program, and the execution history is traced by referring to the contents of the trace memory 2 after the execution of the program. ing.

In the trace device 1, the storage timing of data I and data II is controlled by a plurality of basic timing signals 10 output from a microcomputer. That is, O of the basic timing signals 10a and 10b
The R signal 4a is connected to the trace memory 2 and the second buffer 12, and its inverted signal is connected to the first buffer 11.

As a result, when the data I stored in the first buffer 11 or the data II stored in the second buffer 12 is switched, the upper space and the lower space (upper space) of the trace memory 2 are stored. In each space when divided into two areas, that is, a lower address and a lower address, for example, 0H to 0FFFH and 100.
Selection of each space when divided into high-order addresses from 0H to 1FFFH) is made.

Also, the basic timing signals 10e and 10f
Data I and data II based on the OR signal 4b with
Writing to the trace memory 2 is controlled. Figure 4
3 is a timing chart in the trace device 1, based on which the writing of data I and data II into the trace memory 2 and the count-up of the counter 3 are controlled.

That is, when the basic timing signal 10a or 10b is being output, the signal 4a to the trace memory 2 becomes High Level (hereinafter referred to as "H"), and the upper space of the trace memory 2 is selected.
At the same time, the Low Level is sent to the first buffer 11.
Since the signal (hereinafter, referred to as “L”) is input, the first buffer 11 is selected and the data I stored therein is output to the trace memory 2 side. Then, when the signal 4b is "L" at the time of this output (see A in FIG. 4), the data I is written in the trace memory 2.

On the other hand, the basic timing signal 10c or 1
When 0d is output, the signal 4a to the trace memory 2 is "L", so the lower space of the trace memory 2 is selected. At this time, since the "H" signal is input to the second buffer 12, the second buffer 12 is selected and the data II stored therein is output to the trace memory 2 side. When the signal 4b is "L" at the time of this output (see B in FIG. 4), the data II is written in the trace memory 2.

When the writing of the two data I and data II is completed and the basic timing signal 10d becomes "L", the signal 10d / becomes "H" and the counter 3 is counted up. By repeating this, two data I and data II can be stored in one trace memory 2 in a time division manner.

[0010]

However, such a program tracing device has the following problems. That is, since the trace device controls the storage of data based on a plurality of basic timing signals,
When the operation of the microcomputer is speeded up and the signal width of the basic timing signal is reduced or the signal output is reduced, it is necessary to use a complicated circuit to cope with this. Further, since the circuit for generating the basic timing signal differs depending on the type of microcomputer, it is difficult to unify the circuits of the trace device. Therefore, it is an object of the present invention to provide a program trace device capable of coping with the case where the operating frequency of the microcomputer is different.

[0011]

SUMMARY OF THE INVENTION The present invention is a program tracing device that is designed to solve such problems. That is, the trace device has a plurality of buffers for sequentially storing a plurality of data output from the microcomputer when the program is executed, and a predetermined amount of data stored in a selected one of the buffers. A trace memory to be stored at an address, a counter for instructing the address at which data is stored to the trace memory, a selection signal for selecting one of a plurality of buffers based on a basic timing signal, and a trace memory And a signal control section for generating a count control signal for the counter, and the signal control section has different delay times triggered by the input of one basic timing signal. A delay circuit that generates a plurality of delay signals and the plurality of delays And it constitutes a control circuit for generating respective select signals, the write signals and count control signals using a No..

[0012]

With the delay circuit provided in the signal control unit, a plurality of delay signals having different delay times can be obtained by using one basic timing signal input as a trigger.
It is possible to obtain a control signal that does not depend on the operation speed of the microcomputer or the number of outputs of the basic timing signal. In addition, the control circuit provided in the signal control unit uses one of the plurality of delay signals from the delay circuit,
Further, it becomes possible to generate a selection signal, a write signal, and a count control signal by combining a plurality of them to store data in a trace memory in a time division manner.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a program trace device of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a trace device of the present invention, and FIG. 2 is a timing chart of the trace device of the present invention.

As shown in FIG. 1, the trace device 1 stores the data output by the execution of a program in a microcomputer in a memory, and refers to the data in the memory after the end of the program to record the operation history. The main configuration is, for example, a first buffer 11 and a second buffer 12 that sequentially store two types of data, data I and data II, and these data I.
And a trace memory 2 for storing data II,
It is composed of a counter 3 for instructing an address to be stored and a signal controller 4 for controlling various signals.

Further, the signal control section 4 generates a signal A by using, for example, one basic timing signal 10 output from a microcomputer as a trigger, and further outputs signals B to J whose generation points are delayed by a constant interval. It is composed of a circuit 41 and a control circuit 42 which generates various control signals by using these signals A to J.

The delay circuit 41 is composed of a delay element 43 and a predetermined flip-flop 44. One basic timing signal 10 is input to the flip-flop 44 to output a signal A, and the signal A is delayed by the delay element 43. To the delay signals B to J based on the signal A.

Next, the signal control of the trace device 1 will be described with reference to FIG. This basic timing signal 10
Is a pulse signal having a constant width at a constant interval and is one of those output from a microcomputer, for example. This basic timing signal 10 is shown in FIG.
When the signal is input to the flip-flop 44 of the delay circuit 41 shown in (4), the signal A becomes “L” with its rising as a trigger, and this signal A is input to the delay element 43. That is, the signal A is output based on the rising edge of the basic timing signal 10 regardless of the signal width thereof.

Upon receiving the signal A, the delay element 43 sequentially outputs the signals B to J which become "L" at a constant delay interval. Further, the flip-flop 44 is adapted to be reset when the signal CF, which is the AND signal of the signals C and F from the delay element 43, becomes “L”, which causes the signal A to be “H”. Is input to the delay element 43, and the signals B to J sequentially become “H”. That is, the signal widths of the signals A to J are determined by the combination of the delay signals from the delay element 43 regardless of the signal width of the basic timing signal 10 and the signal speed.

The signals A to J are output from the delay circuit 41, and the signals A, G, H, and I among them are input to the control circuit 42. The control circuit 42 is composed of two OR gates, and the signal G and the signal I are input to one of the OR gates. Also, the other OR
The signal A and the signal H are input to the gate.

The output signal 42a from one OR gate is input to the first buffer 11 and the second buffer 12, and, for example, when the output signal 42a is "H", "1" is output to the first buffer 11. "L" is input and this is selected. When the output signal 42a is "L", "L" is input to the second buffer 12 and is selected. That is, the output signal 42a controls whether the first buffer 11 or the second buffer 12 is selected.

Further, the output signal 42b from the other OR gate of the control circuit 42 is input to the trace memory 2, and when the output signal 42b becomes "L", writing is performed. That is, when the signal A is "L" (marked with a circle in FIG. 2) or when the signal H is "L" (marked with a triangle in FIG. 2), the output signal 42b becomes "L" and is selected at each time point. Buffers (first buffer 1
The data I or the data II stored in the first or second buffer 12) is written to a predetermined address of the trace memory 2.

That is, when the signal A is "L", the first buffer 11 is selected, and when this and the output signal 42b are "L" (portion A in FIG. 2). The data I in the first buffer 11 is written in the trace memory 2. On the other hand, when the signal H is “L”, the second buffer 12 is selected, and this and the output signal 4
2B and "L" (B portion in FIG. 2), the data II of the second buffer 12 is written to the trace memory 2.

Further, the first buffer 11 and the second buffer 1
The output signal 42a for selecting 2 is input to the most significant bit of the trace memory 2 and selects the upper space or the lower space. That is, when the output signal 42 a is “H”, the first buffer 11 is selected, and the most significant bit of the trace memory 2 is input to “L” to select the lower space and the trace memory 2 is selected. The data I is written in the address of the lower space. On the other hand, when the output signal 42a is "L", the second
The buffer 12 is selected, "H" is input to the most significant bit of the trace memory 2, the upper space is selected, and the data II is written to the address of the upper space of the trace memory 2.

The signal J from the delay element 43 is input to the counter 3 for instructing the address to the trace memory 2. The signal J is the signal that rises at the end of the delayed signal, and this is "H" as shown by the arrow in FIG.
Then, the counter 3 is incremented. That is, every time the data I and the data II are written in the trace memory 2, the counter 3 counts up, and the next address is designated at the time of the next writing.

By repeating the series of operations up to this point, the data I and the data II can be sequentially written into the trace memory 2 based on one basic timing signal, and the written contents are referred to after the execution of the program is completed. By doing so, you will be able to track the program.

In this embodiment, two types of data output from the microcomputer, i.e., data I and data II, are used, and buffers for storing the respective data are first buffer 11 and second buffer 12. However, the present invention is not limited to this. Further, since various signals are generated by using the input of one basic timing signal 10 as a trigger, any signal other than the basic timing signal 10 output from the microcomputer may be used as long as it is linked to the microcomputer. Can also be used as the basic timing signal 10.

[0027]

As described above, the program tracing device of the present invention has the following effects. That is, since a delay signal is generated by using one basic timing signal input as a trigger and various signals are controlled using this delay signal, the operation of the microcomputer is speeded up and the signal width of the basic timing signal is increased. Decrease,
Even if the signal output decreases, the data can be surely written in the trace memory. Also, since it is sufficient to input one basic timing signal, no special timing is required, and it is possible to support even microcomputers with different operating frequencies, output timings, etc., and to unify the circuits of the trace device. Is possible.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a trace device of the present invention.

FIG. 2 is a timing chart in the trace device of the present invention.

FIG. 3 is a block diagram illustrating a conventional trace device.

FIG. 4 is a timing chart in a conventional trace device.

[Explanation of symbols]

 1 Trace Device 2 Trace Memory 3 Counter 4 Signal Control Unit 10 Basic Timing Signal 11 First Buffer 12 Second Buffer 41 Delay Circuit 42 Control Circuit 43 Delay Element 44 Flip Flop

Claims (1)

[Claims] 1. A plurality of buffers for sequentially storing a plurality of data output from a microcomputer by executing a program, and data stored in a selected one of the plurality of buffers at a predetermined address. To the trace memory, a counter for indicating the address to the trace memory, a selection signal for selecting one of the plurality of buffers based on a basic timing signal, and the trace memory In a tracing device of a program, which comprises a write signal for instructing writing of the data and a signal control unit for generating a count control signal for the counter, the signal control unit uses the input of one basic timing signal as a trigger for delay time. A delay circuit for generating a plurality of different delay signals, The selection signal, the trace device program characterized by comprising the write signal and said count control signal from a control circuit for generating respectively, using a delay signal.